#13 Refactor PCBWay rules to mirror JLCPCB structure

[Cimos]

Closes #13.

Brings PCBWay.kicad_dru up to the same structure JLCPCB.kicad_dru has been using since #12 was merged.

What changed

Bug fixes

• Conditions converted from lowercase 'track'/'via'/'pad' to PascalCase 'Track'/'Via'/'Pad' (KiCad 8 convention; the old form would silently never match in some places).
• "Pad Size" rule was applying hole_size (min 0.5mm) to all plated pads including SMD. Split into PCBWay: PTH Hole Size (PTH only) and PCBWay: PTH Annular Ring.
• "pad to pad clearance (without hole, different nets)" was missing the A.Net != B.Net test — the rule name said different nets but the condition would have flagged same-net pad pairs.

Added rules (backed by PCBWay's published spec)

• PCBWay: Via Annular Ring — 0.15mm, per "Annular Ring (Pad Ring Width) Standard: 0.15mm(6mil)" on https://www.pcbway.com/capabilities.html
• PCBWay: PTH Annular Ring — split out from the old combined Pad Size rule
• PCBWay: NPTH Annular Ring — split out, value preserved (0.25mm)
• PCBWay: Plated Slot Width / Non-Plated Slot Width — pulled out into their own section
• PCBWay: NPTH to Copper (non-Track) — preserves the old "NPTH with copper around" rule, renamed for clarity

Structure

• Header doc block matching JLCPCB
• Section dividers and naming match JLCPCB exactly so users mixing both fabs see consistent DRC output
• "Choose between" comment blocks preserved for layer count / copper weight variants

Not done in this PR

• Add PCBWay PCB Test cases #16 (PCBWay test PCB) — the rule file is correct and ready, but adding a test footprint per rule needs to happen in KiCad's PCB editor and is best done as a separate PR.
• Rule tightening to PCBWay's actual published minimums (e.g. 0.1mm trace standard vs current 0.127mm). Conservative defaults preserved deliberately so this PR doesn't change DRC behaviour for existing users — only adds the missing rules.