ARM32 assembly: Get CPU Id flags to choose assembly.

Added flag determination for Linux/Android/BSD/Windows/privilege-mode.
Made AES and SHA-256 runtime dispatch.
Updated the ARM32 assembly to support having multiple implementations compiled
in.

Author: SparkiDev

.wolfssl_known_macro_extras

@@ -785,6 +785,8 @@ WOLFSSL_ALLOW_SERVER_SC_EXT
 WOLFSSL_ALLOW_TLS_SHA1
 WOLFSSL_ALTERNATIVE_DOWNGRADE
 WOLFSSL_ALT_NAMES_NO_REV
+WOLFSSL_ARM32_BUILD
+WOLFSSL_ARM32_PRIVILEGE_MODE
 WOLFSSL_ARMASM_NEON_NO_TABLE_LOOKUP
 WOLFSSL_ARM_ARCH_NEON_64BIT
 WOLFSSL_ASCON_UNROLL

configure.ac

@@ -3917,10 +3917,12 @@ ENABLED_ARMASM_INLINE="no"
 ENABLED_ARMASM_SHA256_SMALL="no"
 ENABLED_ARMASM_SHA3="unknown"
 ENABLED_ARMASM_CRYPTO_SM4="no"
+ENABLED_ARMASM_NO_BASE_IMPL="no"
+ENABLED_ARMASM_NO_NEON_IMPL="no"
 # ARM Assembly
 # Both SHA3 and SHA512 instructions available with ARMV8.2-a
 AC_ARG_ENABLE([armasm],
-    [AS_HELP_STRING([--enable-armasm],[Enable wolfSSL ARMv8 ASM support (default: disabled). Set to sha512-crypto or sha3-crypto to use SHA512 and SHA3 instructions with Aarch64 CPU.])],
+    [AS_HELP_STRING([--enable-armasm],[Enable wolfSSL ARMv8 ASM support (default: disabled). Set to sha512-crypto or sha3-crypto to use SHA512 and SHA3 instructions with Aarch64 CPU. On 32-bit ARM, no-base and no-neon-impl drop the base/NEON run-time fallbacks when the crypto extension is always present.])],
     [ ENABLED_ARMASM=$enableval ],
     [ ENABLED_ARMASM=no ]
     )
@@ -4025,13 +4027,33 @@ then
             esac
             ENABLED_ARMASM_AES_BLOCK_INLINE=yes
             ;;
+        no-base)
+            case $host_cpu in
+            *arm*)
+                ;;
+            *)
+                AC_MSG_ERROR([no-base option only available on 32-bit ARM CPU.])
+                break;;
+            esac
+            ENABLED_ARMASM_NO_BASE_IMPL=yes
+            ;;
+        no-neon-impl)
+            case $host_cpu in
+            *arm*)
+                ;;
+            *)
+                AC_MSG_ERROR([no-neon-impl option only available on 32-bit ARM CPU.])
+                break;;
+            esac
+            ENABLED_ARMASM_NO_NEON_IMPL=yes
+            ;;
         *)
             case $host_cpu in
             *aarch64*)
                 AC_MSG_ERROR([Invalid choice of ARM asm inclusions (yes, inline, no-crypto, sha512-crypto, sha3-crypto, no-sha512-crypto, no-sha3-crypto, barrier-sb, barrier-detect): $ENABLED_ARMASM.])
                 break;;
             *arm*)
-                AC_MSG_ERROR([Invalid choice of ARM asm inclusions (yes, inline, no-crypto, sha256-small, aes-block-dup): $ENABLED_ARMASM.])
+                AC_MSG_ERROR([Invalid choice of ARM asm inclusions (yes, inline, no-crypto, sha256-small, aes-block-dup, no-base, no-neon-impl): $ENABLED_ARMASM.])
                 break;;
             esac
             break;;
@@ -4194,6 +4216,17 @@ if test "$ENABLED_ARMASM_NEON" = "no"; then
     AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_ARMASM_NO_NEON"
     AM_CCASFLAGS="$AM_CCASFLAGS -DWOLFSSL_ARMASM_NO_NEON"
 fi
+# 32-bit ARM run-time dispatch: drop a fallback implementation when the crypto
+# extension is always present.  Gates both the C dispatch and the generated
+# assembly, so define for the C and assembler flags.
+if test "$ENABLED_ARMASM_NO_BASE_IMPL" = "yes"; then
+    AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_ARMASM_NO_BASE_IMPL"
+    AM_CCASFLAGS="$AM_CCASFLAGS -DWOLFSSL_ARMASM_NO_BASE_IMPL"
+fi
+if test "$ENABLED_ARMASM_NO_NEON_IMPL" = "yes"; then
+    AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_ARMASM_NO_NEON_IMPL"
+    AM_CCASFLAGS="$AM_CCASFLAGS -DWOLFSSL_ARMASM_NO_NEON_IMPL"
+fi
 
 if test "$ENABLED_ARMASM_INLINE" = "yes"; then
     AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_ARMASM_INLINE"