dxa: size smem address datapath to LMEM byte-address width

The DXA shared-memory (LMEM) byte address was carried as
VX_CFG_MEM_ADDR_WIDTH (48b on XLEN=64) — the global-memory width — even
though it only ever indexes one core's LMEM. Introduce
DXA_SMEM_ADDR_W = VX_CFG_LMEM_LOG_SIZE (the LMEM byte-address width, same
as VX_local_mem's ADDR_WIDTH) and use it across the whole smem datapath:
dxa_req_data_t.smem_addr, dxa_setup_params_t.initial_smem_base, setup's
r_/s_initial_smem_base, addr_gen's smem_byte_addr_r/km_row_base_r and
out_smem_byte_addr, worker's ag_/sw_smem_byte_addr and the gmem_req
SMEM_ADDR_W param, and smem_wr's pend_/defer_/fb_byte_addr_r and
fb_load_smem_byte_addr. The unit producer slices the LMEM-relative
address to DXA_SMEM_ADDR_W; UNUSED_VAR covers the LMEM-bounded upper bits
of km_step_in_row and per_lane_stride_bytes. GMEM addresses and the
already-tight LMEM word-address internals are unchanged. Elaborates clean
on build64.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>

Author: tinebp

hw/rtl/dxa/VX_dxa_addr_gen.sv

@@ -36,7 +36,7 @@ module VX_dxa_addr_gen import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
     output wire                        out_valid,
     input  wire                        out_ready,
     output wire [GMEM_ADDR_WIDTH-1:0]  out_cl_addr,
-    output wire [`VX_CFG_MEM_ADDR_WIDTH-1:0]  out_smem_byte_addr,
+    output wire [DXA_SMEM_ADDR_W-1:0]  out_smem_byte_addr,
     output wire [CL_OFF_BITS-1:0]      out_byte_offset,
     output wire [CL_OFF_BITS:0]        out_valid_length,
     output wire                        out_oob,
@@ -65,15 +65,15 @@ module VX_dxa_addr_gen import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
     reg [DXA_MAX_OUTER_DIMS-1:0][31:0] oob_limit_r;   // OOB limit per dim
 
     // SMEM byte address tracking.
-    reg [`VX_CFG_MEM_ADDR_WIDTH-1:0]  smem_byte_addr_r;
+    reg [DXA_SMEM_ADDR_W-1:0]  smem_byte_addr_r;
     // K-major scatter-mode state.
     //   km_row_base_r: SMEM base for the current outer-dim row (= initial +
     //                  dim_count[0] * elem_bytes). Updates only at row wrap.
     //   km_dest_kmajor_r / km_per_lane_stride / km_elem_bytes: stable params.
     reg                        km_dest_kmajor_r;
     reg [15:0]                 km_per_lane_stride_r;
     reg [3:0]                  km_elem_bytes_r;
-    reg [`VX_CFG_MEM_ADDR_WIDTH-1:0]  km_row_base_r;
+    reg [DXA_SMEM_ADDR_W-1:0]  km_row_base_r;
 
     // Pass-through latched params.
     reg [31:0]                 cfill_r;
@@ -181,11 +181,11 @@ module VX_dxa_addr_gen import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
             row_len_r        <= setup_params.row_len_bytes;
             line_idx_r       <= '0;
             cfill_r          <= setup_params.cfill;
-            smem_byte_addr_r <= `VX_CFG_MEM_ADDR_WIDTH'(setup_params.initial_smem_base);
+            smem_byte_addr_r <= setup_params.initial_smem_base;
             km_dest_kmajor_r <= setup_params.dest_kmajor;
             km_per_lane_stride_r <= setup_params.per_lane_stride_bytes;
             km_elem_bytes_r  <= setup_params.elem_bytes;
-            km_row_base_r    <= `VX_CFG_MEM_ADDR_WIDTH'(setup_params.initial_smem_base);
+            km_row_base_r    <= setup_params.initial_smem_base;
             for (int d = 0; d < DXA_MAX_OUTER_DIMS; d++) begin
                 dim_count_r[d] <= '0;
                 dim_tile_r[d]  <= setup_params.dim_tiles[d];
@@ -200,9 +200,9 @@ module VX_dxa_addr_gen import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
             //              layout). On row wrap, the address is overridden
             //              below to the next column's row base.
             if (km_dest_kmajor_r) begin
-                smem_byte_addr_r <= smem_byte_addr_r + `VX_CFG_MEM_ADDR_WIDTH'(km_step_in_row);
+                smem_byte_addr_r <= smem_byte_addr_r + DXA_SMEM_ADDR_W'(km_step_in_row);
             end else begin
-                smem_byte_addr_r <= smem_byte_addr_r + `VX_CFG_MEM_ADDR_WIDTH'(cur_valid_length);
+                smem_byte_addr_r <= smem_byte_addr_r + DXA_SMEM_ADDR_W'(cur_valid_length);
             end
 
             if (is_last_line && is_last_outer) begin
@@ -218,8 +218,8 @@ module VX_dxa_addr_gen import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
                 // cursor — the override above is unconditional, so it would
                 // step PAST the row base; we restore it here for K-major.
                 if (km_dest_kmajor_r) begin
-                    smem_byte_addr_r <= km_row_base_r + `VX_CFG_MEM_ADDR_WIDTH'(km_elem_bytes_r);
-                    km_row_base_r    <= km_row_base_r + `VX_CFG_MEM_ADDR_WIDTH'(km_elem_bytes_r);
+                    smem_byte_addr_r <= km_row_base_r + DXA_SMEM_ADDR_W'(km_elem_bytes_r);
+                    km_row_base_r    <= km_row_base_r + DXA_SMEM_ADDR_W'(km_elem_bytes_r);
                 end
                 if (dim0_steps) begin
                     dim_count_r[0] <= dim_count_r[0] + 1;
@@ -245,7 +245,8 @@ module VX_dxa_addr_gen import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
 
     `UNUSED_VAR (cur_cl_byte_addr[CL_OFF_BITS-1:0])
     `UNUSED_VAR (total_end[31:CL_OFF_BITS])
-    `UNUSED_VAR (setup_params.initial_smem_base)
+    // km_step_in_row is LMEM-bounded; only the low DXA_SMEM_ADDR_W bits feed smem_byte_addr_r.
+    `UNUSED_VAR (km_step_in_row[31:DXA_SMEM_ADDR_W])
 
 `ifdef DBG_TRACE_DXA
     always @(posedge clk) begin

hw/rtl/dxa/VX_dxa_gmem_req.sv

@@ -29,7 +29,7 @@ module VX_dxa_gmem_req import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
     parameter GMEM_ADDR_WIDTH = `VX_CFG_MEM_ADDR_WIDTH - `CLOG2(`VX_CFG_L1_LINE_SIZE),
     parameter GMEM_TAG_WIDTH  = L1_MEM_ARB_TAG_WIDTH,
     parameter CL_OFF_BITS     = `CLOG2(`VX_CFG_L1_LINE_SIZE),
-    parameter SMEM_ADDR_W     = `VX_CFG_MEM_ADDR_WIDTH
+    parameter SMEM_ADDR_W     = DXA_SMEM_ADDR_W
 ) (
     input  wire                        clk,
     input  wire                        reset,

hw/rtl/dxa/VX_dxa_pkg.sv

@@ -24,6 +24,10 @@ package VX_dxa_pkg;
     localparam DXA_LMEM_WORD_SIZE = `VX_CFG_LMEM_NUM_BANKS * (`VX_CFG_XLEN / 8);
     localparam DXA_LMEM_ADDR_W = LMEM_DMA_ADDR_WIDTH;
 
+    // LMEM byte-address width: an LMEM-relative byte offset, same as
+    // VX_local_mem's ADDR_WIDTH = `CLOG2(SIZE) = `VX_CFG_LMEM_LOG_SIZE.
+    localparam DXA_SMEM_ADDR_W = `VX_CFG_LMEM_LOG_SIZE;
+
     localparam DXA_DESC_SLOT_BITS = `CLOG2(`VX_DCR_DXA_DESC_COUNT);
     localparam DXA_DESC_SLOT_W    = `UP(DXA_DESC_SLOT_BITS);
 
@@ -32,7 +36,7 @@ package VX_dxa_pkg;
         logic [NC_WIDTH-1:0]      core_id;
         logic [UUID_WIDTH-1:0]    uuid;
         logic [NW_WIDTH-1:0]      wid;
-        logic [`VX_CFG_XLEN-1:0]         smem_addr;   // from lane 0 rs1
+        logic [DXA_SMEM_ADDR_W-1:0]      smem_addr;   // from lane 0 rs1; LMEM byte address
         logic [31:0]                     meta;        // from lane 1 rs1 (desc[3:0], bar[30:4], 1[31]); 32-bit ABI word
         logic [4:0][31:0]                coords;      // [0]=lane2.rs1,[1]=lane3.rs1,[2]=lane0.rs2,[3]=lane1.rs2,[4]=lane2.rs2; element indices, 32-bit ABI
         logic [`VX_CFG_NUM_WARPS-1:0]    cta_mask;     // from rs2 lane 3
@@ -67,7 +71,7 @@ package VX_dxa_pkg;
     // All multiplies happen during setup; fast path uses additions only.
     typedef struct packed {
         logic [`VX_CFG_MEM_ADDR_WIDTH-1:0]  initial_gmem_base;
-        logic [`VX_CFG_XLEN-1:0]           initial_smem_base;
+        logic [DXA_SMEM_ADDR_W-1:0]         initial_smem_base;
         logic [31:0]                row_len_bytes;
         // Rolling-cursor deltas applied at each outer-dim step:
         //   delta[0]: dim-0 step                = stride[0]

hw/rtl/dxa/VX_dxa_setup.sv

@@ -150,10 +150,10 @@ module VX_dxa_setup import VX_gpu_pkg::*, VX_dxa_pkg::*; (
     reg [BAR_ADDR_W-1:0]                   r_bar_addr;
     reg                                    r_notify_smem_done;
     reg                                    r_is_multicast;
-    reg [`VX_CFG_NUM_WARPS-1:0]                   r_cta_mask;
+    reg [`VX_CFG_NUM_WARPS-1:0]            r_cta_mask;
     reg [31:0]                             r_smem_stride;
-    reg [`VX_CFG_MEM_ADDR_WIDTH-1:0]              r_initial_gmem_base;
-    reg [`VX_CFG_XLEN-1:0]                        r_initial_smem_base;
+    reg [`VX_CFG_MEM_ADDR_WIDTH-1:0]       r_initial_gmem_base;
+    reg [DXA_SMEM_ADDR_W-1:0]              r_initial_smem_base;
     reg [31:0]                             r_row_len_bytes;
     reg [DXA_MAX_OUTER_DIMS-1:0][31:0]     r_delta;
     reg [DXA_MAX_OUTER_DIMS-1:0][31:0]     r_dim_tiles;
@@ -174,10 +174,10 @@ module VX_dxa_setup import VX_gpu_pkg::*, VX_dxa_pkg::*; (
     reg [BAR_ADDR_W-1:0]                   s_bar_addr;
     reg                                    s_notify_smem_done;
     reg                                    s_is_multicast;
-    reg [`VX_CFG_NUM_WARPS-1:0]                   s_cta_mask;
+    reg [`VX_CFG_NUM_WARPS-1:0]            s_cta_mask;
     reg [31:0]                             s_smem_stride;
-    reg [`VX_CFG_MEM_ADDR_WIDTH-1:0]              s_initial_gmem_base;
-    reg [`VX_CFG_XLEN-1:0]                        s_initial_smem_base;
+    reg [`VX_CFG_MEM_ADDR_WIDTH-1:0]       s_initial_gmem_base;
+    reg [DXA_SMEM_ADDR_W-1:0]              s_initial_smem_base;
     reg [31:0]                             s_row_len_bytes;
     reg [DXA_MAX_OUTER_DIMS-1:0][31:0]     s_delta;
     reg [DXA_MAX_OUTER_DIMS-1:0][31:0]     s_dim_tiles;

hw/rtl/dxa/VX_dxa_smem_wr.sv

@@ -51,7 +51,7 @@ module VX_dxa_smem_wr import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
     output wire                        sw_ready,
     input  wire [TAG_W-1:0]            sw_tag,
     input  wire [GMEM_DATAW-1:0]       sw_data,
-    input  wire [`VX_CFG_MEM_ADDR_WIDTH-1:0]  sw_smem_byte_addr,
+    input  wire [DXA_SMEM_ADDR_W-1:0]  sw_smem_byte_addr,
     input  wire [CL_OFF_BITS-1:0]      sw_byte_offset,
     input  wire [CL_OFF_BITS:0]        sw_valid_length,
     input  wire                        sw_oob,
@@ -112,7 +112,7 @@ module VX_dxa_smem_wr import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
     // ════════════════════════════════════════════════════════════════════
     reg                       pend_valid_r;
     reg [TAG_W-1:0]           pend_tag_r;
-    reg [`VX_CFG_MEM_ADDR_WIDTH-1:0] pend_smem_byte_addr_r;
+    reg [DXA_SMEM_ADDR_W-1:0] pend_smem_byte_addr_r;
     reg [CL_OFF_BITS-1:0]     pend_byte_offset_r;
     reg [CL_OFF_BITS:0]       pend_valid_length_r;
     reg                       pend_last_r;
@@ -124,7 +124,7 @@ module VX_dxa_smem_wr import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
     // ════════════════════════════════════════════════════════════════════
     reg                       defer_valid_r;
     reg [TAG_W-1:0]           defer_tag_r;
-    reg [`VX_CFG_MEM_ADDR_WIDTH-1:0] defer_smem_byte_addr_r;
+    reg [DXA_SMEM_ADDR_W-1:0] defer_smem_byte_addr_r;
     reg [CL_OFF_BITS-1:0]     defer_byte_offset_r;
     reg [CL_OFF_BITS:0]       defer_valid_length_r;
     reg [GMEM_DATAW-1:0]      defer_data_r;
@@ -142,7 +142,7 @@ module VX_dxa_smem_wr import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
     reg [SMEM_ADDR_WIDTH-1:0]  fb_start_word_r;
     // K-major scatter state: per-beat target byte address (this CL's
     // element-0 destination plus N*per_lane_stride per beat).
-    reg [`VX_CFG_MEM_ADDR_WIDTH-1:0] fb_byte_addr_r;
+    reg [DXA_SMEM_ADDR_W-1:0] fb_byte_addr_r;
 
     // K-major drain quantum (in bytes) = 1 element per beat in scatter mode,
     // SMEM_WORD_SIZE bytes per beat in row-major streaming mode.
@@ -257,7 +257,7 @@ module VX_dxa_smem_wr import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
     wire                       fb_load_now      = use_sw_for_fb || use_pend_for_fb || use_defer_for_fb;
 
     wire [GMEM_DATAW-1:0]      fb_load_data;
-    wire [`VX_CFG_MEM_ADDR_WIDTH-1:0] fb_load_smem_byte_addr;
+    wire [DXA_SMEM_ADDR_W-1:0] fb_load_smem_byte_addr;
     wire [CL_OFF_BITS-1:0]     fb_load_byte_offset;
     wire [CL_OFF_BITS:0]       fb_load_valid_length;
     wire [TAG_W-1:0]           fb_load_tag;
@@ -323,7 +323,7 @@ module VX_dxa_smem_wr import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
                 if (dest_kmajor) begin
                     fb_data_r      <= fb_data_r >> km_shift_bits;
                     fb_level_r     <= fb_level_r - drain_q_bytes;
-                    fb_byte_addr_r <= fb_byte_addr_r + `VX_CFG_MEM_ADDR_WIDTH'(per_lane_stride_bytes);
+                    fb_byte_addr_r <= fb_byte_addr_r + DXA_SMEM_ADDR_W'(per_lane_stride_bytes);
                 end else begin
                     fb_data_r      <= fb_data_r >> SMEM_DATAW;
                     fb_level_r     <= fb_level_r - FILL_W'(SMEM_WORD_SIZE);
@@ -458,6 +458,8 @@ module VX_dxa_smem_wr import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
     wire [SMEM_ADDR_WIDTH-1:0] replay_addr  = base_word_addr + beat_offset;
     // Only the low SMEM_ADDR_WIDTH+SMEM_OFF_W bits of smem_stride are used.
     `UNUSED_VAR (smem_stride)
+    // per_lane_stride_bytes is LMEM-bounded; only the low DXA_SMEM_ADDR_W bits feed fb_byte_addr_r.
+    `UNUSED_VAR (per_lane_stride_bytes[15:DXA_SMEM_ADDR_W])
 
     wire replay_is_last = replay_has_remaining
         && (replay_remaining_use == (`VX_CFG_NUM_WARPS'(1) << replay_next_idx));

hw/rtl/dxa/VX_dxa_unit.sv

@@ -61,15 +61,17 @@ module VX_dxa_unit import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
     assign dxa_req_data_in.core_id   = NC_WIDTH'(CORE_ID);
     assign dxa_req_data_in.uuid      = execute_if.data.header.uuid;
     assign dxa_req_data_in.wid       = execute_if.data.header.wid;
-    assign dxa_req_data_in.smem_addr = lmem_rel_byte_addr;
+    assign dxa_req_data_in.smem_addr = lmem_rel_byte_addr[DXA_SMEM_ADDR_W-1:0];
     assign dxa_req_data_in.meta      = lane1_rs1[31:0];
     assign dxa_req_data_in.coords[0] = lane2_rs1[31:0];
     assign dxa_req_data_in.coords[1] = lane3_rs1[31:0];
     assign dxa_req_data_in.coords[2] = lane0_rs2[31:0];
     assign dxa_req_data_in.coords[3] = lane1_rs2[31:0];
     assign dxa_req_data_in.coords[4] = lane2_rs2[31:0];
     assign dxa_req_data_in.cta_mask  = lane3_rs2[`VX_CFG_NUM_WARPS-1:0];
-    // meta/coords carry 32-bit ABI values; high bits unused on XLEN>32 builds
+    // smem_addr (LMEM byte width) and meta/coords (32-bit ABI) take low bits;
+    // high bits unused when XLEN exceeds the field width
+    `UNUSED_VAR (lmem_rel_byte_addr)
     `UNUSED_VAR (lane1_rs1)
     `UNUSED_VAR (lane2_rs1)
     `UNUSED_VAR (lane3_rs1)

hw/rtl/dxa/VX_dxa_worker.sv

@@ -67,7 +67,7 @@ module VX_dxa_worker import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
     wire                        ag_valid;
     wire                        ag_ready;
     wire [GMEM_ADDR_WIDTH-1:0]  ag_cl_addr;
-    wire [`VX_CFG_MEM_ADDR_WIDTH-1:0]  ag_smem_byte_addr;
+    wire [DXA_SMEM_ADDR_W-1:0]  ag_smem_byte_addr;
     wire [GMEM_OFF_BITS-1:0]    ag_byte_offset;
     wire [GMEM_OFF_BITS:0]      ag_valid_length;
     wire                        ag_oob;
@@ -82,7 +82,7 @@ module VX_dxa_worker import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
     wire                        sw_ready;
     wire [TAG_W-1:0]            sw_tag;
     wire [GMEM_DATAW-1:0]       sw_data;
-    wire [`VX_CFG_MEM_ADDR_WIDTH-1:0]  sw_smem_byte_addr;
+    wire [DXA_SMEM_ADDR_W-1:0]  sw_smem_byte_addr;
     wire [GMEM_OFF_BITS-1:0]    sw_byte_offset;
     wire [GMEM_OFF_BITS:0]      sw_valid_length;
     wire                        sw_oob;
@@ -168,7 +168,7 @@ module VX_dxa_worker import VX_gpu_pkg::*, VX_dxa_pkg::*; #(
         .GMEM_ADDR_WIDTH (GMEM_ADDR_WIDTH),
         .GMEM_TAG_WIDTH  (GMEM_TAG_WIDTH),
         .CL_OFF_BITS     (GMEM_OFF_BITS),
-        .SMEM_ADDR_W     (`VX_CFG_MEM_ADDR_WIDTH)
+        .SMEM_ADDR_W     (DXA_SMEM_ADDR_W)
     ) gmem_req (
         .clk                (clk),
         .reset              (reset),