feat: support SystemVerilog (HDL) via tree-sitter

[vitali87]

Motivation

Requested in #133: enable CodeRAG over SystemVerilog (HDL) projects. Rather than adopting a separate index format (Kythe), SystemVerilog fits the existing tree-sitter pipeline used for every other supported language.

Approach

Add SystemVerilog as a first-class tree-sitter language, following the pattern of existing languages:

• Add a SystemVerilog tree-sitter grammar (e.g. tree-sitter-systemverilog) and register it in codebase_rag/parser_loader.py.
• Add a SupportedLanguage.SYSTEMVERILOG entry plus file extensions (.sv, .svh, .v) and a LanguageSpec in codebase_rag/language_spec.py mapping HDL constructs to graph nodes:
  • modules/packages/interfaces/programs as containers/classes
  • module declarations, functions, tasks as functions/methods
  • module instantiations and function/task calls as CALLS
  • import/package references as IMPORTS
  • a SystemVerilog FQNSpec for qualified-name scoping
• Add a test suite mirroring the existing test_<lang>_* style (structure/containment oracle, functions, imports, instantiation/call edges).

Notes

• Split off from Would you consider integrating the Kythe code index format? #133; the Kythe route was declined as out of current architecture.
• HDL semantics differ from general-purpose languages (modules, instances, ports, always blocks); the initial scope is structural extraction + instantiation/call edges, with type/connectivity inference as later work.