More detail about implementing NPUs on FPGA

[nikmehr]

Hi,

I wonder if more detailed information could be added to the end of "Tutorial" describing that section of the design flow that offloads candidates for neural acceleration on Zynq+FPGA (preferably using an example).

[sampsyo]

Thanks for your interest. But getting SNNAP up and running on an FPGA is a big, complicated endeavor! So I have to warn you that detailed documentation may be more work (and take longer) than you expect.

[nikmehr]

Thanks for the hint :-) but we are committed to give it a try. So I will be very grateful if you can direct me to the detailed documentation please.

[sampsyo]

I'm glad you're interested! But that's sort of what I was trying to say: it would be a surprisingly large amount of effort on my end to put together this documentation, so I can't promise it will happen any time soon. But if you figure out anything useful by digging around, please consider posting your notes here!