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**Ternary Fabric** is a ternary-native memory and interconnect co-processor designed to accelerate AI and signal processing. By utilizing balanced-ternary semantics ({-1, 0, 1}), it eliminates multiplication overhead and enables fine-grained hardware optimizations like **Zero-Skip** and **Free-Negation**.
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**Ternary Fabric** is a ternary-native memory and interconnect co-processor designed to accelerate AI and signal processing. By utilizing balanced-ternary semantics `{ -1, 0, +1 }`, it replaces general multiplication with gated add/subtract and sign logic, enabling fine-grained hardware optimizations like **Zero-Skip** and **Free-Negation**.
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Ternary Fabric transparently intercepts AI workloads and executes sparse linear algebra using ternary hardware semantics to reduce power, memory traffic, and multiplication cost without rewriting models.
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> **In one line:**Ternary Fabric transparently intercepts AI workloads and executes sparse linear algebra using ternary hardware semantics to reduce power, memory traffic, and multiplication cost without rewriting models.
For detailed setup instructions, see **[Installation & Setup](docs/01_INSTALL.md)**.
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## 🤔 Why Ternary?
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In traditional binary systems, multiplication is the most expensive operation in terms of area and power. Ternary computing ({-1, 0, 1}) turns multiplications into simple gated additions or subtractions.
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In traditional binary systems, multiplication dominates area, power, and routing cost. Balanced ternary `{ -1, 0, +1 }` converts many multiply paths into conditional add, subtract, or bypass operations.
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This enables:
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***Zero-Skip:** No toggle, no fetch, no accumulate when operand = 0.
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***Free-Negation:** Sign inversion without multiplier hardware.
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***Sparse-first execution:** Control logic prioritizes semantic absence over arithmetic presence.
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### Performance vs. Sparsity
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The Fabric thrives on sparsity. In typical LLM workloads with 50-70% zero-valued operands, the **Zero-Skip** hardware suppresses clock toggling, leading to massive power savings and effective throughput gains that binary accelerators cannot match.
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The Fabric thrives on sparsity. In typical GGUF / LLM layers after ternary quantization:
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***55–72%** of operands become zero.
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* Zero-Skip suppresses both compute *and memory toggle* for those lanes.
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* Energy per operation drops super-linearly with sparsity.
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```text
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Effective Throughput
@@ -52,11 +66,89 @@ Effective Throughput
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0% 50% 100%
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```
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Binary accelerators still pay fetch and multiply cost for zeros. Fabric does not.
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---
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## 🪞 The Fabric Illusion
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Ternary Fabric operates as a **semantic execution substrate**, not a library rewrite.
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It creates a *memory illusion layer* that:
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* Intercepts allocations and GEMV calls.
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* Migrates hot weights into ternary residency pools.
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* Offloads compute onto Fabric tiles.
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* Short-circuits CPU execution when Fabric execution is available.
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From the application’s point of view, nothing changes — but execution migrates underneath the program.
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This allows **zero-patch acceleration** of existing AI software.
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---
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## 🧠 How Fabric Executes a Layer
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When an application executes a linear layer, Fabric reshapes execution beneath the program:
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1.**Invocation**
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The application issues a GEMV / GEMM through PyTorch, GGUF, or native code.
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2.**Interception**
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The Fabric interposer captures allocations and compute calls using the illusion layer (`LD_PRELOAD` / IOCTL).
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3.**Residency Migration**
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Hot weights are migrated into ternary residency pools managed with LRU and tile locality.
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4.**Quantization**
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Operands are converted into balanced ternary `{ -1, 0, +1 }` form.
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5.**Sparse Scheduling**
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Tiles schedule lanes with **Zero-Skip**:
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*`0` → bypass
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*`+1` → add
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*`-1` → subtract
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6.**Execution**
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Accumulators perform gated adds/subtracts with sign control instead of full multipliers.
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7.**Return Illusion**
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Results are written back into host-visible memory while CPU execution is short-circuited when possible.
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Conceptually:
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```
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Binary: y = W · x
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Fabric: y = Σ (sign(wᵢ) * xᵢ) , wᵢ ∈ {-1,0,+1}
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skip if wᵢ = 0
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```
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Fabric accelerates not by computing faster, but by **not computing at all when semantics allow omission**.
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---
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## 🆚 What Makes Fabric Different
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Ternary Fabric is not a conventional accelerator. It combines ternary arithmetic with memory illusion and sparse-first scheduling.
| Execution model | Arithmetic-first | Arithmetic-first | Arithmetic-first |**Semantic-first**|
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Where GPUs accelerate arithmetic, Fabric accelerates **semantic absence**: zeros, signs, bypasses, and residency locality.
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## 🚀 Real-World Use Case: `llama.cpp` Integration
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Ternary Fabric provides **zero-patch acceleration** for `llama.cpp` through device-level memory interposition. It intercepts memory allocations and offloads GEMV operations to the fabric transparently.
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Ternary Fabric provides transparent acceleration for `llama.cpp` through device-level memory interposition. It intercepts memory allocations and GEMV operations and offloads them to the fabric automatically.
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```bash
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# Enable Fabric acceleration with CPU short-circuiting
Telemetry exposes sparsity, residency, and queue pressure in real time.
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## 🏗️ Project State & Architecture
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The project is currently in **Phase 15**, offering deep integration with PyTorch and GGUF, alongside native hardware acceleration for advanced kernels.
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The project is currently in **Phase 15**, representing full-stack operation:
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* PyTorch frontends
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* GGUF ingestion
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* Multi-tile emulation
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* IOCTL device layer
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* Interposition illusion
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* RTL kernel parity
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### Architecture Layers
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***Framework Layer**
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Transparent PyTorch integration via `TFMBSLinear`, supporting automatic quantization and weight residency.
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***Software Layer (Emulation)**
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High-fidelity multi-tile emulator with `/dev/tfmbs` IOCTL support, GGUF v2/v3 parsing, async queues, and `LD_PRELOAD` interposer.
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***Hardware Layer (RTL)**
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ASIC-ready synthesizable RTL with native support for T-GEMM, T-CONV3D, T-LSTM, and T-Attention kernels.
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### Fabric Configurations
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***Framework Layer:** Transparent PyTorch integration via `TFMBSLinear`, supporting automatic quantization and weight residency.
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***Software Layer (Emulation):** High-fidelity multi-tile emulator with IOCTL support (`/dev/tfmbs`), GGUF v2/v3 parsing, and transparent `LD_PRELOAD` interposer.
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***Hardware Layer (RTL):** ASIC-ready synthesizable RTL with native support for T-GEMM, T-CONV3D, T-LSTM, and T-Attention kernels.
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