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The Ternary Fabric is designed to scale horizontally. While a single **Tile** provides 15 parallel lanes of ternary execution, a physical **Fabric Device** typically contains multiple Tiles (e.g., 4 or 8) that can operate in lock-step or independently.
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## 2. The `tile_mask` Mechanism
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Execution requests (both via the high-level `fabric_exec_gemv` and the low-level `TFMBS_IOC_SUBMIT`) now support a `tile_mask`.
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***Type:**`uint8_t` (Bit-field)
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***Behavior:** Each bit corresponds to a physical Tile.
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***Example:**
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*`0x01`: Only Tile 0 is active (15 lanes).
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*`0x03`: Tiles 0 and 1 are active (30 lanes).
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*`0x0F`: All 4 Tiles are active (60 lanes).
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## 3. Workload Partitioning
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In Phase 11, the fabric controller automatically partitions GEMV workloads across the active tiles specified in the mask.
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### 3.1 Row-Wise Distribution
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For a matrix $W$ with $R$ rows, the controller distributes rows such that each tile $T$ handles approximately $R / N$ rows, where $N$ is the number of set bits in the `tile_mask`.
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### 3.2 Performance Benefits
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Scaling across tiles provides:
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-**Increased Throughput:** Linear scaling of operations per cycle.
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-**Power Efficiency:** Tiles not specified in the `tile_mask` can remain in a low-power clock-gated state.
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## 4. Multi-GPU / Multi-Fabric (Future)
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Phase 11 established the logic for intra-device scaling. Future updates will extend this to multi-device configurations where partial results are reduced across the PCIe or CXL interconnect.
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