NIOS_II_System.sdc

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# Clock constraints

create_clock -name "clock50Mhz" -period 20.000ns [get_ports {CLOCK_50}] -waveform {0.000 10.000}


# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
derive_clocks -period 40.000ns -waveform {0.000 20.000}

# Automatically calculate clock uncertainty to jitter and other effects.
#derive_clock_uncertainty
# Not supported for family Cyclone II

# tsu/th constraints

# tco constraints

# tpd constraints

#set_max_delay 12.000ns -from [get_ports {CLOCK_50}] -to [get_ports {SRam_LB_N SRam_OE_N SRam_UB_N SRam_WE_N SRam_CE_N SRam_DQ SRAM_ADDR}]
#set_min_delay 8.000ns -from [get_ports {CLOCK_50}] -to [get_ports {SRam_LB_N SRam_OE_N SRam_UB_N SRam_WE_N SRam_CE_N SRam_DQ SRAM_ADDR}]


set_max_skew  -to [get_ports {SRam_LB_N SRam_OE_N SRam_UB_N SRam_WE_N SRam_CE_N SRam_DQ[*] SRAM_ADDR[*]}] 0.5
#report_max_skew -panel_name "Report Max Skew" -npaths 10 -detail path_only