Merge pull request #1423 from slaclab/pre-release

Release Candidate v2.72.0

Author: ruck314

.github/CODEOWNERS

@@ -0,0 +1,5 @@
+# GitHub requests reviews from CODEOWNERS when matching files change.
+# If path-specific rules are added later, include one of these owners on each
+# rule to keep code-owner review required for every PR into pre-release.
+
+* @bengineerd @slacrherbst @ruck314

AGENTS.md

@@ -6,6 +6,21 @@ SLAC Ultimate RTL Framework
 
 <!--- ########################################################################################### -->
 
+# Repository Map
+
+- [Agent guidance](AGENTS.md): project layout, coding conventions, and verification notes for contributors and coding agents.
+- [AXI](axi/README.md): AXI-Lite, AXI4, AXI Stream, DMA, bridges, and simulation-link RTL.
+- [Base](base/README.md): foundational packages, CDC, FIFO, RAM, reset, delay, CRC, and generic RTL helpers.
+- [Devices](devices/README.md): vendor and component-specific RTL support.
+- [DSP](dsp/README.md): generic and Xilinx-specific DSP support.
+- [Ethernet](ethernet/README.md): MAC, raw Ethernet, IPv4, UDP, RoCEv2, and high-speed Ethernet cores.
+- [Protocols](protocols/README.md): PGP, SSI, SRP, RSSI, CoaXPress, JESD204B, peripheral buses, and related protocol cores.
+- [Xilinx](xilinx/README.md): Xilinx-family wrappers, primitive integrations, and XVC UDP support.
+- [Python](python/README.md): PyRogue package layout under `python/surf`.
+- [Tests](tests/README.md): cocotb regression layout, methodology, helpers, and simulator conventions.
+
+<!--- ########################################################################################### -->
+
 # Before you clone the GIT repository
 
 Setup for large filesystems on github.  `git-lfs` used for all binary files (example: .dcp)

README.md

@@ -0,0 +1,14 @@
+# AXI
+
+This tree contains reusable AXI-family RTL and wrappers. Top-level `axi/ruckus.tcl` loads the submodules used by SURF builds.
+
+## Layout
+
+- `axi-lite/`: AXI-Lite records, crossbars, endpoints, masters, slaves, monitors, and IP-integrator adapters.
+- `axi-stream/`: AXI Stream records, FIFOs, muxes, monitors, protocol adapters, and stream wrappers.
+- `axi4/`: full AXI4 support blocks and adapters.
+- `bridge/`: bridges between AXI-family buses and SURF protocol records.
+- `dma/`: DMA register, descriptor, FIFO, and stream integration cores.
+- `simlink/`: simulator-link support and C/C++/VHDL pieces used by simulation flows.
+
+Use existing package record types before adding flattened ports. Put durable adapter entities in `ip_integrator/` or `wrappers/`, and keep executable cocotb tests under `tests/axi/`.

axi/README.md

@@ -262,7 +262,7 @@ package AxiLitePkg is
             connectivity => X"FFFF"));
 
    -------------------------------------------------------------------------------------------------
-   -- Initilize masters with uppder address bits already set to configuration base address
+   -- Initialize masters with upper address bits already set to configuration base address
    -------------------------------------------------------------------------------------------------
    function axiWriteMasterInit (constant config : AxiLiteCrossbarMasterConfigArray) return AxiLiteWriteMasterArray;
    function axiWriteMasterInit (constant config : AxiLiteCrossbarMasterConfigType) return AxiLiteWriteMasterType;

axi/axi-lite/rtl/AxiLitePkg.vhd

@@ -451,7 +451,7 @@ begin
             end if;
          ----------------------------------------------------------------------
          when SEQ_DONE_S =>
-            -- Set all bits to 1 so SW knowns it done
+            -- Set all bits to 1 so SW knows it done
             v.addr  := (others => '0');
             v.din   := (others => '1');
             v.wstrb := (others => '1');

axi/axi-lite/rtl/AxiLiteSequencerRam.vhd

@@ -66,7 +66,7 @@ entity AxiStreamFifoV2IpIntegrator is
 
       -- Internal FIFO width select, "WIDE", "NARROW" or "CUSTOM"
       -- WIDE uses wider of slave / master. NARROW  uses narrower.
-      -- CUSOTM uses passed FIFO_DATA_WIDTH_G
+      -- CUSTOM uses passed FIFO_DATA_WIDTH_G
       INT_WIDTH_SELECT : string                := "WIDE";
       INT_DATA_WIDTH   : natural range 1 to 16 := 16;
 

axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd

@@ -216,7 +216,7 @@ begin
    ------- END MAIN DATA FIFO -------
    ----------------------------------
 
-   -- These signals are not responsible for hanshakes and can
+   -- These signals are not responsible for handshakes and can
    -- just be forwarded
    combAxisMaster.tData <= axisMasterFifo.tData;
    combAxisMaster.tStrb <= axisMasterFifo.tStrb;

axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd

@@ -142,7 +142,7 @@ begin  -- architecture rtl
             -- Reset full flags
             v.fullBus := false;
 
-            -- get tKeet boundaries
+            -- get tKeep boundaries
             tKeepMin   := getTKeepMin(sAxisMaster.tKeep, SLAVE_AXI_CONFIG_G);
             tKeepWidth := getTKeep(sAxisMaster.tKeep, SLAVE_AXI_CONFIG_G);
             tDataWidth := to_integer(shift_left(to_unsigned(tKeepWidth, SLV_BYTES_C), 3));

axi/axi-stream/rtl/AxiStreamCompact.vhd

@@ -4,7 +4,7 @@
 -- Description: Firmware module that AxiStreamConcat multiple AXI stream frames
 --              together.  It will ignore TKEEP and the format of the frame.
 -------------------------------------------------------------------------------
--- Note: This module is similiar to "AxiStreamBatcher.vhd" but does NOT
+-- Note: This module is similar to "AxiStreamBatcher.vhd" but does NOT
 --       have the following features
 --          1) No super header
 --          2) No tail footer