diff --git a/.github/workflows/riscv-rt.yaml b/.github/workflows/riscv-rt.yaml
index ea976ba5..3dfc6cd1 100644
--- a/.github/workflows/riscv-rt.yaml
+++ b/.github/workflows/riscv-rt.yaml
@@ -59,6 +59,8 @@ jobs:
         run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=s-mode,single-hart,v-trap
       - name : Build (u-boot)
         run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example empty --features=u-boot
+      - name : Build (defmt)
+        run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example empty --features=defmt
   
   build-others:
     strategy:
@@ -71,7 +73,7 @@ jobs:
       - name: Build (no features)
         run: cargo build --package riscv-rt
       - name: Build (all features but u-boot)
-        run: cargo build --package riscv-rt --features=s-mode,single-hart,v-trap
+        run: cargo build --package riscv-rt --features=s-mode,single-hart,v-trap,defmt
       - name: Build (u-boot)
         run: cargo build --package riscv-rt --features=u-boot
         
diff --git a/.github/workflows/riscv.yaml b/.github/workflows/riscv.yaml
index 7a0eb07e..b3dfc06c 100644
--- a/.github/workflows/riscv.yaml
+++ b/.github/workflows/riscv.yaml
@@ -63,8 +63,13 @@ jobs:
       - uses: dtolnay/rust-toolchain@stable
       - name: Test (no features)
         run: cargo test --package riscv
+      # defmt linking fails if not on an ELF platform (https://defmt.ferrous-systems.com/#current-limitations)
       - name: Test (all features)
+        if: matrix.os == 'ubuntu-latest'
         run: cargo test --package riscv --all-features
+      - name: Test (all features except defmt)
+        if: matrix.os != 'ubuntu-latest'
+        run: cargo test --package riscv --no-default-features --features riscv-macros,s-mode,critical-section-single-hart,rt,rt-v-trap
 
   # Job to check that all the builds succeeded
   build-check:
diff --git a/Cargo.toml b/Cargo.toml
index ef411f0f..4b5e8941 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -22,3 +22,6 @@ default-members = [
     "riscv-semihosting",
     "riscv-types",
 ]
+
+[workspace.dependencies]
+defmt = "1.1.1"
diff --git a/riscv-rt/CHANGELOG.md b/riscv-rt/CHANGELOG.md
index 7d16a91e..05973e7c 100644
--- a/riscv-rt/CHANGELOG.md
+++ b/riscv-rt/CHANGELOG.md
@@ -22,6 +22,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
   with the ID of the running hart. This allows users to implement hart-specific
   interrupt setup in multi-hart targets.
 - Use macros from `riscv-macros` instead of `riscv-rt-macros`
+- Updated minimum defmt to `1.1.1`, which fixes an FCW
 
 ### Removed
 
diff --git a/riscv-rt/Cargo.toml b/riscv-rt/Cargo.toml
index 9e8ba54a..9c9718a2 100644
--- a/riscv-rt/Cargo.toml
+++ b/riscv-rt/Cargo.toml
@@ -28,7 +28,7 @@ riscv = { path = "../riscv", version = "0.16.1", features = ["rt"] }
 riscv-types = { path = "../riscv-types", version = "0.1.0" }
 riscv-macros = { path = "../riscv-macros", version = "0.4.1", features = ["riscv-rt"] }
 
-defmt = { version = "1.0.1", optional = true }
+defmt = { workspace = true, optional = true }
 
 [dev-dependencies]
 panic-halt = "1.0.0"
@@ -52,5 +52,5 @@ no-xie-xip = []
 no-xtvec = []
 device = []
 memory = []
-defmt = ["dep:defmt"]
+defmt = ["dep:defmt", "riscv/defmt", "riscv-types/defmt"]
 pre-default-start-trap = ["riscv-macros/rvrt-pre-default-start-trap"]
diff --git a/riscv-types/CHANGELOG.md b/riscv-types/CHANGELOG.md
index 0b48be49..cacd1969 100644
--- a/riscv-types/CHANGELOG.md
+++ b/riscv-types/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Added
+
+- Add new feature `defmt` which will optionally derive `defmt::Format` on `result::Error`.
+
 ## v0.1.0 - 2025-12-19
 
 ### Changed
@@ -29,7 +33,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Classify interrupt numbers in `CoreInterruptNumber` and `ExternalInterruptNumber`.
 - Added simple tests to illustrate how to implement all the provided traits.
 
-### Changed 
+### Changed
 
 - All traits now work with `usize` data type.
 
diff --git a/riscv-types/Cargo.toml b/riscv-types/Cargo.toml
index b06c017f..44529e1e 100644
--- a/riscv-types/Cargo.toml
+++ b/riscv-types/Cargo.toml
@@ -17,3 +17,9 @@ targets = [
     "riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf",
     "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf",
 ]
+
+[dependencies]
+defmt = { workspace = true, optional = true }
+
+[features]
+defmt = ["dep:defmt"]
diff --git a/riscv-types/src/result.rs b/riscv-types/src/result.rs
index fa158529..27dfa9c0 100644
--- a/riscv-types/src/result.rs
+++ b/riscv-types/src/result.rs
@@ -6,6 +6,7 @@ pub type Result<T> = core::result::Result<T, Error>;
 /// Represents error variants for the library.
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
 #[non_exhaustive]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Error {
     /// Attempted out-of-bounds access.
     IndexOutOfBounds {
diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index d42f084f..61ceb659 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
+- Add new feature `defmt` which will optionally derive `defmt::Format` on certain types.
 - Add `stimecmp`/`stimecmph` CSRs
 - Add `tselect`, `tdata2` and `tdata3` Sdtrig CSRs as raw `read_write_csr_as_usize!` accessors, and `tdata1` and `tcontrol` as typed CSRs with field accessors.
 - Add `read_bits`/`try_read_bits` and `write_bits`/`try_write_bits` to the modules generated by `read_csr_as_usize!` and `write_csr_as_usize!`, as aliases of `read`/`write` so that a generated CSR module offers the same raw accessors no matter which macro defined it.
diff --git a/riscv/Cargo.toml b/riscv/Cargo.toml
index eaa50c6f..f334cd62 100644
--- a/riscv/Cargo.toml
+++ b/riscv/Cargo.toml
@@ -25,10 +25,12 @@ s-mode = []
 critical-section-single-hart = ["critical-section/restore-state-bool"]
 rt = ["riscv-macros/rt"]
 rt-v-trap = ["rt", "riscv-macros/rt-v-trap"]
+defmt = ["dep:defmt", "riscv-types/defmt"]
 
 [dependencies]
 critical-section = "1.2.0"
 embedded-hal = "1.0.0"
+defmt = { workspace = true, optional = true }
 riscv-types = { path = "../riscv-types", version = "0.1.0" }
 riscv-macros = { path = "../riscv-macros", version = "0.4.1", optional = true }
 pastey = "0.2.2"
diff --git a/riscv/src/interrupt.rs b/riscv/src/interrupt.rs
index a66ae062..4a1c98d8 100644
--- a/riscv/src/interrupt.rs
+++ b/riscv/src/interrupt.rs
@@ -54,6 +54,7 @@ pub enum Trap<I, E> {
 
 /// Trap Error
 #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum TrapError {
     InvalidInterrupt(usize),
     InvalidException(usize),
diff --git a/riscv/src/interrupt/machine.rs b/riscv/src/interrupt/machine.rs
index 9de36c0a..22f2eee1 100644
--- a/riscv/src/interrupt/machine.rs
+++ b/riscv/src/interrupt/machine.rs
@@ -7,6 +7,7 @@ use crate::{
 
 /// Standard M-mode RISC-V interrupts
 #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[repr(usize)]
 pub enum Interrupt {
     SupervisorSoft = 1,
@@ -45,6 +46,7 @@ unsafe impl CoreInterruptNumber for Interrupt {}
 
 /// Standard M-mode RISC-V exceptions
 #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[repr(usize)]
 pub enum Exception {
     InstructionMisaligned = 0,
diff --git a/riscv/src/interrupt/supervisor.rs b/riscv/src/interrupt/supervisor.rs
index 59ef39d5..62546fac 100644
--- a/riscv/src/interrupt/supervisor.rs
+++ b/riscv/src/interrupt/supervisor.rs
@@ -7,6 +7,7 @@ use crate::{
 
 /// Interrupt
 #[derive(Copy, Clone, Debug, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[repr(usize)]
 pub enum Interrupt {
     SupervisorSoft = 1,
@@ -39,6 +40,7 @@ unsafe impl CoreInterruptNumber for Interrupt {}
 
 /// Exception
 #[derive(Copy, Clone, Debug, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
 #[repr(usize)]
 pub enum Exception {
     InstructionMisaligned = 0,