Add abs_diff

Author: novacrazy

.claude/skills/thermite.zip

@@ -18,6 +18,11 @@ m.all()  -> bool          // every lane true
 m.any()  -> bool          // some lane true
 m.none() -> bool          // no lane true  (== !any)
 
+// scanning: turn a mask into find/count primitives (build on native_bitmask)
+m.first_set() -> Option<usize>   // index of lowest true lane; with cmp_eq this is a SIMD memchr
+m.last_set()  -> Option<usize>   // index of highest true lane
+m.count_set() -> usize           // number of true lanes (popcount)
+
 m.select(t, f) -> S       // per-lane: mask ? t : f   (one instruction; S: GenericSelectable)
 
 // bitwise combine

.claude/skills/thermite/references/masks.md

@@ -80,8 +80,8 @@ instruction sequences per backend at zero runtime cost
 
 - **GenericVector**: construction, lane access, load/store, gather/scatter, lookup,
   widen/narrow (`extend`/`narrow`/`concat`/`split`), interleave/deinterleave,
-  reverse/swap_bytes/compress, cast/into_bits, `zz`/`nz`, prefix/suffix mask,
-  map/fold/reduce. -> [vector-api.md](vector-api.md) section 1.
+  reverse/swap_bytes/compress, `align::<OFFSET>` (two-vector lane window), cast/into_bits,
+  `zz`/`nz`, prefix/suffix mask, map/fold/reduce. -> [vector-api.md](vector-api.md) section 1.
 - **BitwiseVector / BitshiftVector**: `&` `|` `^` `!`, `bitandnot`, `ternlog`/`bilog`;
   `shl`/`shr`/`shlv`/`shrv`/`shli`/`shri`, byte shifts, rotates, `reverse_bits`.
   -> section 2.
@@ -94,7 +94,8 @@ instruction sequences per backend at zero runtime cost
   `NEG_ONE`, `MIN_POSITIVE`. -> section 5.
 - **IntegerVector family**: `mulhi`/`mullo`, `saturating_add/sub`, `wrapping_sum/prod`,
   dividers, `count_ones/zeros`, `leading_ones/zeros`; signed `srai/sra/srav`,
-  `avg_floor/ceil`; unsigned `is_power_of_two`, `avg`, `parity`, `ilog2p1`. -> section 6.
+  `avg_floor/ceil`, `mulhrs` (rounded Q-format multiply); unsigned `is_power_of_two`,
+  `avg`, `parity`, `ilog2p1`, `abs_diff`, `in_range`. -> section 6.
 - **FloatVector**: `sqrt`, `rcp`, `rsqrt`, `floor/ceil/round/trunc/fract`, `mix`,
   `next_up/down`, `mul_sign`, `signed_zero`, `one_minus_sq`, classification
   (`is_nan/finite/infinite/normal/subnormal`), constants

.claude/skills/thermite/references/trait-hierarchy.md

@@ -45,6 +45,10 @@ let (lo, hi) = a.interleave(b)      let (a, b)    = lo.deinterleave(hi)
 v.compress(mask)    // stable left-pack of true lanes (AVX-512 vpcompress; portable fallback)
 v.compress_z(mask)  // left-pack true lanes, zero the rest
 
+// Two-vector element align (palignr family; any element type): the window of
+// LANES lanes starting at lane OFFSET of [a, b]. OFFSET=0 -> a, OFFSET=LANES -> b.
+a.align::<OFFSET>(b)   // sliding window across a load boundary; int backends use native byte aligns
+
 // Casting
 v.cast::<W>()         // numeric cast, like `as`
 v.fast_cast::<W>()    // faster, may skip edge cases
@@ -112,8 +116,11 @@ v.wrapping_sum()  v.wrapping_prod()   v.count_ones()  v.count_zeros()
 v.leading_ones()  v.leading_zeros()
 // SignedIntegerVector
 v.srai::<I>()  v.sra(n)  v.srav(unsigned)   a.avg_floor(b)  a.avg_ceil(b)
+a.mulhrs(b)    // rounded Q(W-1) fixed-point multiply (i16: Q15, x86 PMULHRSW); rounds, not truncates
 // UnsignedIntegerVector
 v.is_power_of_two() -> M   a.avg(b)   v.parity()   v.ilog2p1()   v.next_power_of_two_m1()
+a.abs_diff(b)              // |a - b| without overflow (saturating-sub form)
+x.in_range(lo, hi) -> M    // mask of lo <= x <= hi, inclusive (branchless, one compare)
 
 // Division by a precomputed divisor (constant-time, branchfree). See `divider` module.
 use thermite::{BranchfreeDivider, Divider};

.claude/skills/thermite/references/vector-api.md

@@ -1828,6 +1828,18 @@ pub trait UnsignedIntegerRegister:
         Self::sub(Self::bitor(a, b), Self::shri::<1>(Self::bitxor(a, b)))
     }
 
+    /// Per-lane unsigned absolute difference `|a - b|`, without overflow.
+    ///
+    /// Computed as `(a -| b) | (b -| a)` with saturating subtraction: exactly
+    /// one of the two saturating subtractions is nonzero (whichever operand is
+    /// larger wins), so the `OR` yields `|a - b|` for any unsigned width. On x86
+    /// this lowers to the canonical `psubus`/`psubus`/`por` sequence, so no
+    /// native override is needed.
+    #[conditional]
+    fn abs_diff(a: Storage<Self>, b: Storage<Self>) -> Storage<Self> {
+        Self::bitor(Self::saturating_sub(a, b), Self::saturating_sub(b, a))
+    }
+
     // TODO: Interleave bits?
 }
 

crates/thermite/src/register/mod.rs

@@ -1731,6 +1731,13 @@ pub trait UnsignedIntegerVector: IntegerVector<Element: crate::element::Unsigned
     ///
     /// Matches x86 `PAVGB`/`PAVGW` and ARM `vrhadd` semantics.
     #[conditional] fn avg(self, other: Self) -> Self;
+
+    /// Per-lane unsigned absolute difference `|self - other|`, without overflow.
+    ///
+    /// Computed branchlessly as `(self -| other) | (other -| self)` with
+    /// saturating subtraction. The per-lane building block of sum-of-absolute-
+    /// differences (block matching, motion estimation).
+    #[conditional] fn abs_diff(self, other: Self) -> Self;
 }
 
 /// Escape hatch tying a [`Vector`] to its specific underlying

crates/thermite/src/vector/mod.rs

@@ -625,6 +625,7 @@ where
     #[conditional] fn ilog2p1(self) -> Self {}
     #[conditional] fn parity(self) -> Self {}
     #[conditional] fn avg(self, other: Self) -> Self {}
+    #[conditional] fn abs_diff(self, other: Self) -> Self {}
 }
 
 #[rustfmt::skip] #[thermite_macros::vector_impl]

crates/thermite/src/vector/vector.rs

@@ -0,0 +1,72 @@
+//! `UnsignedIntegerVector::abs_diff` correctness.
+//!
+//! `a.abs_diff(b)` is the per-lane unsigned `|a - b|`, computed branchlessly as
+//! `(a -| b) | (b -| a)` with saturating subtraction. Verified against Rust's
+//! `uN::abs_diff` oracle over all ordered pairs of a probe set (covering equal,
+//! a<b, a>b, and the 0/MAX corners). The default composes `saturating_sub`,
+//! which is natively overridden per backend, so this is exercised across scalar
+//! and x86 v1/v2/v3.
+
+use thermite::backend::scalar::Scalar;
+use thermite::prelude::*;
+
+#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+use thermite::backend::{x86_v1::X86V1, x86_v2::X86V2, x86_v3::X86V3};
+
+macro_rules! check {
+    ($name:ident, $vty:ty, $elem:ty, $n:literal) => {
+        #[test]
+        fn $name() {
+            type V = $vty;
+            const N: usize = $n;
+
+            let max = <$elem>::MAX;
+            let probes: [$elem; 8] = [0, 1, 2, 127, 128, max / 2, max - 1, max];
+            let p = probes.len();
+
+            // Every ordered (probe, rotated-probe) pair across the lanes.
+            for shift in 0..p {
+                let mut da = [0 as $elem; N];
+                let mut db = [0 as $elem; N];
+                for i in 0..N {
+                    da[i] = probes[i % p];
+                    db[i] = probes[(i + shift) % p];
+                }
+                let got = V::new(da).abs_diff(V::new(db));
+
+                for i in 0..N {
+                    assert_eq!(
+                        got.as_slice()[i],
+                        da[i].abs_diff(db[i]),
+                        "abs_diff a={} b={} lane={}",
+                        da[i], db[i], i
+                    );
+                }
+            }
+        }
+    };
+}
+
+macro_rules! suite {
+    ($modname:ident, $backend:ty) => {
+        mod $modname {
+            use super::*;
+            check!(u8x16, thermite::simd::u8x16<$backend>, u8, 16);
+            check!(u16x8, thermite::simd::u16x8<$backend>, u16, 8);
+            check!(u16x16, thermite::simd::u16x16<$backend>, u16, 16);
+            check!(u32x4, thermite::simd::u32x4<$backend>, u32, 4);
+            check!(u32x8, thermite::simd::u32x8<$backend>, u32, 8);
+            check!(u64x2, thermite::simd::u64x2<$backend>, u64, 2);
+            check!(u64x4, thermite::simd::u64x4<$backend>, u64, 4);
+        }
+    };
+}
+
+suite!(scalar, Scalar);
+
+#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+suite!(v1, X86V1);
+#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+suite!(v2, X86V2);
+#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
+suite!(v3, X86V3);