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cc_delta_counter: Use register macros
1 parent fca9522 commit ae07ef9

1 file changed

Lines changed: 6 additions & 21 deletions

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src/cc_delta_counter.sv

Lines changed: 6 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,8 @@
1010

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// Up/down counter with variable delta
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13+
`include "common_cells/registers.svh"
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module cc_delta_counter #(
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parameter int unsigned Width = 4,
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parameter bit StickyOverflow = 1'b0
@@ -29,20 +31,11 @@ module cc_delta_counter #(
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if (StickyOverflow) begin : gen_sticky_overflow
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logic overflow_d, overflow_q;
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32-
always_ff @(posedge clk_i or negedge rst_ni)
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begin
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if(!rst_ni) begin
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overflow_q <= 1'b0;
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end else begin
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overflow_q <= overflow_d;
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end
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end
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`FFARNC(overflow_q, overflow_d, clr_i || load_i, 1'b0, clk_i, rst_ni)
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4136
always_comb begin
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overflow_d = overflow_q;
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if (clr_i || load_i) begin
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overflow_d = 1'b0;
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end else if (!overflow_q && en_i) begin
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if (!overflow_q && en_i) begin
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if (down_i) begin
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overflow_d = delta_i > counter_q[Width-1:0];
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end else begin
@@ -60,9 +53,7 @@ module cc_delta_counter #(
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always_comb begin
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counter_d = counter_q;
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63-
if (clr_i) begin
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counter_d = '0;
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end else if (load_i) begin
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if (load_i) begin
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counter_d = {1'b0, d_i};
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end else if (en_i) begin
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if (down_i) begin
@@ -73,11 +64,5 @@ module cc_delta_counter #(
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end
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end
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76-
always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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counter_q <= '0;
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end else begin
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counter_q <= counter_d;
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end
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end
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`FFARNC(counter_q, counter_d, clr_i, '0, clk_i, rst_ni)
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endmodule

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