1010
1111// Up/down counter with variable delta
1212
13+ `include " common_cells/registers.svh"
14+
1315module cc_delta_counter # (
1416 parameter int unsigned Width = 4 ,
1517 parameter bit StickyOverflow = 1'b0
@@ -29,20 +31,11 @@ module cc_delta_counter #(
2931 if (StickyOverflow) begin : gen_sticky_overflow
3032 logic overflow_d, overflow_q;
3133
32- always_ff @ (posedge clk_i or negedge rst_ni)
33- begin
34- if (! rst_ni) begin
35- overflow_q <= 1'b0 ;
36- end else begin
37- overflow_q <= overflow_d;
38- end
39- end
34+ `FFARNC (overflow_q, overflow_d, clr_i || load_i, 1'b0 , clk_i, rst_ni)
4035
4136 always_comb begin
4237 overflow_d = overflow_q;
43- if (clr_i || load_i) begin
44- overflow_d = 1'b0 ;
45- end else if (! overflow_q && en_i) begin
38+ if (! overflow_q && en_i) begin
4639 if (down_i) begin
4740 overflow_d = delta_i > counter_q[Width- 1 : 0 ];
4841 end else begin
@@ -60,9 +53,7 @@ module cc_delta_counter #(
6053 always_comb begin
6154 counter_d = counter_q;
6255
63- if (clr_i) begin
64- counter_d = '0 ;
65- end else if (load_i) begin
56+ if (load_i) begin
6657 counter_d = { 1'b0 , d_i} ;
6758 end else if (en_i) begin
6859 if (down_i) begin
@@ -73,11 +64,5 @@ module cc_delta_counter #(
7364 end
7465 end
7566
76- always_ff @ (posedge clk_i or negedge rst_ni) begin
77- if (! rst_ni) begin
78- counter_q <= '0 ;
79- end else begin
80- counter_q <= counter_d;
81- end
82- end
67+ `FFARNC (counter_q, counter_d, clr_i, '0 , clk_i, rst_ni)
8368endmodule
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