Masked `vmerge.vim` with vd=v0 and v0.t does not raise illegal-instruction exception

[KnightGOKU]

Describe the bug

Under matched VLEN = 4096 on both Spike and Ara, Ara executes a masked vector instruction whose destination is v0 while v0 is also used as the mask register. Spike raises an illegal-instruction exception for the same ELF.

The testcase is:

vsetivli x8, 10, e8, m4

li      t0, -1
vmv.v.x v0, t0

li      t0, 0x33
vmv.v.x v20, t0

vmerge.vim v0, v20, -2, v0

The final instruction is the key operation:

vmerge.vim v0, v20, -2, v0

It is a masked vector instruction that writes v0 while also reading v0 as the mask register. This should be rejected as an illegal vector instruction.

Expected behavior

The instruction should trap with an illegal-instruction exception.

Spike reports:

mem 0x0000000080021700 0x0000000000000001   # trap_seen
mem 0x0000000080021708 0x0000000000000002   # mcause = illegal instruction
mem 0x0000000080021710 0x000000005d4f3057   # mtval = vmerge.vim encoding
mem 0x0000000080021718 0x0000000080000046   # mepc = vmerge.vim PC
mem 0x0000000080021720 0x0000000000000000   # vstart
mem 0x0000000080021738 0x0000000000000000   # exit code

The disassembly confirms the faulting instruction:

80000046: 5d4f3057           vmerge.vim v0,v20,-2,v0

Observed behavior

Ara completes the testcase and exits successfully instead of raising an illegal-instruction exception.

Ara RVFI/probe-buffer evidence:

mem 0x0000000080021700 0x0000000000000000   # no trap
mem 0x0000000080021728 0xfffffffffffffffe   # observed result read back from v0
mem 0x0000000080021738 0x0000000000000000   # exit code

Ara log:

Core Test *** SUCCESS *** (tohost = 0)

So Ara executes an instruction that Spike treats as illegal.

To Reproduce

Build:

riscv64-unknown-elf-gcc -nostdlib -static \
  -march=rv64imfdcv_zicsr_zifencei_zfh \
  -mabi=lp64d \
  -T /home/ara_audit_repros/common.ld \
  -o /home/ara_audit_repros/masked_dest_v0_overlap_probe.elf \
  /home/ara_audit_repros/masked_dest_v0_overlap_probe.S

Run Spike:

/home/projects/projects/riscv-isa-sim/install/bin/spike \
  -p1 \
  --isa=RV64IMAFDCV_ZICSR_ZIFENCEI_ZFH_ZVL4096B \
  --log-commits \
  /home/ara_audit_repros/masked_dest_v0_overlap_probe.elf \
  > masked_dest_v0_overlap_probe.spike.log 2>&1

Run Ara:

/home/projects/projects/ara/hardware/build-rvfi9/verilator/Vara_tb_verilator \
  -l ram,/home/ara_audit_repros/masked_dest_v0_overlap_probe.elf,elf \
  > masked_dest_v0_overlap_probe.ara.log 2>&1

program.zip