Ara reports ILLEGAL_INSTR for indexed-load misalignment instead of load-address-misaligned

[KnightGOKU]

Describe the bug

Under matched VLEN = 4096 on both Spike and Ara, an unmasked misaligned indexed load traps on both implementations, but Ara reports the wrong exception class and loses the faulting address.

The testcase is:

vsetivli x0, 4, e32, m1
la      t0, idx_data
vle32.v v4, (t0)
la      t1, mem_data
vluxei32.v v8, (t1), v4

with:

• idx_data = {1, 4, 8, 12}
• no masking
• the very first indexed element uses base + 1, which is misaligned for
  vluxei32.v

The testcase is trap-probe oriented:

• it expects a trap
• it records mcause, mtval, mepc, and vstart
• it exits successfully after recording those observations

Expected behavior

Spike reports:

mem 0x0000000080021100 0x0000000000000004   # mcause
mem 0x0000000080021108 0x00000000800000c1   # mtval
mem 0x0000000080021110 0x0000000080000048   # mepc
mem 0x0000000080021118 0x0000000000000000   # vstart
mem 0x0000000080021120 0x0000000000000000   # exit code

Interpretation:

• mcause = 4 = load address misaligned
• mtval = 0x800000c1 = the faulting effective address
• mepc = 0x80000048 = the vluxei32.v instruction
• vstart = 0 because the exception happened on the first element

Observed behavior

Ara reaches the trap handler and exits successfully, but the recorded trap metadata differs:

mem 0x0000000080021100 0x0000000000000002   # mcause
mem 0x0000000080021108 0x0000000000000000   # mtval
mem 0x0000000080021110 0x0000000080000048   # mepc
mem 0x0000000080021118 0x0000000000000000   # vstart
mem 0x0000000080021120 0x0000000000000000   # exit code

So Ara reports:

• mcause = 2 = illegal instruction
• mtval = 0

instead of the misaligned-load trap metadata shown by Spike.

To Reproduce

Build:

riscv64-unknown-elf-gcc -nostdlib -static \
  -march=rv64imfdcv_zicsr_zifencei_zfh \
  -mabi=lp64d \
  -T /home/projects/ara_audit_repros/common.ld \
  -o /home/projects/ara_audit_repros/indexed_misaligned_cause_probe.elf \
  /home/projects/ara_audit_repros/indexed_misaligned_cause_probe.S

Run Spike:

/home/projects/riscv_impls_bins/spike \
  -p1 \
  --isa=RV64IMAFDCV_ZICSR_ZIFENCEI_ZFH_ZVL4096B \
  --log-commits \
  /home/projects/ara_audit_repros/indexed_misaligned_cause_probe.elf \
  > indexed_misaligned_cause_probe.spike.log 2>&1

Run Ara:

/home/projects/ara/hardware/build-rvfi9/verilator/Vara_tb_verilator \
  -l ram,/home/projects/ara_audit_repros/indexed_misaligned_cause_probe.elf,elf \
  > indexed_misaligned_cause_probe.ara.log 2>&1

Test Cases: indexed_misaligned_cause_probe.zip