Masked-off misaligned indexed load element incorrectly raises illegal-instruction trap

[KnightGOKU]

Describe the bug

Under matched VLEN = 4096 on both Spike and Ara, a masked indexed load with a misaligned address only in a masked-off element traps on Ara, even though the same testcase executes successfully on Spike.

The testcase is:

vsetivli x0, 4, e32, m1
li      t0, 0xdeadbeef
vmv.v.x v8, t0
la      t1, idx_data
vle32.v v4, (t1)
vid.v   v1
vmsne.vi v0, v1, 0
la      t2, mem_data
vluxei32.v v8, (t2), v4, v0.t

with:

• idx_data = {1, 4, 8, 12}
• v0.t active only for elements 1..3
• element 0 therefore masked off
• only the masked-off element uses the misaligned address base + 1

So this is a focused masked-memory testcase:

• element 0 is masked off
• elements 1..3 are aligned and valid
• the destination vector is preinitialized to 0xdeadbeef
• the expected architectural behavior is “no trap, masked-off element remains undisturbed”

Expected behavior

Because the only misaligned indexed element is masked off, the instruction should not raise an exception.

The expected post-load vector contents are:

• element 0: unchanged, still 0xdeadbeef
• element 1: 0x22222222
• element 2: 0x33333333
• element 3: 0x44444444

Spike shows exactly this behavior. The fixed probe buffer contains:

mem 0x0000000080021000 0xdeadbeef
mem 0x0000000080021004 0x22222222
mem 0x0000000080021008 0x33333333
mem 0x000000008002100c 0x44444444
mem 0x0000000080021010 0x0000000000000000   # vstart
mem 0x0000000080021018 0x0000000000000000   # exit code

Observed behavior

Ara traps at the indexed load instruction instead of completing it:

ILLEGAL_INSTR exception @ 0x0000000080000062 (0x0443e407)

The trap handler records:

mem 0x0000000080021020 0x0000000000000002   # mcause = ILLEGAL_INSTR
mem 0x0000000080021028 0x0000000000000000   # mtval
mem 0x0000000080021030 0x0000000080000062   # mepc
mem 0x0000000080021018 0x000000000000dead   # exit code

So Ara raises an exception where the masked operation should complete normally.

To Reproduce

Build:

riscv64-unknown-elf-gcc -nostdlib -static \
  -march=rv64imfdcv_zicsr_zifencei_zfh \
  -mabi=lp64d \
  -T /home/projects/ara_bugs/common.ld \
  -o /home/projects/ara_bugs/masked_index_misaligned_no_trap.elf \
  /home/projects/ara_bugs/masked_index_misaligned_no_trap.S

Run Spike:

/home/projects/riscv_impls_bins/spike \
  -p1 \
  --isa=RV64IMAFDCV_ZICSR_ZIFENCEI_ZFH_ZVL4096B \
  --log-commits \
  /home/projects/ara_bugs/masked_index_misaligned_no_trap.elf \
  > masked_index_misaligned_no_trap.spike.log 2>&1

Run Ara:

/home/projects/ara/hardware/build-rvfi9/verilator/Vara_tb_verilator \
  -l ram,/home/projects/ara_bugs/masked_index_misaligned_no_trap.elf,elf \
  > masked_index_misaligned_no_trap.ara.log 2>&1

Test Cases & logs: masked_index_misaligned_no_trap.ara.zip