Describe the bug
Under matched VLEN = 4096 on both Spike and Ara, the same pure-probe ELF produces different committed architectural results after the sequence:
li x9, 0xa04f
vsetivli x8, 1, e16, mf4
vmv.s.x v28, x9
vsetivli x8, 27, e64, m1
vzext.vf8 v14, v28
vmv.x.s x20, v14
vslidedown.vi v15, v14, 1
vmv.x.s x21, v15
The divergence is already visible at the first probe after vzext.vf8:
- Spike:
x20 = 0x4f
- Ara:
x20 = 0xa04f
Then the second probe after vslidedown.vi also diverges:
- Spike:
x21 = 0xa0
- Ara:
x21 = 0x0
The control-state observations match:
- both record
x8 = 0x1b
- both record
vl = 0x1b
- both record
vtype = 0x18
To Reproduce
Build the pure-probe ELF:
riscv64-unknown-elf-gcc -nostdlib -static \
-march=rv64imfdcv_zicsr_zifencei_zfh \
-mabi=lp64d \
-T /home/projects/projects/ara-pure-probe-common.ld \
-o ara-5840-pure-probe.elf \
/home/projects/projects/ara-5840-pure-probe.S
Run Spike with VLEN = 4096:
/home/projects/projects/riscv_impls_bins/spike \
-p1 \
--isa=RV64IMAFDCV_ZICSR_ZIFENCEI_ZFH_ZVL4096B \
--log-commits \
ara-5840-pure-probe.elf > spike_vlen4096.log 2>&1
Run Ara RVFI build:
/home/projects/projects/ara/hardware/build-rvfi9/verilator/Vara_tb_verilator \
-l ram,ara-5840-pure-probe.elf,elf > ara.log 2>&1
Then compare:
- Spike commit-log observations at
0x8000004a, 0x80000052
- Ara RVFI observations at
0x8000004a, 0x80000052
- fixed probe-buffer writes at
0x80021000 and 0x80021008
Original Code:
.section .text.init
.globl _start
_start:
.option push
.option norelax
1:
auipc gp, %pcrel_hi(__global_pointer$)
addi gp, gp, %pcrel_lo(1b)
.option pop
la sp, __stack_top
la t0, trap_handler
csrw mtvec, t0
csrr t0, mstatus
li t1, 0x00003600
or t0, t0, t1
csrw mstatus, t0
csrw fcsr, x0
j user_code
user_code:
li x9, 0xa04f
vsetivli x8, 1, e16, mf4
vmv.s.x v28, x9
vsetivli x8, 27, e64, m1
vzext.vf8 v14, v28
vmv.x.s x20, v14
vslidedown.vi v15, v14, 1
vmv.x.s x21, v15
csrr x24, vl
csrr x25, vtype
li t0, 0x80021000
sd x20, 0(t0)
sd x21, 8(t0)
sd x8, 16(t0)
sd x24, 24(t0)
sd x25, 32(t0)
pass:
li a0, 0
j exit
unexpected_trap:
li a0, 0xdead
j exit
exit:
la t0, result_code
sd a0, 0(t0)
la t0, eoc_address_reg
sd a0, 0(t0)
slli t6, a0, 1
ori t6, t6, 1
la t0, tohost
sd t6, 0(t0)
1:
j 1b
.align 2
trap_handler:
j unexpected_trap
.section .data
.align 3
result_code:
.dword 0
.section .tohost,"aw",@progbits
.align 6
.globl tohost
.globl fromhost
tohost:
.dword 0
fromhost:
.dword 0
Code and ELF:
ara-5840-pure-probe.zip
Describe the bug
Under matched
VLEN = 4096on both Spike and Ara, the same pure-probe ELF produces different committed architectural results after the sequence:The divergence is already visible at the first probe after
vzext.vf8:x20 = 0x4fx20 = 0xa04fThen the second probe after
vslidedown.vialso diverges:x21 = 0xa0x21 = 0x0The control-state observations match:
x8 = 0x1bvl = 0x1bvtype = 0x18To Reproduce
Build the pure-probe ELF:
Run Spike with
VLEN = 4096:Run Ara RVFI build:
Then compare:
0x8000004a,0x800000520x8000004a,0x800000520x80021000and0x80021008Original Code:
Code and ELF:
ara-5840-pure-probe.zip