Reproducer
vsetvli zero, zero, e32, m1, tu, ma
vwaddu.wv v8, v8, v11
vsetvli a4, zero, e64, m2, ta, ma
vmv.s.x v10, zero
vredsum.vs v8, v8, v10
Steps to Reproduce
git clone https://github.com/ianfield/ara-test.git
cd ara-test/
export LLVM_RISCV=/opt/homebrew/Cellar/llvm/21.1.7/bin/
./sh/checkout.sh
./sh/build.sh --dlen=128
./sh/run.sh --sim spike -k test_vredsum.py
./sh/run.sh --sim fork -k test_vredsum.py
./sh/run.sh --sim base -k test_vredsum.py
Proposed change
valu.sv:790-792
if (is_reduction(vinsn_queue_q.vinsn[vinsn_queue_d.issue_pnt].op)
&& (vinsn_queue_d.issue_cnt != '0)
&& (result_queue_cnt_d == '0)) begin
Reproducer
Steps to Reproduce
Proposed change
valu.sv:790-792