Hello @Navaneeth-KunhiPurayil @mp-17 @suehtamacv , I was doing some verification work with the latest version of ara and found a problem with the compress instruction.
The logic of the corresponding masku.sv is as follows, but without vcompress_bit, the idx_fifo will not be pushed, then the vcompress_last_idx_d will not enter FIFO, which will eventually lead to the inability of the instruction to retire
VCOMPRESS: begin
// Select the current enable bit
vcompress_bit = masku_operand_alu_seq[vrgat_cnt_q[idx_width(NrLanes*DataWidth)-1:0]];
// Select the current index
vrgat_req_idx_d = vrgat_cnt_q;
if (&masku_operand_alu_valid && ~vrgat_idx_fifo_full && ~vrgat_req_fifo_full) begin
// Check vrgat_m_seq_bit: we can use this since VRGATHER and VCOMPRESS are mutually exclusive
// and the masku_operand_m is used in different ways
if (vcompress_bit) begin
// Push this index and address if the fifos are free and if the mask bit is set
vrgat_idx_fifo_push = 1'b1;
vrgat_req_fifo_push = 1'b1;
// Increase the number of elements to write
vcompress_cnt_d = vcompress_cnt_q + 1;
end
end
Hello @Navaneeth-KunhiPurayil @mp-17 @suehtamacv , I was doing some verification work with the latest version of ara and found a problem with the compress instruction.
The logic of the corresponding masku.sv is as follows, but without vcompress_bit, the idx_fifo will not be pushed, then the vcompress_last_idx_d will not enter FIFO, which will eventually lead to the inability of the instruction to retire