Skip to content

@chipfoundry ChipFoundry

Change the repository type filter

All

    Repositories list

    98 repositories

    • cf-precheck

      Public
      Shell
      •
      Apache License 2.0
      •1•2•42•0•Updated Jul 13, 2026Jul 13, 2026

    • CF_ADC

      Public
      Verilog
      •1•0•0•0•Updated Jul 2, 2026Jul 2, 2026

    • caravel_board

      Public
      C
      •0•1•10•1•Updated Jun 30, 2026Jun 30, 2026

    • CF_FPGA_testchip

      Public
      Verilog
      •
      Apache License 2.0
      •1•0•0•0•Updated Jun 15, 2026Jun 15, 2026

    • chipfoundry_discover

      Public
      ChipDiscover
      1•0•0•0•Updated Jun 13, 2026Jun 13, 2026

    • nydesign-cc2509

      Public
      Tiny Tapeout SKY 25b shuttle using sky130A PDK on ChipFoundry CC2511 MPW
      Verilog
      •
      Apache License 2.0
      •12•0•0•0•Updated Jun 10, 2026Jun 10, 2026

    • Neuromorphic_X1_32x32

      Public
      For chip foundry platform
      Verilog
      •6•0•0•0•Updated May 31, 2026May 31, 2026

    • tt-private-index

      Public
      0•0•0•0•Updated May 28, 2026May 28, 2026

    • tt-commander-app

      Public
      Web app to control the Tiny Tapeout Demo board
      TypeScript
      •
      Other
      •11•0•0•0•Updated May 28, 2026May 28, 2026

    • nydesign-ci2605

      Public
      NYDesign CI2605 Tiny Tapeout chip
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated May 23, 2026May 23, 2026

    • CF_chip_id

      Public archive
      DEPRECATED -- replaced by CF_owire_id. The clock requirement made this IP a poor fit for OpenFrame designs.
      0•0•0•0•Updated May 20, 2026May 20, 2026

    • CF_owire_id

      Public
      Dallas/Maxim 1-Wire chip-ID slave for ChipFoundry OpenFrame projects. Publishes mask_rev as a DS2401-compatible 64-bit ROM. No external clock required.
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated May 20, 2026May 20, 2026

    • cf-cli

      Public
      Python
      •
      Apache License 2.0
      •3•0•2•0•Updated May 13, 2026May 13, 2026

    • breakout-pcb

      Public
      Tiny Tapeout breakout PCBs
      HTML
      •
      Apache License 2.0
      •6•0•0•0•Updated May 12, 2026May 12, 2026

    • breakout-pcb-standalone

      Public
      HTML
      •
      Apache License 2.0
      •0•0•0•0•Updated May 12, 2026May 12, 2026

    • sky130-fabulous-testchip

      Public
      A test chip featuring three different FPGA fabrics and custom padring, compatible with Caravel's bondpads.
      Verilog
      •2•0•0•1•Updated May 12, 2026May 12, 2026

    • caravel_user_project

      Public template
      Verilog
      •
      Apache License 2.0
      •17•19•57•7•Updated May 12, 2026May 12, 2026

    • CF_SRAM_8192x32

      Public
      32KB SRAM macro (8192 words × 32 bits) built from 8 × 1024x32 SRAM macros with Wishbone B4 interface
      Verilog
      •
      Apache License 2.0
      •0•1•0•0•Updated May 11, 2026May 11, 2026

    • CF_SRAM_16384x32

      Public
      Commercial 16384x32 SRAM (64KB) - Wishbone compliant memory macro
      Verilog
      •
      Apache License 2.0
      •0•1•0•0•Updated May 11, 2026May 11, 2026

    • CF_SRAM_4096x32

      Public
      Verilog
      •
      Apache License 2.0
      •0•0•2•0•Updated May 11, 2026May 11, 2026

    • tt-micropython-firmware

      Public
      TinyTapeout demo pcb's RP2040 functionality
      Python
      •
      GNU Lesser General Public License v2.1
      •15•0•0•0•Updated May 8, 2026May 8, 2026

    • ip_unit

      Public
      IP unit monorepo (cocotb/pyuvm verification)
      Verilog
      •0•0•0•0•Updated Apr 26, 2026Apr 26, 2026

    • CF_I2C

      Public
      Verilog
      •
      Other
      •1•0•6•4•Updated Apr 26, 2026Apr 26, 2026

    • CF_SPI

      Public
      Verilog
      •
      Other
      •1•0•5•8•Updated Apr 26, 2026Apr 26, 2026

    • CF_UART

      Public
      Verilog
      •
      Other
      •1•0•8•3•Updated Apr 26, 2026Apr 26, 2026

    • CF_I2S

      Public
      Verilog
      •
      Other
      •1•0•6•2•Updated Apr 26, 2026Apr 26, 2026

    • CF_TMR32

      Public
      Python
      •
      Other
      •1•0•2•5•Updated Apr 23, 2026Apr 23, 2026

    • CF_SHA256

      Public
      Verilog
      •5•0•0•0•Updated Apr 23, 2026Apr 23, 2026

    • cf_verify

      Public
      Universal IP Verification Framework for ChipFoundry IPs — pyuvm + cocotb
      Python
      •0•0•0•0•Updated Apr 14, 2026Apr 14, 2026

    • caravel-lite

      Public
      Verilog
      •
      Apache License 2.0
      •1•0•5•0•Updated Mar 30, 2026Mar 30, 2026
    ProTip! When viewing an organization's repositories, you can use the props. filter to filter by custom property.