Add FuseSoC support

This adds support for FuseSoC, currently for the verilator model only.

Signed-off-by: Stefan Wallentowitz <stefan.wallentowitz@hm.edu>

Author: wallento

.gitignore

@@ -15,6 +15,6 @@ TAGS
 .build-rtl
 .lib-rtl
 .opt-rtl
-/build
+build/
 /Bender.lock
 /Bender.local

cv32e40p.core

@@ -0,0 +1,49 @@
+CAPI=2:
+# Copyright OpenHW Group contributors.
+# Licensed under the Solderpad Hardware Licence, Version 2.0 , see LICENSE for details.
+name: "openhw:cv32e40p:core:0.1"
+description: "CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform"
+
+filesets:
+  files_rtl:
+    depend:
+      - pulp-platform.org::fpnew
+    files:
+      - rtl/include/apu_macros.sv: {is_include_file: true}
+      - rtl/include/riscv_config.sv: {is_include_file: true}
+      - rtl/include/apu_core_package.sv
+      - rtl/include/riscv_defines.sv
+      - rtl/include/riscv_tracer_defines.sv
+      - rtl/riscv_if_stage.sv
+      - rtl/riscv_tracer.sv
+      - rtl/cv32e40p_sim_clock_gate.sv
+      - rtl/riscv_cs_registers.sv
+      - rtl/riscv_register_file.sv
+      - rtl/riscv_load_store_unit.sv
+      - rtl/riscv_id_stage.sv
+      - rtl/riscv_decoder.sv
+      - rtl/riscv_compressed_decoder.sv
+      - rtl/riscv_fetch_fifo.sv
+      - rtl/riscv_prefetch_buffer.sv
+      - rtl/riscv_prefetch_L0_buffer.sv
+      - rtl/riscv_L0_buffer.sv
+      - rtl/riscv_hwloop_regs.sv
+      - rtl/riscv_hwloop_controller.sv
+      - rtl/riscv_mult.sv
+      - rtl/register_file_test_wrap.sv
+      - rtl/riscv_int_controller.sv
+      - rtl/riscv_ex_stage.sv
+      - rtl/riscv_alu_div.sv
+      - rtl/riscv_alu.sv
+      - rtl/riscv_ff_one.sv
+      - rtl/riscv_popcnt.sv
+      - rtl/riscv_pmp.sv
+      - rtl/riscv_apu_disp.sv
+      - rtl/riscv_controller.sv
+      - rtl/riscv_core.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_rtl

tb/core/Makefile.fusesoc

@@ -0,0 +1,7 @@
+build:
+	fusesoc --cores-root=../../ run --target=sim --setup --build openhw:cv32e40p:testbench
+
+run:
+	build/openhw_cv32e40p_testbench_0.1/sim-verilator/Vtb_top_verilator "+firmware=firmware/firmware.hex"
+
+.PHONY: build run

tb/core/testbench.core

@@ -0,0 +1,30 @@
+CAPI=2:
+# Copyright OpenHW Group contributors.
+# Licensed under the Solderpad Hardware Licence, Version 2.0 , see LICENSE for details.
+name: "openhw:cv32e40p:testbench:0.1"
+description: "Testbench for CV32E40P"
+filesets:
+  files_sim_verilator:
+    depend:
+      - openhw:cv32e40p:core
+    files:
+      - tb_top_verilator.sv
+      - riscv_wrapper.sv
+      - mm_ram.sv
+      - dp_ram.sv
+      - amo_shim.sv
+      - tb_top_verilator.cpp: { file_type: cppSource }
+    file_type: systemVerilogSource
+
+targets:
+  sim:
+    filesets:
+      - files_sim_verilator
+    toplevel: tb_top_verilator
+    default_tool: verilator
+    tools:
+      verilator:
+        mode: cc
+        verilator_options:
+          - "-Wno-fatal"
+          - "--trace"

tb/verilator-model/Makefile.fusesoc

@@ -0,0 +1,4 @@
+build:
+	fusesoc --cores-root=../../ run --target=sim --setup --build openhw:cv32e40p:verilator-model
+
+.PHONY: build

tb/verilator-model/testbench.core

@@ -0,0 +1,28 @@
+CAPI=2:
+# Copyright OpenHW Group contributors.
+# Licensed under the Solderpad Hardware Licence, Version 2.0 , see LICENSE for details.
+name: "openhw:cv32e40p:verilator-model:0.1"
+description: "Verilator testbench for CV32E40P"
+filesets:
+  files_sim_verilator:
+    depend:
+      - openhw:cv32e40p:core
+    files:
+      - dp_ram.sv
+      - ram.sv
+      - top.sv
+      - testbench.cpp: { file_type: cppSource }
+    file_type: systemVerilogSource
+
+targets:
+  sim:
+    filesets:
+      - files_sim_verilator
+    toplevel: top
+    default_tool: verilator
+    tools:
+      verilator:
+        mode: cc
+        verilator_options:
+          - "-Wno-fatal"
+          - "--trace"