A small INT8 systolic-array accelerator on the Basys 3, driven by a custom CPU and instruction set. The goal is to run neural network inference end-to-end on real hardware. A scalar CPU sequences a 4×4 weight-stationary systolic array through a small custom ISA.
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ISA, assembler, golden model, PE, and 3-stage scalar CPU are built and cocotb-verified. Systolic array integration is next.
| Numeric system | INT8 in, INT32 accumulate |
| Array | 4×4, weight-stationary |
| CPU | 3-stage scalar (fetch / decode / execute) |
| ISA | 10 custom opcodes, 32-bit encoding |
| Target | Basys 3 (Artix-7, XC7A35T) |
| Verification | cocotb golden model in NumPy |
[31:26] opcode | [25:21] rd | [20:16] rs1 | [15:0] imm
| Op | Mnemonic | Operands | Action |
|---|---|---|---|
| 0x00 | LI |
Rd, Imm | Rd ← Imm |
| 0x01 | ADDI |
Rd, Rs1, Imm | Rd ← Rs1 + Imm |
| 0x02 | LOOP |
Rs1, Imm | Rs1 ← Rs1 − 1; branch if Rs1 ≠ 0 |
| 0x03 | M_LD_W |
Rs1 | load weight tile into array |
| 0x04 | M_MUL |
Rd, Rs1 | run systolic matmul |
| 0x05 | ACT |
Rs1, Imm | ReLU activation |
| 0x06 | STATUS |
Rd | Rd ← matrix unit status |
| 0x07 | HALT |
— | stop |
| 0x08 | M_LD_A |
Rs1 | load activation tile |
| 0x09 | M_ST |
Rs1, Imm | store accumulator result |
Turns .asm into the .mem hex the hardware loads.
python3 assembler/assembler.py assembler/test.asm assembler/test.mem
Bit-accurate NumPy reference for the full MNIST forward pass - INT8 quantization, integer matmul, INT32 accumulation, ReLU, argmax. Runs at 98.6% accuracy. Will serve as the verification oracle once the systolic array produces MNIST-scale outputs to check against; PE and CPU tests so far are verified against pre-computed expected values.
pip install numpy tensorflow
python3 golden_model/golden_model.py
Each block lives in its own folder, split into src/ (design) and sim/ (cocotb testbench + Makefile).
Single weight-stationary processing element. INT8×INT8 → INT32 accumulate, 1-cycle registered output. Verified against pre-computed MAC values across signed weight/activation combinations.
cd rtl/pe/sim && make
3-stage scalar CPU running the ISA above. Verified with a pre-assembled integration test covering LI, ADDI, LOOP and STATUS, cross-checked against a GTKWave trace and cocotb.
cd rtl/cpu/sim && make