Skip to content

Commit f41338c

Browse files
adamperlinadamperlin
committed
Add Wasm32 instruction set description along with PackedSimd, Vector128 definitions for Wasm
1 parent fdec023 commit f41338c

8 files changed

Lines changed: 144 additions & 6 deletions

File tree

‎src/coreclr/inc/corinfoinstructionset.h‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,11 @@ enum CORINFO_InstructionSet
6161
InstructionSet_Zbb=3,
6262
InstructionSet_Zbs=4,
6363
#endif // TARGET_RISCV64
64+
#ifdef TARGET_WASM
65+
InstructionSet_WasmBase=1,
66+
InstructionSet_PackedSimd=2,
67+
InstructionSet_Vector128=3,
68+
#endif // TARGET_WASM
6469
#ifdef TARGET_AMD64
6570
InstructionSet_X86Base=1,
6671
InstructionSet_AVX=2,
@@ -284,6 +289,8 @@ struct CORINFO_InstructionSetFlags
284289
#endif // TARGET_ARM64
285290
#ifdef TARGET_RISCV64
286291
#endif // TARGET_RISCV64
292+
#ifdef TARGET_WASM
293+
#endif // TARGET_WASM
287294
#ifdef TARGET_AMD64
288295
if (HasInstructionSet(InstructionSet_X86Base))
289296
AddInstructionSet(InstructionSet_X86Base_X64);
@@ -448,6 +455,12 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
448455
if (resultflags.HasInstructionSet(InstructionSet_Zbs) && !resultflags.HasInstructionSet(InstructionSet_RiscV64Base))
449456
resultflags.RemoveInstructionSet(InstructionSet_Zbs);
450457
#endif // TARGET_RISCV64
458+
#ifdef TARGET_WASM
459+
if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_PackedSimd))
460+
resultflags.RemoveInstructionSet(InstructionSet_Vector128);
461+
if (resultflags.HasInstructionSet(InstructionSet_PackedSimd) && !resultflags.HasInstructionSet(InstructionSet_WasmBase))
462+
resultflags.RemoveInstructionSet(InstructionSet_PackedSimd);
463+
#endif // TARGET_WASM
451464
#ifdef TARGET_AMD64
452465
if (resultflags.HasInstructionSet(InstructionSet_X86Base) && !resultflags.HasInstructionSet(InstructionSet_X86Base_X64))
453466
resultflags.RemoveInstructionSet(InstructionSet_X86Base);
@@ -742,6 +755,14 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
742755
case InstructionSet_Zbs :
743756
return "Zbs";
744757
#endif // TARGET_RISCV64
758+
#ifdef TARGET_WASM
759+
case InstructionSet_WasmBase :
760+
return "WasmBase";
761+
case InstructionSet_PackedSimd :
762+
return "PackedSimd";
763+
case InstructionSet_Vector128 :
764+
return "Vector128";
765+
#endif // TARGET_WASM
745766
#ifdef TARGET_AMD64
746767
case InstructionSet_X86Base :
747768
return "X86Base";
@@ -943,6 +964,10 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
943964
case READYTORUN_INSTRUCTION_Zbb: return InstructionSet_Zbb;
944965
case READYTORUN_INSTRUCTION_Zbs: return InstructionSet_Zbs;
945966
#endif // TARGET_RISCV64
967+
#ifdef TARGET_WASM
968+
case READYTORUN_INSTRUCTION_WasmBase: return InstructionSet_WasmBase;
969+
case READYTORUN_INSTRUCTION_PackedSimd: return InstructionSet_PackedSimd;
970+
#endif // TARGET_WASM
946971
#ifdef TARGET_AMD64
947972
case READYTORUN_INSTRUCTION_X86Base: return InstructionSet_X86Base;
948973
case READYTORUN_INSTRUCTION_Sse: return InstructionSet_X86Base;

‎src/coreclr/inc/jiteeversionguid.h‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -37,11 +37,11 @@
3737

3838
#include <minipal/guid.h>
3939

40-
constexpr GUID JITEEVersionIdentifier = { /* 31a04b06-915e-42a0-bbd2-c9c397677ae5 */
41-
0x31a04b06,
42-
0x915e,
43-
0x42a0,
44-
{0xbb, 0xd2, 0xc9, 0xc3, 0x97, 0x67, 0x7a, 0xe5}
40+
constexpr GUID JITEEVersionIdentifier = { /* 00584b4c-9681-41ae-87be-17bc0d7643a3 */
41+
0x00584b4c,
42+
0x9681,
43+
0x41ae,
44+
{0x87, 0xbe, 0x17, 0xbc, 0x0d, 0x76, 0x43, 0xa3}
4545
};
4646

4747
#endif // JIT_EE_VERSIONING_GUID_H

‎src/coreclr/inc/readytoruninstructionset.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,8 @@ enum ReadyToRunInstructionSet
9898
READYTORUN_INSTRUCTION_SveAes=88,
9999
READYTORUN_INSTRUCTION_SveSha3=89,
100100
READYTORUN_INSTRUCTION_SveSm4=90,
101+
READYTORUN_INSTRUCTION_WasmBase=91,
102+
READYTORUN_INSTRUCTION_PackedSimd=92,
101103

102104
};
103105

‎src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -101,5 +101,7 @@ public enum ReadyToRunInstructionSet
101101
SveAes = 88,
102102
SveSha3 = 89,
103103
SveSm4 = 90,
104+
WasmBase = 91,
105+
PackedSimd = 92,
104106
}
105107
}

‎src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSetHelper.cs‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,18 @@ public static class ReadyToRunInstructionSetHelper
7878
}
7979
}
8080

81+
case TargetArchitecture.Wasm32:
82+
{
83+
switch (instructionSet)
84+
{
85+
case InstructionSet.Wasm32_WasmBase: return ReadyToRunInstructionSet.WasmBase;
86+
case InstructionSet.Wasm32_PackedSimd: return ReadyToRunInstructionSet.PackedSimd;
87+
case InstructionSet.Wasm32_Vector128: return null;
88+
89+
default: throw new Exception("Unknown instruction set");
90+
}
91+
}
92+
8193
case TargetArchitecture.X64:
8294
{
8395
switch (instructionSet)

‎src/coreclr/tools/Common/JitInterface/CorInfoInstructionSet.cs‎

Lines changed: 82 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,9 @@ public enum InstructionSet
5959
RiscV64_Zba = InstructionSet_RiscV64.Zba,
6060
RiscV64_Zbb = InstructionSet_RiscV64.Zbb,
6161
RiscV64_Zbs = InstructionSet_RiscV64.Zbs,
62+
Wasm32_WasmBase = InstructionSet_Wasm32.WasmBase,
63+
Wasm32_PackedSimd = InstructionSet_Wasm32.PackedSimd,
64+
Wasm32_Vector128 = InstructionSet_Wasm32.Vector128,
6265
X64_X86Base = InstructionSet_X64.X86Base,
6366
X64_AVX = InstructionSet_X64.AVX,
6467
X64_AVX2 = InstructionSet_X64.AVX2,
@@ -206,6 +209,15 @@ public enum InstructionSet_RiscV64
206209
Zbs = 4,
207210
}
208211

212+
public enum InstructionSet_Wasm32
213+
{
214+
ILLEGAL = InstructionSet.ILLEGAL,
215+
NONE = InstructionSet.NONE,
216+
WasmBase = 1,
217+
PackedSimd = 2,
218+
Vector128 = 3,
219+
}
220+
209221
public enum InstructionSet_X64
210222
{
211223
ILLEGAL = InstructionSet.ILLEGAL,
@@ -319,6 +331,8 @@ public unsafe struct InstructionSetFlags : IEnumerable<InstructionSet>
319331

320332
public IEnumerable<InstructionSet_RiscV64> RiscV64Flags => this.Select((x) => (InstructionSet_RiscV64)x);
321333

334+
public IEnumerable<InstructionSet_Wasm32> Wasm32Flags => this.Select((x) => (InstructionSet_Wasm32)x);
335+
322336
public IEnumerable<InstructionSet_X64> X64Flags => this.Select((x) => (InstructionSet_X64)x);
323337

324338
public IEnumerable<InstructionSet_X86> X86Flags => this.Select((x) => (InstructionSet_X86)x);
@@ -438,6 +452,12 @@ public static InstructionSet ConvertToImpliedInstructionSetForVectorInstructionS
438452
case InstructionSet.ARM64_VectorT: return InstructionSet.ARM64_Sve;
439453
}
440454
break;
455+
case TargetArchitecture.Wasm32:
456+
switch (input)
457+
{
458+
case InstructionSet.Wasm32_Vector128: return InstructionSet.Wasm32_PackedSimd;
459+
}
460+
break;
441461
case TargetArchitecture.X64:
442462
switch (input)
443463
{
@@ -581,6 +601,13 @@ public static InstructionSetFlags ExpandInstructionSetByImplicationHelper(Target
581601
resultflags.AddInstructionSet(InstructionSet.RiscV64_RiscV64Base);
582602
break;
583603

604+
case TargetArchitecture.Wasm32:
605+
if (resultflags.HasInstructionSet(InstructionSet.Wasm32_Vector128))
606+
resultflags.AddInstructionSet(InstructionSet.Wasm32_PackedSimd);
607+
if (resultflags.HasInstructionSet(InstructionSet.Wasm32_PackedSimd))
608+
resultflags.AddInstructionSet(InstructionSet.Wasm32_WasmBase);
609+
break;
610+
584611
case TargetArchitecture.X64:
585612
if (resultflags.HasInstructionSet(InstructionSet.X64_X86Base))
586613
resultflags.AddInstructionSet(InstructionSet.X64_X86Base_X64);
@@ -879,6 +906,13 @@ private static InstructionSetFlags ExpandInstructionSetByReverseImplicationHelpe
879906
resultflags.AddInstructionSet(InstructionSet.RiscV64_Zbs);
880907
break;
881908

909+
case TargetArchitecture.Wasm32:
910+
if (resultflags.HasInstructionSet(InstructionSet.Wasm32_PackedSimd))
911+
resultflags.AddInstructionSet(InstructionSet.Wasm32_Vector128);
912+
if (resultflags.HasInstructionSet(InstructionSet.Wasm32_WasmBase))
913+
resultflags.AddInstructionSet(InstructionSet.Wasm32_PackedSimd);
914+
break;
915+
882916
case TargetArchitecture.X64:
883917
if (resultflags.HasInstructionSet(InstructionSet.X64_X86Base_X64))
884918
resultflags.AddInstructionSet(InstructionSet.X64_X86Base);
@@ -1124,6 +1158,12 @@ public static IEnumerable<InstructionSetInfo> ArchitectureToValidInstructionSets
11241158
yield return new InstructionSetInfo("zbs", "", InstructionSet.RiscV64_Zbs, true);
11251159
break;
11261160

1161+
case TargetArchitecture.Wasm32:
1162+
yield return new InstructionSetInfo("base", "WasmBase", InstructionSet.Wasm32_WasmBase, true);
1163+
yield return new InstructionSetInfo("simd128", "PackedSimd", InstructionSet.Wasm32_PackedSimd, true);
1164+
yield return new InstructionSetInfo("Vector128", "", InstructionSet.Wasm32_Vector128, false);
1165+
break;
1166+
11271167
case TargetArchitecture.X64:
11281168
yield return new InstructionSetInfo("base", "X86Base", InstructionSet.X64_X86Base, true);
11291169
yield return new InstructionSetInfo("base", "Sse", InstructionSet.X64_X86Base, true);
@@ -1315,6 +1355,9 @@ public void Set64BitInstructionSetVariants(TargetArchitecture architecture)
13151355
case TargetArchitecture.RiscV64:
13161356
break;
13171357

1358+
case TargetArchitecture.Wasm32:
1359+
break;
1360+
13181361
case TargetArchitecture.X64:
13191362
if (HasInstructionSet(InstructionSet.X64_X86Base))
13201363
AddInstructionSet(InstructionSet.X64_X86Base_X64);
@@ -1381,6 +1424,9 @@ public void Set64BitInstructionSetVariantsUnconditionally(TargetArchitecture arc
13811424
case TargetArchitecture.RiscV64:
13821425
break;
13831426

1427+
case TargetArchitecture.Wasm32:
1428+
break;
1429+
13841430
case TargetArchitecture.X64:
13851431
AddInstructionSet(InstructionSet.X64_X86Base_X64);
13861432
AddInstructionSet(InstructionSet.X64_AVX_X64);
@@ -1449,6 +1495,10 @@ public static InstructionSet LookupPlatformIntrinsicInstructionSet(TargetArchite
14491495
platformIntrinsicNamespace = "System.Runtime.Intrinsics.Arm";
14501496
break;
14511497

1498+
case TargetArchitecture.Wasm32:
1499+
platformIntrinsicNamespace = "System.Runtime.Intrinsics.Wasm";
1500+
break;
1501+
14521502
case TargetArchitecture.X64:
14531503
platformIntrinsicNamespace = "System.Runtime.Intrinsics.X86";
14541504
break;
@@ -1566,6 +1616,18 @@ public static InstructionSet LookupPlatformIntrinsicInstructionSet(TargetArchite
15661616
case TargetArchitecture.RiscV64:
15671617
switch (typeName)
15681618
{
1619+
default:
1620+
return InstructionSet.ILLEGAL;
1621+
}
1622+
case TargetArchitecture.Wasm32:
1623+
switch (typeName)
1624+
{
1625+
case "WasmBase":
1626+
return InstructionSet.Wasm32_WasmBase;
1627+
1628+
case "PackedSimd":
1629+
return InstructionSet.Wasm32_PackedSimd;
1630+
15691631
default:
15701632
return InstructionSet.ILLEGAL;
15711633
}
@@ -2243,6 +2305,26 @@ public static IEnumerable<MetadataType> LookupPlatformIntrinsicTypes(TypeSystemC
22432305
}
22442306
break;
22452307

2308+
case (InstructionSet.Wasm32_WasmBase, TargetArchitecture.Wasm32):
2309+
{
2310+
var type = context.SystemModule.GetType("System.Runtime.Intrinsics.Wasm"u8, "WasmBase"u8, false);
2311+
if (type != null)
2312+
{
2313+
yield return type;
2314+
}
2315+
}
2316+
break;
2317+
2318+
case (InstructionSet.Wasm32_PackedSimd, TargetArchitecture.Wasm32):
2319+
{
2320+
var type = context.SystemModule.GetType("System.Runtime.Intrinsics.Wasm"u8, "PackedSimd"u8, false);
2321+
if (type != null)
2322+
{
2323+
yield return type;
2324+
}
2325+
}
2326+
break;
2327+
22462328
case (InstructionSet.X64_X86Base, TargetArchitecture.X64):
22472329
case (InstructionSet.X64_X86Base_X64, TargetArchitecture.X64):
22482330
{

‎src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetDesc.txt‎

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626
; DO NOT CHANGE R2R NUMERIC VALUES OF THE EXISTING SETS. Changing R2R numeric values definitions would be R2R format breaking change.
2727

2828
; The ISA definitions should also be mapped to `hwintrinsicIsaRangeArray` in hwintrinsic.cpp.
29-
; NEXT_AVAILABLE_R2R_BIT = 91
29+
; NEXT_AVAILABLE_R2R_BIT = 93
3030

3131
; Definition of X86 instruction sets
3232
definearch ,X86 ,32Bit ,X64, X64, X86
@@ -302,3 +302,15 @@ instructionsetgroup ,armv8.6-a ,ARM64 ,armv8.5-a
302302

303303
; Technically, apple-m1 is v8.5+
304304
instructionsetgroup ,apple-m1 ,ARM64 ,armv8.5-a
305+
306+
307+
; Definition of Wasm instruction sets
308+
definearch ,Wasm32 ,32Bit , , ,Wasm
309+
310+
instructionset ,Wasm32 ,WasmBase , ,91 ,WasmBase ,base
311+
instructionset ,Wasm32 ,PackedSimd , ,92 ,PackedSimd ,simd128
312+
instructionset ,Wasm32 , , , ,Vector128 ,
313+
314+
vectorinstructionset ,Wasm32 ,Vector128
315+
implication ,Wasm32 ,Vector128 ,PackedSimd
316+
implication ,Wasm32 ,PackedSimd ,WasmBase

‎src/coreclr/tools/Common/JitInterface/ThunkGenerator/InstructionSetGenerator.cs‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -121,6 +121,9 @@ private static string ArchToIfDefArch(string arch)
121121
return "AMD64";
122122
if (arch == "RiscV64")
123123
return "RISCV64";
124+
if (arch == "Wasm32")
125+
return "WASM";
126+
124127
return arch;
125128
}
126129

0 commit comments

Comments
 (0)