Arm64: Don't use GT_LEA for masks (#128684)

genCreateAddrMode() will need rewrites for scalable vectors/masks. Until
then, avoid using LEA nodes.

In addition, remove invalid code for LDR/STR from the emitter. The
emitter expects the offset to be a multiple of the VL/PL

Fixes #127605

Author: a74nh

src/coreclr/jit/emitarm64.cpp

@@ -2523,13 +2523,6 @@ emitter::code_t emitter::emitInsCode(instruction ins, insFormat fmt)
     return (imm >= -256) && (imm <= 255);
 }
 
-// true if this 'imm' can be encoded as the offset in an unscaled ldr/str instruction
-/*static*/ bool emitter::emitIns_valid_imm_for_scaled_sve_ldst_offset(INT64 imm)
-{
-    // TODO-SVE: This assumes 128bit SVE.
-    return ((imm % 16) == 0 && (imm / 16) <= 255 && (imm / 16) >= -256);
-}
-
 // true if this 'imm' can be encoded as the offset in a ldr/str instruction
 /*static*/ bool emitter::emitIns_valid_imm_for_ldst_offset(INT64 imm, emitAttr attr)
 {

src/coreclr/jit/emitarm64.h

@@ -1058,9 +1058,6 @@ static bool emitIns_valid_imm_for_ldst_offset(INT64 imm, emitAttr size);
 // true if this 'imm' can be encoded as the offset in an unscaled ldr/str instruction
 static bool emitIns_valid_imm_for_unscaled_ldst_offset(INT64 imm);
 
-// true if this 'imm' can be encoded as the offset in an scaled SVE ldr/str instruction
-static bool emitIns_valid_imm_for_scaled_sve_ldst_offset(INT64 imm);
-
 // true if this 'imm' can be encoded as a input operand to a ccmp instruction
 static bool emitIns_valid_imm_for_ccmp(INT64 imm);
 

src/coreclr/jit/emitarm64sve.cpp

@@ -2741,27 +2741,12 @@ void emitter::emitInsSve_R_R_I(instruction     ins,
         case INS_sve_ldr:
             assert(insOptsNone(opt));
             assert(isScalableVectorSize(size));
-            assert(isGeneralRegister(reg2)); // nnnnn
+            assert(isGeneralRegisterOrSP(reg2)); // nnnnn
             assert(insScalableOptsNone(sopt));
-
-            // imm is the number of bytes to offset by. The instruction requires a multiple of the
-            // vector length ([#imm mul vl]). If it doesn't fit then stash the resulting address
-            // into a register.
-            if (emitIns_valid_imm_for_scaled_sve_ldst_offset(imm))
-            {
-                // TODO-SVE: This assumes 128bit SVE.
-                imm = imm / 16;
-            }
-            else
-            {
-                regNumber rsvdReg = codeGen->rsGetRsvdReg();
-                codeGen->instGen_Set_Reg_To_Base_Plus_Imm(EA_PTRSIZE, rsvdReg, reg2, imm);
-                reg2 = rsvdReg;
-                imm  = 0;
-            }
-
             assert(isValidSimm<9>(imm));
 
+            reg2 = encodingSPtoZR(reg2);
+
             if (isVectorRegister(reg1))
             {
                 fmt = IF_SVE_IE_2A;
@@ -2776,27 +2761,12 @@ void emitter::emitInsSve_R_R_I(instruction     ins,
         case INS_sve_str:
             assert(insOptsNone(opt));
             assert(isScalableVectorSize(size));
-            assert(isGeneralRegister(reg2)); // nnnnn
+            assert(isGeneralRegisterOrSP(reg2)); // nnnnn
             assert(insScalableOptsNone(sopt));
-
-            // imm is the number of bytes to offset by. The instruction requires a multiple of the
-            // vector length ([#imm mul vl]). If it doesn't fit then stash the resulting address
-            // into a register.
-            if (emitIns_valid_imm_for_scaled_sve_ldst_offset(imm))
-            {
-                // TODO-SVE: This assumes 128bit SVE.
-                imm = imm / 16;
-            }
-            else
-            {
-                regNumber rsvdReg = codeGen->rsGetRsvdReg();
-                codeGen->instGen_Set_Reg_To_Base_Plus_Imm(EA_PTRSIZE, rsvdReg, reg2, imm);
-                reg2 = rsvdReg;
-                imm  = 0;
-            }
-
             assert(isValidSimm<9>(imm));
 
+            reg2 = encodingSPtoZR(reg2);
+
             if (isVectorRegister(reg1))
             {
                 fmt = IF_SVE_JH_2A;

src/coreclr/jit/lower.cpp

@@ -7679,6 +7679,12 @@ bool Lowering::TryCreateAddrMode(GenTree* addr, bool isContainable, GenTree* par
         // because we won't be able to use ldar/star
         return false;
     }
+
+    // TODO-SVE: Create an addressable node containing an index scaled by VL or PL
+    if (parent->TypeIs(TYP_MASK, TYP_SIMD))
+    {
+        return false;
+    }
 #endif
 
     GenTree* base   = nullptr;