Align thunk gen formating with dotnet-format (#128785)

While working on new instructions, I noticed inconsistent formatting
with dotnet-format. This PR updates the thunk generator so it produces
properly formatted code from the get go.

Author: am11

src/coreclr/tools/Common/Internal/Runtime/ReadyToRunInstructionSet.cs

@@ -12,95 +12,94 @@ namespace Internal.ReadyToRunConstants
 {
     public enum ReadyToRunInstructionSet
     {
-        Sse=1,
-        Sse2=2,
-        Sse3=3,
-        Ssse3=4,
-        Sse41=5,
-        Sse42=6,
-        Avx=7,
-        Avx2=8,
-        Aes=9,
-        Bmi1=10,
-        Bmi2=11,
-        Fma=12,
-        Lzcnt=13,
-        Pclmulqdq=14,
-        Popcnt=15,
-        ArmBase=16,
-        AdvSimd=17,
-        Crc32=18,
-        Sha1=19,
-        Sha256=20,
-        Atomics=21,
-        X86Base=22,
-        Dp=23,
-        Rdm=24,
-        AvxVnni=25,
-        Rcpc=26,
-        Movbe=27,
-        X86Serialize=28,
-        Avx512F=29,
-        Avx512F_VL=30,
-        Avx512BW=31,
-        Avx512BW_VL=32,
-        Avx512CD=33,
-        Avx512CD_VL=34,
-        Avx512DQ=35,
-        Avx512DQ_VL=36,
-        Avx512Vbmi=37,
-        Avx512Vbmi_VL=38,
-        VectorT128=39,
-        VectorT256=40,
-        VectorT512=41,
-        Rcpc2=42,
-        Sve=43,
-        Avx10v1=44,
-        Avx10v1_V512=46,
-        Evex=47,
-        Apx=48,
-        Pclmulqdq_V256=49,
-        Pclmulqdq_V512=50,
-        Avx10v2=51,
-        Avx10v2_V512=52,
-        Gfni=53,
-        Gfni_V256=54,
-        Gfni_V512=55,
-        RiscV64Base=56,
-        Zba=57,
-        Zbb=58,
-        Sve2=59,
-        AvxVnniInt8=60,
-        AvxVnniInt8_V512=61,
-        AvxVnniInt16=62,
-        AvxVnniInt16_V512=63,
-        Aes_V256=64,
-        Aes_V512=65,
-        AvxIfma=66,
-        F16C=67,
-        Sha=68,
-        WaitPkg=69,
-        Avx512Bitalg=70,
-        Avx512Bitalg_VL=71,
-        Avx512Bf16=72,
-        Avx512Bf16_VL=73,
-        Avx512Fp16=74,
-        Avx512Fp16_VL=75,
-        Avx512Ifma=76,
-        Avx512Vbmi2=77,
-        Avx512Vbmi2_VL=78,
-        Avx512Vnni=79,
-        Avx512Vp2intersect=80,
-        Avx512Vp2intersect_VL=81,
-        Avx512Vpopcntdq=82,
-        Avx512Vpopcntdq_VL=83,
-        Zbs=84,
-        Avx512Bmm=85,
-        Sha3=86,
-        Sm4=87,
-        SveAes=88,
-        SveSha3=89,
-        SveSm4=90,
-
+        Sse = 1,
+        Sse2 = 2,
+        Sse3 = 3,
+        Ssse3 = 4,
+        Sse41 = 5,
+        Sse42 = 6,
+        Avx = 7,
+        Avx2 = 8,
+        Aes = 9,
+        Bmi1 = 10,
+        Bmi2 = 11,
+        Fma = 12,
+        Lzcnt = 13,
+        Pclmulqdq = 14,
+        Popcnt = 15,
+        ArmBase = 16,
+        AdvSimd = 17,
+        Crc32 = 18,
+        Sha1 = 19,
+        Sha256 = 20,
+        Atomics = 21,
+        X86Base = 22,
+        Dp = 23,
+        Rdm = 24,
+        AvxVnni = 25,
+        Rcpc = 26,
+        Movbe = 27,
+        X86Serialize = 28,
+        Avx512F = 29,
+        Avx512F_VL = 30,
+        Avx512BW = 31,
+        Avx512BW_VL = 32,
+        Avx512CD = 33,
+        Avx512CD_VL = 34,
+        Avx512DQ = 35,
+        Avx512DQ_VL = 36,
+        Avx512Vbmi = 37,
+        Avx512Vbmi_VL = 38,
+        VectorT128 = 39,
+        VectorT256 = 40,
+        VectorT512 = 41,
+        Rcpc2 = 42,
+        Sve = 43,
+        Avx10v1 = 44,
+        Avx10v1_V512 = 46,
+        Evex = 47,
+        Apx = 48,
+        Pclmulqdq_V256 = 49,
+        Pclmulqdq_V512 = 50,
+        Avx10v2 = 51,
+        Avx10v2_V512 = 52,
+        Gfni = 53,
+        Gfni_V256 = 54,
+        Gfni_V512 = 55,
+        RiscV64Base = 56,
+        Zba = 57,
+        Zbb = 58,
+        Sve2 = 59,
+        AvxVnniInt8 = 60,
+        AvxVnniInt8_V512 = 61,
+        AvxVnniInt16 = 62,
+        AvxVnniInt16_V512 = 63,
+        Aes_V256 = 64,
+        Aes_V512 = 65,
+        AvxIfma = 66,
+        F16C = 67,
+        Sha = 68,
+        WaitPkg = 69,
+        Avx512Bitalg = 70,
+        Avx512Bitalg_VL = 71,
+        Avx512Bf16 = 72,
+        Avx512Bf16_VL = 73,
+        Avx512Fp16 = 74,
+        Avx512Fp16_VL = 75,
+        Avx512Ifma = 76,
+        Avx512Vbmi2 = 77,
+        Avx512Vbmi2_VL = 78,
+        Avx512Vnni = 79,
+        Avx512Vp2intersect = 80,
+        Avx512Vp2intersect_VL = 81,
+        Avx512Vpopcntdq = 82,
+        Avx512Vpopcntdq_VL = 83,
+        Zbs = 84,
+        Avx512Bmm = 85,
+        Sha3 = 86,
+        Sm4 = 87,
+        SveAes = 88,
+        SveSha3 = 89,
+        SveSm4 = 90,
     }
 }