Make a library for user space Physical Counter Access.

This commit exposes a common API to interact with physical counters
on arm and x86.

The x86 logic was introduced to improve the performance of the timer driver
see commit #645402620af9bf9a6bf4ef3bd17d5a1077a567b7 on x86.

Using these counters provides significant performance benefits in contrast to
interacting with an external timer driver. At the bare minimum this change will
save thousands of cycles for applications that simply need to track time progression
rather than reading a timestamp and or setting time outs, for the reasons discussed
in #645402620af9bf9a6bf4ef3bd17d5a1077a567b7 as well as avoiding the overhead of invoking
the kernel un-necessarily.

Putting this code in a library like this means that applications that are not worried about
architecture specific details can interact with the generic read_counter and read_freq
functions, avoiding the need for #if defined checks. In addition, applications do not need
to repeat the non trivial boiler plate logic on x86 that is required to calculate the tsc frequency.

Furthermore for x86 in future if we want to calculate the tsc freq when it is otherwise not
available, having a stable API now will avoid having to change more files later.

For RISC-V the frequency must be supplied by the user of the library by patching a valid
config struct into the elfs that use the library. Failure to do this will likely fault but to
ensure this error is caught we check for magic bytes.

Signed-off-by: Callum <c.berry@student.unsw.edu.au>

Author: cazb2

drivers/timer/tsc_hpet/timer.c

@@ -5,6 +5,7 @@
 
 #include <stdint.h>
 #include <microkit.h>
+#include <sddf/util/arch_counter.h>
 #include <sddf/util/printf.h>
 #include <sddf/resources/device.h>
 #include <sddf/timer/protocol.h>
@@ -14,35 +15,10 @@
 
 /* Documents referenced:
  * 1. IA-PC HPET (High Precision Event Timers) Specification
- * 2. Intel® 64 and IA-32 Architectures Software Developer’s Manual
- *    Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4
- *    Order Number: 325462-080US June 2023
- * 3. Linux v6.17 source: native_calibrate_tsc() arch/x86/kernel/tsc.c
  */
 
 __attribute__((__section__(".device_resources"), retain, used)) device_resources_t device_resources;
 
-/* CPUID related definitions for TSC detection. */
-
-/* [2] "Vendor Identification String" page "3-240 Vol. 2A" */
-#define CPUID_VENDOR_ID_LEAF 0x0
-#define CPUID_VENDOR_ID_INTEL_EBX 0x756e6547 // "Genu"
-#define CPUID_VENDOR_ID_INTEL_ECX 0x6c65746e // "ineI"
-#define CPUID_VENDOR_ID_INTEL_EDX 0x49656e69 // "ntel"
-
-/* [2] "Time Stamp Counter and Nominal Core Crystal Clock Information Leaf" page "Vol. 2A 3-231" */
-#define CPUID_TSC_LEAF 0x15
-
-/* [2] "Processor Frequency Information Leaf" page "3-232 Vol. 2A" */
-#define CPUID_PROC_FREQ_LEAF 0x16
-
-/* [2] "Maximum Input Value for Extended Function CPUID Information." page "Vol. 2A 3-245" */
-#define CPUID_MAX_EXT_LEAF 0x80000000
-
-/* [2] "Invariant TSC available if 1" page "Vol. 2A 3-239" */
-#define CPUID_INVARIANT_TSC_LEAF 0x80000007
-#define CPUID_INVARIANT_TSC_EDX_BIT 8
-
 /* hpet data structures / memory maps
  * each timer has its own configuration registers:
  *   - Timer n Configuration and Capability Register
@@ -171,83 +147,6 @@ static void process_timeouts(uint64_t curr_ticks)
     }
 }
 
-static bool is_intel_cpu(void)
-{
-    uint32_t a, b, c, d;
-    cpuid(CPUID_VENDOR_ID_LEAF, 0, &a, &b, &c, &d);
-    return b == CPUID_VENDOR_ID_INTEL_EBX && d == CPUID_VENDOR_ID_INTEL_EDX && c == CPUID_VENDOR_ID_INTEL_ECX;
-}
-
-static bool is_invariant_tsc(void)
-{
-    /* [2] page "Vol. 2A 3-245" */
-    /* Check "Maximum Input Value for Extended Function CPUID Information." */
-    uint32_t max_ext_leaf, a, b, c, d;
-    cpuid(CPUID_MAX_EXT_LEAF, 0, &max_ext_leaf, &b, &c, &d);
-
-    if (max_ext_leaf < CPUID_INVARIANT_TSC_LEAF) {
-        return false;
-    }
-
-    /* Then check whether Invariant TSC is true */
-    uint32_t invariant_tsc;
-    cpuid(CPUID_INVARIANT_TSC_LEAF, 0, &a, &b, &c, &invariant_tsc);
-    return !!(invariant_tsc & BIT(CPUID_INVARIANT_TSC_EDX_BIT));
-}
-
-static uint64_t get_tsc_frequency(void)
-{
-    uint32_t max_basic_leaf, b, c, d;
-    /* Checks whether the CPU expose TSC/Crystal ratio and Crystal frequency via cpuid leaf 0x15. */
-    cpuid(CPUID_VENDOR_ID_LEAF, 0, &max_basic_leaf, &b, &c, &d);
-    if (max_basic_leaf < CPUID_TSC_LEAF) {
-        LOG_TIMER_DRIVER("CPU does not expose TSC leaf.\n");
-        return 0;
-    }
-
-    uint32_t denominator, numerator, crystal_khz;
-    cpuid(CPUID_TSC_LEAF, 0, &denominator, &numerator, &crystal_khz, &d);
-    if (!denominator || !numerator) {
-        LOG_TIMER_DRIVER("TSC/Crystal ratio cannot be calculated.\n");
-        return 0;
-    }
-
-    double tsc_to_crystal_freq_ratio = numerator / (double)denominator;
-
-    uint32_t crystal_hz;
-    if (!crystal_khz) {
-        LOG_TIMER_DRIVER("CPU does not report Crystal frequency, deriving...\n");
-
-        /* From [3]: "Some Intel SoCs like Skylake and Kabylake don't report the crystal
-         * clock, but we can easily calculate it to a high degree of accuracy
-         * by considering the crystal ratio and the CPU speed." */
-        if (max_basic_leaf < CPUID_PROC_FREQ_LEAF) {
-            return 0;
-        }
-
-        uint32_t proc_base_mhz;
-        cpuid(CPUID_PROC_FREQ_LEAF, 0, &proc_base_mhz, &b, &c, &d);
-        uint64_t proc_base_hz = proc_base_mhz * 1000ull * 1000ull;
-        crystal_hz = proc_base_hz * (1 / tsc_to_crystal_freq_ratio);
-
-        LOG_TIMER_DRIVER("Processor base speed is %u MHz\n", proc_base_mhz);
-        LOG_TIMER_DRIVER("Crystal clock is %u Hz\n", crystal_hz);
-    } else {
-        crystal_hz = crystal_khz * 1000;
-    }
-
-    /* From [2]:
-     * EAX: denominator of the TSC/”core crystal clock” ratio.
-     * EBX: numerator of the TSC/”core crystal clock” ratio.
-     * ECX: nominal frequency of the core crystal clock in Hz.
-     * So “TSC frequency” = “core crystal clock frequency” * EBX/EAX.
-     */
-
-    uint64_t tsc_hz = crystal_hz * tsc_to_crystal_freq_ratio;
-    LOG_TIMER_DRIVER("TSC frequency is %u * (%u / %u) = %lu Hz\n", crystal_hz, numerator, denominator, tsc_hz);
-    return tsc_hz;
-}
-
 static uint64_t tsc_ticks_to_ns(uint64_t tsc)
 {
     return ticks_to_ns(tsc, tsc_freq);
@@ -317,7 +216,7 @@ void init(void)
              * TSC took 0.601s, HPET took 12.263s!
              */
         } else {
-            tsc_freq = get_tsc_frequency();
+            tsc_freq = read_freq();
             if (!tsc_freq) {
                 LOG_TIMER_DRIVER_ERR("cannot detect TSC frequency via cpuid, expect performance degradation.\n");
                 /* Because same reason as above. */
@@ -336,7 +235,7 @@ seL4_MessageInfo_t protected(microkit_channel ch, microkit_msginfo msginfo)
 
     case SDDF_TIMER_GET_TIME: {
         if (tsc_freq) {
-            microkit_mr_set(0, tsc_ticks_to_ns(rdtsc()));
+            microkit_mr_set(0, tsc_ticks_to_ns(read_counter()));
         } else {
             microkit_mr_set(0, hpet_ticks_to_ns(get_hpet_ticks()));
         }

include/sddf/util/arch_counter.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright 2022, UNSW
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <microkit.h>
+
+#if defined(CONFIG_ARCH_X86)
+bool is_intel_cpu(void);
+/* On intel x86 if the TSC is not invariant then if the processor is put into sleep states or is overclocked then the
+ * result of reading it may be invalid.
+ */
+bool is_invariant_tsc(void);
+#endif //x86 specific helper functions
+
+/*
+ * Return the current architecture counter value.
+ *
+ * Each implementation aims to use the required serialisation instructions to ensure
+ * an accurate counter read is returned. The ARM barriers try to reflect the x86 synchronisation
+ * and the risc-v is the mapping of the ARM barriers from https://docs.riscv.org/reference/isa/unpriv/mm-eplan.html#armmappings
+ */
+uint64_t read_counter(void);
+/* This may return 0 if frequency was not available */
+uint64_t read_freq(void);
+
+#if defined(CONFIG_ARCH_RISCV)
+#define COUNTER_UTIL_MAGIC_LEN 5
+static char COUNTER_UTIL_MAGIC[COUNTER_UTIL_MAGIC_LEN] = { 's', 'D', 'D', 'F', 0x4 };
+typedef struct arch_counter_config {
+    char magic[COUNTER_UTIL_MAGIC_LEN];
+    uint64_t frequency;
+} arch_counter_config_t;
+#endif

tools/make/board/qemu_virt_riscv64.mk

@@ -3,6 +3,7 @@
 #
 # SPDX-License-Identifier: BSD-2-Clause
 #
+PLATFORM ?= riscv
 BLK_DRIV_DIR ?= virtio/mmio
 GPU_DRIV_DIR ?= virtio
 NET_DRIV_DIR ?= virtio/mmio