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1. tpu-accelerator-lite tpu-accelerator-lite Public

   This is my senior project, we aim to design a Low-cost-AI-Accelerator based on Google's Tensor Processing Unit.

   Verilog 21 1

2. Pipelined-RV32-SoC Pipelined-RV32-SoC Public

   32-bit Pipelined RISC-V CPU Based on RV32I & RV32M including Forwarding, Hazard, Flush, Brach Predictor and two L1 Cache to transmiss data with BRAM using the AXI bus.

   Verilog 15 4

3. DSP-In-VLSI DSP-In-VLSI Public

   Implements DSP-IPs including QRD, FFT, Filters, CORDIC, Interpolator, and Sorter in TSMC 16nm

   SystemVerilog 1

4. Eigen-Value-Decomposition Eigen-Value-Decomposition Public

   Eigen-Value-Decomposition by Iterative QR Algorithm IP for ICDA 5003 Final Project

   Jupyter Notebook