MicroProcessador-RISCV/work-obj93.cf at main · YujiKamiji/MicroProcessador-RISCV · GitHub

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v 4
file . "Memoria/RAM_128_19bits.vhd" "d63dfb3be20e0d857a1edaccd2b87a522f75c4b0" "20250625160207.203":
  entity ram at 1( 0) + 0 on 83;
  architecture a_ram of ram at 15( 305) + 0 on 84;
file . "Processador_tb.vhd" "b529effc18e87f663bf654c719d97c9e72608470" "20250625201338.544":
  entity processador_tb at 1( 0) + 0 on 195;
  architecture sim of processador_tb at 8( 108) + 0 on 196;
file . "UC/UC.vhd" "41e33408f7602fc770b2f99c5ee5ec20cf9798d4" "20250625201338.487":
  entity uc at 1( 0) + 0 on 191;
  architecture arch of uc at 30( 817) + 0 on 192;
file . "PC/somador_pc.vhd" "6679ad5681bcd98f9a33a2a9e448789869120a66" "20250625201338.436":
  entity somador_pc at 1( 0) + 0 on 187;
  architecture arch of somador_pc at 13( 238) + 0 on 188;
file . "Banc_ULA/Banc_ULA.vhd" "94dc01ac0cbd5092278fdd1774c037a7c939a4ae" "20250625201338.330":
  entity banc_ula at 1( 0) + 0 on 181;
  architecture arch of banc_ula at 28( 921) + 0 on 182;
file . "Banc_ULA/DeMuxes/Mux_9x1.vhd" "f016a6153ad441ecb7c148a7d44c79b462a8c312" "20250625201338.277":
  entity mux_9x1 at 1( 0) + 0 on 177;
  architecture arch of mux_9x1 at 13( 275) + 0 on 178;
file . "Banc_ULA/DeMuxes/Mux_3x1.vhd" "00c0908ca5dc52057dbabddd4ca5266a691dbb2a" "20250625201338.230":
  entity mux_3x1 at 1( 0) + 0 on 173;
  architecture arch of mux_3x1 at 13( 259) + 0 on 174;
file . "Banc_ULA/DeMuxes/Demux_1x9.vhd" "1272597a478c2afbbcc65e06a09e122f8ac93f2b" "20250625201338.171":
  entity demux_1x9 at 1( 0) + 0 on 169;
  architecture arch of demux_1x9 at 13( 237) + 0 on 170;
file . "Banc_ULA/registrador/reg_19b.vhd" "04de6c4ba465f80875b372ae597b611d6a7c478b" "20250625201338.117":
  entity reg_19b at 1( 0) + 0 on 165;
  architecture arch of reg_19b at 15( 292) + 0 on 166;
file . "Banc_ULA/registrador/flip_flop.vhd" "2bae282a3c40b2f3c67f2d74b7b330080b48f8e7" "20250625201338.063":
  entity flip_flop at 1( 0) + 0 on 161;
  architecture arch of flip_flop at 15( 269) + 0 on 162;
file . "Banc_ULA/registrador/reg_16b.vhd" "7ba24bf82cc1b67d9cdd51e904c922da1972de3f" "20250625201338.091":
  entity reg_16b at 1( 0) + 0 on 163;
  architecture arch of reg_16b at 15( 292) + 0 on 164;
file . "Banc_ULA/banc_reg/banc_reg_16b.vhd" "287a84f3f227de37ab5495a043d66325dbd7599a" "20250625201338.145":
  entity banc_reg_16b at 1( 0) + 0 on 167;
  architecture arch of banc_reg_16b at 16( 347) + 0 on 168;
file . "Banc_ULA/DeMuxes/Mux_2x1.vhd" "60e9958a4531a8f34731e871a0d2aff2bdb186a8" "20250625201338.198":
  entity mux_2x1 at 1( 0) + 0 on 171;
  architecture arch of mux_2x1 at 13( 243) + 0 on 172;
file . "Banc_ULA/DeMuxes/Mux_4x1.vhd" "ec7d28d277d7200c4daf6216df8c98c65536ff93" "20250625201338.253":
  entity mux_4x1 at 1( 0) + 0 on 175;
  architecture arch of mux_4x1 at 13( 264) + 0 on 176;
file . "Banc_ULA/ULA/ULA.vhd" "095a8d815454b25064664fcfbdbec2f8a25859af" "20250625201338.302":
  entity ula at 1( 0) + 0 on 179;
  architecture arch of ula at 20( 504) + 0 on 180;
file . "FSM/fsm_estado.vhd" "799854f4616c3d4114b737b8c85ec1230e616258" "20250625201338.355":
  entity fsm_estado at 1( 0) + 0 on 183;
  architecture behavior of fsm_estado at 13( 230) + 0 on 184;
file . "PC/pc.vhd" "8d4fdf9724d5ab3fccd6da4151251cb96fc697af" "20250625201338.461":
  entity pc at 1( 0) + 0 on 189;
  architecture arch of pc at 17( 398) + 0 on 190;
file . "Processador.vhd" "fa8d2ae9a77527e9ce679c7c1b46cb8960a0fc50" "20250625201338.517":
  entity processador at 1( 0) + 0 on 193;
  architecture arch of processador at 12( 183) + 0 on 194;
file . "Memoria/ROM_128_12bits.vhd" "cda5d47ad173e036be54d8a8eb3f60988a19f9de" "20250626190934.953":
  entity rom at 1( 0) + 0 on 199;
  architecture a_rom of rom at 13( 292) + 0 on 200;