[MVAU] Update weight file generation and fix double pumping path

Author: auphelia

finn-rtllib/fetch_weights/fetch_weights.sv

@@ -214,7 +214,12 @@ module fetch_weights #(
 		);
 
 		assign	dma_addr = l_offsets[q_idx_dat];
-		assign	dma_len  = ((MH*MW*WEIGHT_WIDTH+7)/8) & ~7;
+		// Same byte-aligned per-IWSIMD-group packing as the tiled path (see above):
+		// each of the MH*MW/IWSIMD groups occupies roundup(IWSIMD*WEIGHT_WIDTH, 8)
+		// bits (= DS_BITS_BA) in external memory. Using tight bit-packing here would
+		// under-fetch whenever IWSIMD*WEIGHT_WIDTH is not byte-aligned (e.g. SIMD=1,
+		// sub-byte weights). Reduces to the tight value when it is byte-aligned.
+		assign	dma_len  = (((MH*MW/IWSIMD) * ((IWSIMD*WEIGHT_WIDTH+7)/8)) + 7) & ~7;
 
 	end : genDirect
 

src/finn/custom_op/fpgadataflow/matrixvectoractivation.py

@@ -746,15 +746,28 @@ def make_weight_file(self, weights, weight_file_mode, weight_file_name):
                 # AXI-MM / fetch_weights path (MLO and external_mem): external memory
                 # (DDR, HBM, ...) holds one IWSIMD group per DWC output beat, each
                 # byte-aligned to DS_BITS_BA = roundup(IWSIMD*bitwidth, 8) bits. IWSIMD
-                # is (PE*SIMD)/TH for TH>1, SIMD otherwise. The within-group ordering
-                # must match the memstreamer (PE-flipped, TH sub-tile order undone):
-                # unflipped would swap PE lanes when IWSIMD*bitwidth <= 8 packs several
-                # PEs into one byte. For TH>1 weight_tensor_pe_flipped is already in
-                # IWSIMD-sized chunks (tinner == (PE*SIMD)/TH == IWSIMD).
+                # is (PE*SIMD)/TH for TH>1, SIMD otherwise.
+                #
+                # The within-group ordering depends on how fetch_weights delivers the
+                # stream to the MVU:
+                #   - TH>1 (tiled MVAU): the stream passes straight through to the tiled
+                #     MVU, which expects the PE-flipped, TH-sub-tile-undone ordering.
+                #     weight_tensor_pe_flipped is already in IWSIMD-sized chunks
+                #     (tinner == (PE*SIMD)/TH == IWSIMD).
+                #   - TH=1 (standard MVAU): the stream goes through local_weight_buffer,
+                #     which distributes consecutive SIMD groups across PE lanes 0..PE-1
+                #     (pe-minor) and pairs weight SIMD lane s with activation SIMD lane s.
+                #     That reconstruction needs the natural (unflipped) PE/SIMD order:
+                #     PE-flipping reverses the PE lanes and SIMD-flipping scrambles the
+                #     dot product.
                 th = self.get_nodeattr("TH")
                 iwsimd = (pe * simd) // th if th > 1 else simd
                 iwsimd_group_bits = roundup_to_integer_multiple(iwsimd * export_wdt.bitwidth(), 8)
-                weight_tensor_iwsimd_groups = weight_tensor_pe_flipped.reshape(1, -1, iwsimd)
+                if th > 1:
+                    weight_tensor_iwsimd = weight_tensor_pe_flipped
+                else:
+                    weight_tensor_iwsimd = weight_tensor_unflipped.reshape(1, -1, pe * simd).copy()
+                weight_tensor_iwsimd_groups = weight_tensor_iwsimd.reshape(1, -1, iwsimd)
                 weight_tensor_iwsimd_groups = pack_innermost_dim_as_hex_string(
                     weight_tensor_iwsimd_groups, export_wdt, iwsimd_group_bits, prefix=""
                 )

src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py

@@ -241,16 +241,12 @@ def instantiate_ip(self, cmd):
                     node_name,
                 )
             )
-            # if using 2x pumped compute, connect the MVU's 2x clk input
-            # to the 2x clock port. Otherwise connect 2x clk to regular clk port
+            # For 2x pumped compute the MVU's 2x clk input is driven by the external
+            # 2x clock port, which CreateStitchedIP exposes and connects for this
+            # (flat) cell - nothing to connect here. Otherwise drive the unused 2x
+            # clk input from the regular clock.
             clk_name = self.get_verilog_top_module_intf_names()["clk"][0]
-            if self.get_nodeattr("pumpedCompute"):
-                clk2x_name = self.get_verilog_top_module_intf_names()["clk2x"][0]
-                cmd.append(
-                    "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/%s]"
-                    % (node_name, clk2x_name, node_name, clk2x_name)
-                )
-            else:
+            if not self.get_nodeattr("pumpedCompute"):
                 cmd.append(
                     "connect_bd_net [get_bd_pins %s/%s] [get_bd_pins %s/ap_clk2x]"
                     % (node_name, clk_name, node_name)

tests/fpgadataflow/test_fpgadataflow_mvau.py

@@ -777,6 +777,10 @@ def test_mvau_fifocharacterize_rtlsim(
         (9, 8, 9, "external_mem"),  # TH=9 high tiling, CHAINLEN=3
         (9, 16, 3, "external_mem"),  # CHAINLEN=6
         (18, 32, 3, "internal_decoupled"),  # max fold, CHAINLEN=11, decoupled
+        # external_mem + TH=1: standard MVAU fed by fetch_weights from external memory
+        # (PE>1 catches PE-lane swaps, SIMD=1 covers the sub-word byte-packing edge).
+        (9, 16, 1, "external_mem"),
+        (18, 1, 1, "external_mem"),
     ],
 )
 @pytest.mark.parametrize(
@@ -808,6 +812,10 @@ def test_fpgadataflow_rtl_mvau(
     if simd == 1 and pumpedCompute:
         pytest.skip("""Clock pumping an input of SIMD=1 is not meaningful. Skipping test""")
 
+    # External memory has no on-chip weight memory to clock-pump.
+    if mem_mode == "external_mem" and pumpedMemory:
+        pytest.skip("External memory has no on-chip weight memory to clock-pump")
+
     # Tiled MVAU (TH>1) requires DSP58 (Versal) and is not combined with clock pumping.
     # The (PE * SIMD) % TH == 0 constraint is guaranteed by the parameter tuples above.
     if th > 1: