When parsing a $var directive that both contains a square bracket as part of the identifier AND a bit index declared afterwards, pyvcd will fail to process it properly and raise vcd.reader.VCDParseError: [lineno]:[col]: Expected $end. This can occur in VCDs generated for constructs like reg [31:0] regs [31:0] that are an array of vectors, where the resulting VCD would have the declaration $var wire 32 Q! regs[0] [31:0] $end (I had this occur in a file generated by Verilator).
I had difficulty finding the official IEEE Verilog standard's definition of what an "identifier" is, but it seems to me that in the above example, regs[0] would be considered part of the identifier, and [31:0] would be considered the bit index. If you (the maintainers) think this interpretation is correct, then I already have a fix + test case that does this, which I can file a PR for.
(screenshot of the relevant portion of the spec that I could find):
When parsing a
$vardirective that both contains a square bracket as part of the identifier AND a bit index declared afterwards, pyvcd will fail to process it properly and raisevcd.reader.VCDParseError: [lineno]:[col]: Expected $end. This can occur in VCDs generated for constructs likereg [31:0] regs [31:0]that are an array of vectors, where the resulting VCD would have the declaration$var wire 32 Q! regs[0] [31:0] $end(I had this occur in a file generated by Verilator).I had difficulty finding the official IEEE Verilog standard's definition of what an "identifier" is, but it seems to me that in the above example,
regs[0]would be considered part of the identifier, and[31:0]would be considered the bit index. If you (the maintainers) think this interpretation is correct, then I already have a fix + test case that does this, which I can file a PR for.(screenshot of the relevant portion of the spec that I could find):
