Is there an existing issue for this?
Current Behavior
The code file patina_dxe_core\src\cpu\cpu_arch_protocol.rs is publishing an EFI_CPU_ARCH_PROTOCOL that has a field called DmaBufferAlignment to provide the size, in bytes, of the alignment required for DMA buffer allocations. It should be a non-zero number that is the largest cache line size.
Expected Behavior
This value should be the largest cache line size of any cache in the system per the UEFI PI spec, version 1.9, section II-12.3.1.
Steps To Reproduce
A platform using the CIX chipset and an NVME drive will not detect the NVME device at boot.
Build Environment
- OS(s): N/A
- Targets Impacted: AARCH64 platforms if they don't support cache-coherent DMA. X86 CPUs have hardware cache-coherent DMA through PCIe root complex snooping.
Version Information
Urgency
High
Are you going to fix this?
I will fix it
Do you need maintainer feedback?
Maintainer feedback requested
Anything else?
No response
Is there an existing issue for this?
Current Behavior
The code file patina_dxe_core\src\cpu\cpu_arch_protocol.rs is publishing an EFI_CPU_ARCH_PROTOCOL that has a field called DmaBufferAlignment to provide the size, in bytes, of the alignment required for DMA buffer allocations. It should be a non-zero number that is the largest cache line size.
Expected Behavior
This value should be the largest cache line size of any cache in the system per the UEFI PI spec, version 1.9, section II-12.3.1.
Steps To Reproduce
A platform using the CIX chipset and an NVME drive will not detect the NVME device at boot.
Build Environment
Version Information
Urgency
High
Are you going to fix this?
I will fix it
Do you need maintainer feedback?
Maintainer feedback requested
Anything else?
No response