From 9ec656d57fb89d92b435dba8abc505c8e29fb2c7 Mon Sep 17 00:00:00 2001 From: Lukasz Kutyla Date: Sat, 21 Feb 2026 19:16:55 +0100 Subject: [PATCH 1/4] soc/intel/*: Add CFR support for Kconfig DISABLE_HECI1_AT_PRE_BOOT Kconfig DISABLE_HECI1_AT_PRE_BOOT is a compile-time only option. This commit adds support for a run-time configurable CFR, where Kconfig DISABLE_HECI1_AT_PRE_BOOT is used as a default value, and updates SoC code to use this new CFR instead of Kconfig. Signed-off-by: Lukasz Kutyla --- src/soc/intel/alderlake/finalize.c | 3 ++- src/soc/intel/apollolake/cse.c | 3 ++- src/soc/intel/cannonlake/finalize.c | 3 ++- src/soc/intel/cannonlake/smihandler.c | 4 +++- src/soc/intel/common/block/cse/cse.c | 3 ++- .../intel/common/block/include/intelblocks/cfr.h | 15 +++++++++++++++ src/soc/intel/elkhartlake/finalize.c | 3 ++- src/soc/intel/elkhartlake/smihandler.c | 3 ++- src/soc/intel/jasperlake/smihandler.c | 3 ++- src/soc/intel/meteorlake/finalize.c | 3 ++- src/soc/intel/pantherlake/finalize.c | 3 ++- src/soc/intel/skylake/chip.c | 2 +- src/soc/intel/skylake/finalize.c | 3 ++- src/soc/intel/tigerlake/finalize.c | 3 ++- 14 files changed, 41 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index 700fde977b3..404fb9779cf 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -76,7 +77,7 @@ static void tbt_finalize(void) static void heci_finalize(void) { heci_set_to_d0i3(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT))) heci1_disable(); } diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index e82b468436a..68803c14c03 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -218,7 +219,7 @@ void heci_cse_lockdown(void) * It is safe to disable HECI1 now since we won't be talking to the ME * anymore. */ - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT))) heci1_disable(); } diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 974794bd977..d50b4558a34 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -88,7 +89,7 @@ static void soc_finalize(void *unused) pch_finalize(); apm_control(APM_CNT_FINALIZE); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && + if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC)) heci1_disable(); diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index ac259908213..955095b2936 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -16,7 +17,8 @@ */ void smihandler_soc_at_finalize(void) { - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM)) + if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) && + CONFIG(HECI_DISABLE_USING_SMM)) heci1_disable(); } diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d02bb85b37f..bbe2f68b7eb 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1430,7 +1430,8 @@ static void cse_final_ready_to_boot(void) { cse_control_global_reset_lock(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) || cse_is_hfs1_com_soft_temp_disable()) { + if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) || + cse_is_hfs1_com_soft_temp_disable()) { cse_set_to_d0i3(); heci1_disable(); } diff --git a/src/soc/intel/common/block/include/intelblocks/cfr.h b/src/soc/intel/common/block/include/intelblocks/cfr.h index 7828e1f3597..4e174591aa6 100644 --- a/src/soc/intel/common/block/include/intelblocks/cfr.h +++ b/src/soc/intel/common/block/include/intelblocks/cfr.h @@ -31,6 +31,21 @@ static const struct sm_object me_state_counter = SM_DECLARE_NUMBER({ .default_value = 0, }); +/* Intel ME HECI1(CSE) device */ +static const struct sm_object me_heci1 = SM_DECLARE_ENUM({ + .opt_name = "me_heci1", + .ui_name = "Intel ME HECI1(CSE) device", + .ui_helptext = "Allows to disable HECI1(CSE) device at the end of" + " boot. Disabling this hides the device from the OS," + " preventing communication with the Intel Management" + " Engine, but it does not disable ME.", + .default_value = !CONFIG(DISABLE_HECI1_AT_PRE_BOOT), + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + /* * Power state after power loss * Use this option or the one below, but not both diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index 275413b4efa..af2fafdbfa5 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -34,7 +35,7 @@ static void pch_finalize(void) static void heci_finalize(void) { heci_set_to_d0i3(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT))) heci1_disable(); } diff --git a/src/soc/intel/elkhartlake/smihandler.c b/src/soc/intel/elkhartlake/smihandler.c index eb5a57642f1..c3139d6937c 100644 --- a/src/soc/intel/elkhartlake/smihandler.c +++ b/src/soc/intel/elkhartlake/smihandler.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -16,7 +17,7 @@ */ void smihandler_soc_at_finalize(void) { - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT))) heci1_disable(); } diff --git a/src/soc/intel/jasperlake/smihandler.c b/src/soc/intel/jasperlake/smihandler.c index f2294fe05de..06d77d06cb5 100644 --- a/src/soc/intel/jasperlake/smihandler.c +++ b/src/soc/intel/jasperlake/smihandler.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -16,7 +17,7 @@ */ void smihandler_soc_at_finalize(void) { - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT))) heci1_disable(); } diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c index 1fd1d98fb5f..034cf02546b 100644 --- a/src/soc/intel/meteorlake/finalize.c +++ b/src/soc/intel/meteorlake/finalize.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -55,7 +56,7 @@ static void sa_finalize(void) static void heci_finalize(void) { heci_set_to_d0i3(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT))) heci1_disable(); } diff --git a/src/soc/intel/pantherlake/finalize.c b/src/soc/intel/pantherlake/finalize.c index 05ec3eaaca9..a8e3e3b91a0 100644 --- a/src/soc/intel/pantherlake/finalize.c +++ b/src/soc/intel/pantherlake/finalize.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -54,7 +55,7 @@ static void sa_finalize(void) static void heci_finalize(void) { heci_set_to_d0i3(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT))) heci1_disable(); } diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 0061c10ae81..47d81472def 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -394,7 +394,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) * setting, we set the appropriate PsfUnlock policy in FSP, * do the changes and then lock it back in coreboot during finalize. */ - tconfig->PchSbAccessUnlock = CONFIG(DISABLE_HECI1_AT_PRE_BOOT); + tconfig->PchSbAccessUnlock = !get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT)); const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; tconfig->PchLockDownBiosInterface = lockdown_by_fsp; diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index fd80aeac1a0..a9c6559e45a 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -60,7 +61,7 @@ static void pch_finalize_script(struct device *dev) pch_thermal_configuration(); /* we should disable Heci1 based on the config */ - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT))) heci1_disable(); /* Hide p2sb device as the OS must not change BAR0. */ diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index cd02745a9e6..2dbacbe64d2 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -57,7 +58,7 @@ static void soc_finalize(void *unused) pch_finalize(); apm_control(APM_CNT_FINALIZE); tbt_finalize(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + if (!get_uint_option("me_heci1", !CONFIG(DISABLE_HECI1_AT_PRE_BOOT))) heci1_disable(); /* Indicate finalize step with post code */ From d5861eb62b2856d4c713937424567a9778e2afea Mon Sep 17 00:00:00 2001 From: Lukasz Kutyla Date: Sat, 21 Feb 2026 19:37:13 +0100 Subject: [PATCH 2/4] mb/google/*: Add CFR option for HECI1 Allow users to enable/disable HECI1 via CFR options menu. Signed-off-by: Lukasz Kutyla --- src/mainboard/google/brox/cfr.c | 1 + src/mainboard/google/brya/cfr.c | 1 + src/mainboard/google/dedede/cfr.c | 1 + src/mainboard/google/drallion/cfr.c | 1 + src/mainboard/google/eve/cfr.c | 1 + src/mainboard/google/fizz/cfr.c | 1 + src/mainboard/google/glados/cfr.c | 1 + src/mainboard/google/hatch/cfr.c | 1 + src/mainboard/google/octopus/cfr.c | 1 + src/mainboard/google/poppy/cfr.c | 1 + src/mainboard/google/puff/cfr.c | 1 + src/mainboard/google/reef/cfr.c | 1 + src/mainboard/google/rex/cfr.c | 1 + src/mainboard/google/sarien/cfr.c | 1 + src/mainboard/google/volteer/cfr.c | 1 + 15 files changed, 15 insertions(+) diff --git a/src/mainboard/google/brox/cfr.c b/src/mainboard/google/brox/cfr.c index 5cd5af0744a..960870a28bf 100644 --- a/src/mainboard/google/brox/cfr.c +++ b/src/mainboard/google/brox/cfr.c @@ -15,6 +15,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/brya/cfr.c b/src/mainboard/google/brya/cfr.c index bbeb0b7d995..4d35f87c962 100644 --- a/src/mainboard/google/brya/cfr.c +++ b/src/mainboard/google/brya/cfr.c @@ -42,6 +42,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/dedede/cfr.c b/src/mainboard/google/dedede/cfr.c index aa52d96c8a5..cd037067dd0 100644 --- a/src/mainboard/google/dedede/cfr.c +++ b/src/mainboard/google/dedede/cfr.c @@ -38,6 +38,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/drallion/cfr.c b/src/mainboard/google/drallion/cfr.c index c23c8ad87d6..5c1394270d1 100644 --- a/src/mainboard/google/drallion/cfr.c +++ b/src/mainboard/google/drallion/cfr.c @@ -21,6 +21,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/eve/cfr.c b/src/mainboard/google/eve/cfr.c index e15eb30aeea..be978ae9478 100644 --- a/src/mainboard/google/eve/cfr.c +++ b/src/mainboard/google/eve/cfr.c @@ -15,6 +15,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/fizz/cfr.c b/src/mainboard/google/fizz/cfr.c index 8a857845068..f73e71d2609 100644 --- a/src/mainboard/google/fizz/cfr.c +++ b/src/mainboard/google/fizz/cfr.c @@ -21,6 +21,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/glados/cfr.c b/src/mainboard/google/glados/cfr.c index 5cd5af0744a..960870a28bf 100644 --- a/src/mainboard/google/glados/cfr.c +++ b/src/mainboard/google/glados/cfr.c @@ -15,6 +15,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/hatch/cfr.c b/src/mainboard/google/hatch/cfr.c index 03e8f3dc629..f30487de473 100644 --- a/src/mainboard/google/hatch/cfr.c +++ b/src/mainboard/google/hatch/cfr.c @@ -35,6 +35,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/octopus/cfr.c b/src/mainboard/google/octopus/cfr.c index 65991177a9d..494e807130a 100644 --- a/src/mainboard/google/octopus/cfr.c +++ b/src/mainboard/google/octopus/cfr.c @@ -18,6 +18,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/poppy/cfr.c b/src/mainboard/google/poppy/cfr.c index 89cf5eec522..4956438eec6 100644 --- a/src/mainboard/google/poppy/cfr.c +++ b/src/mainboard/google/poppy/cfr.c @@ -36,6 +36,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/puff/cfr.c b/src/mainboard/google/puff/cfr.c index 94dae7d28fc..f8de5749385 100644 --- a/src/mainboard/google/puff/cfr.c +++ b/src/mainboard/google/puff/cfr.c @@ -16,6 +16,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/reef/cfr.c b/src/mainboard/google/reef/cfr.c index d7405b1e6c5..69ce3e190df 100644 --- a/src/mainboard/google/reef/cfr.c +++ b/src/mainboard/google/reef/cfr.c @@ -18,6 +18,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/rex/cfr.c b/src/mainboard/google/rex/cfr.c index 54acd456066..276f50b8126 100644 --- a/src/mainboard/google/rex/cfr.c +++ b/src/mainboard/google/rex/cfr.c @@ -15,6 +15,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/sarien/cfr.c b/src/mainboard/google/sarien/cfr.c index c23c8ad87d6..5c1394270d1 100644 --- a/src/mainboard/google/sarien/cfr.c +++ b/src/mainboard/google/sarien/cfr.c @@ -21,6 +21,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/volteer/cfr.c b/src/mainboard/google/volteer/cfr.c index d1efe794565..9f3da830fd1 100644 --- a/src/mainboard/google/volteer/cfr.c +++ b/src/mainboard/google/volteer/cfr.c @@ -29,6 +29,7 @@ static struct sm_obj_form system = { &legacy_8254_timer, &me_state, &me_state_counter, + &me_heci1, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, From 2befcce559d9e1100a7250ae0eb95641057a801f Mon Sep 17 00:00:00 2001 From: Lukasz Kutyla Date: Sat, 21 Feb 2026 20:03:49 +0100 Subject: [PATCH 3/4] soc/intel/*: Add CFR support for Kconfig PAVP Kconfig PAVP is a compile-time only option. This commit adds support for a run-time configurable CFR, where Kconfig PAVP is used as a default value, and updates SoC code to use this new CFR instead of Kconfig. Signed-off-by: Lukasz Kutyla --- src/soc/intel/alderlake/fsp_params.c | 2 +- src/soc/intel/apollolake/chip.c | 2 +- src/soc/intel/cannonlake/fsp_params.c | 2 +- .../common/block/include/intelblocks/cfr.h | 20 +++++++++++++++++++ src/soc/intel/jasperlake/fsp_params.c | 2 +- src/soc/intel/meteorlake/fsp_params.c | 2 +- src/soc/intel/pantherlake/fsp_params.c | 2 +- src/soc/intel/skylake/chip.c | 2 +- 8 files changed, 27 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index bd6f1d548a2..917366c9011 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -614,7 +614,7 @@ static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, /* Check if IGD is present and fill Graphics init param accordingly */ s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); - s_cfg->PavpEnable = CONFIG(PAVP); + s_cfg->PavpEnable = !!get_uint_option("me_pavp", CONFIG(PAVP)); } WEAK_DEV_PTR(tcss_usb3_port1); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 943573fff75..cb4703feb47 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -734,7 +734,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); - silconfig->PavpEnable = CONFIG(PAVP); + silconfig->PavpEnable = !!get_uint_option("me_pavp", CONFIG(PAVP)); /* SATA config */ if (is_devfn_enabled(PCH_DEVFN_SATA)) { diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 2e00018f369..488968ac888 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -734,7 +734,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); - s_cfg->PavpEnable = CONFIG(PAVP); + s_cfg->PavpEnable = !!get_uint_option("me_pavp", CONFIG(PAVP)); /* * Prevent FSP from programming write-once subsystem IDs by providing diff --git a/src/soc/intel/common/block/include/intelblocks/cfr.h b/src/soc/intel/common/block/include/intelblocks/cfr.h index 4e174591aa6..3385d241be6 100644 --- a/src/soc/intel/common/block/include/intelblocks/cfr.h +++ b/src/soc/intel/common/block/include/intelblocks/cfr.h @@ -46,6 +46,26 @@ static const struct sm_object me_heci1 = SM_DECLARE_ENUM({ SM_ENUM_VALUE_END }, }); +/* Intel ME PAVP (Protected Audio-Video Path) */ +static const struct sm_object me_pavp = SM_DECLARE_ENUM({ + .opt_name = "me_pavp", + .ui_name = "Intel ME PAVP", + .ui_helptext = "Enable or disable Intel PAVP (Protected Audio-Video" + " Path). This technology is used to enforce digital" + " rights protections on multimedia content. Streaming" + " or other media playback services may require it to" + " be enabled for correct functioning. You might want" + " to disable this if you do not want DRM content, or" + " if you do not trust the security of the Intel" + " Management Engine, which is where this technology" + " is implemented.", + .default_value = CONFIG(PAVP), + .values = (const struct sm_enum_value[]) { + { "Disabled", 0 }, + { "Enabled", 1 }, + SM_ENUM_VALUE_END }, +}); + /* * Power state after power loss * Use this option or the one below, but not both diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index b01610d2fed..ba8e4b882fb 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -64,7 +64,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Check if IGD is present and fill Graphics init param accordingly */ params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); - params->PavpEnable = CONFIG(PAVP); + params->PavpEnable = !!get_uint_option("me_pavp", CONFIG(PAVP)); /* Use coreboot MP PPI services if Kconfig is enabled */ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 61be03ad478..30eaaf8623c 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -379,7 +379,7 @@ static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, /* Check if IGD is present and fill Graphics init param accordingly */ s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(PCI_DEVFN_IGD); s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); - s_cfg->PavpEnable = CONFIG(PAVP); + s_cfg->PavpEnable = !!get_uint_option("me_pavp", CONFIG(PAVP)); } static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index 0133e72c00e..83254dceba4 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -335,7 +335,7 @@ static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, /* Check if IGD is present and fill Graphics init param accordingly */ s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(PCI_DEVFN_IGD); s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); - s_cfg->PavpEnable = CONFIG(PAVP); + s_cfg->PavpEnable = !!get_uint_option("me_pavp", CONFIG(PAVP)); } static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 47d81472def..61394071a77 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -499,7 +499,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); - params->PavpEnable = CONFIG(PAVP); + params->PavpEnable = !!get_uint_option("me_pavp", CONFIG(PAVP)); soc_irq_settings(params); } From 8c3263710caf75b5b7fb4f53f94987a3b26f6a2e Mon Sep 17 00:00:00 2001 From: Lukasz Kutyla Date: Sat, 21 Feb 2026 20:36:46 +0100 Subject: [PATCH 4/4] mb/google/*: Add CFR option for PAVP Allow users to enable/disable PAVP via CFR options menu. Signed-off-by: Lukasz Kutyla --- src/mainboard/google/brox/cfr.c | 1 + src/mainboard/google/brya/cfr.c | 1 + src/mainboard/google/dedede/cfr.c | 1 + src/mainboard/google/drallion/cfr.c | 1 + src/mainboard/google/eve/cfr.c | 1 + src/mainboard/google/fizz/cfr.c | 1 + src/mainboard/google/glados/cfr.c | 1 + src/mainboard/google/hatch/cfr.c | 1 + src/mainboard/google/octopus/cfr.c | 1 + src/mainboard/google/poppy/cfr.c | 1 + src/mainboard/google/puff/cfr.c | 1 + src/mainboard/google/reef/cfr.c | 1 + src/mainboard/google/rex/cfr.c | 1 + src/mainboard/google/sarien/cfr.c | 1 + 14 files changed, 14 insertions(+) diff --git a/src/mainboard/google/brox/cfr.c b/src/mainboard/google/brox/cfr.c index 960870a28bf..7ff60860627 100644 --- a/src/mainboard/google/brox/cfr.c +++ b/src/mainboard/google/brox/cfr.c @@ -16,6 +16,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/brya/cfr.c b/src/mainboard/google/brya/cfr.c index 4d35f87c962..4fd6d38fca9 100644 --- a/src/mainboard/google/brya/cfr.c +++ b/src/mainboard/google/brya/cfr.c @@ -43,6 +43,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/dedede/cfr.c b/src/mainboard/google/dedede/cfr.c index cd037067dd0..cfe3f02de80 100644 --- a/src/mainboard/google/dedede/cfr.c +++ b/src/mainboard/google/dedede/cfr.c @@ -39,6 +39,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/drallion/cfr.c b/src/mainboard/google/drallion/cfr.c index 5c1394270d1..72e8501ce05 100644 --- a/src/mainboard/google/drallion/cfr.c +++ b/src/mainboard/google/drallion/cfr.c @@ -22,6 +22,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/eve/cfr.c b/src/mainboard/google/eve/cfr.c index be978ae9478..4ef10499ce3 100644 --- a/src/mainboard/google/eve/cfr.c +++ b/src/mainboard/google/eve/cfr.c @@ -16,6 +16,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/fizz/cfr.c b/src/mainboard/google/fizz/cfr.c index f73e71d2609..8d98e7ffbd3 100644 --- a/src/mainboard/google/fizz/cfr.c +++ b/src/mainboard/google/fizz/cfr.c @@ -22,6 +22,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/glados/cfr.c b/src/mainboard/google/glados/cfr.c index 960870a28bf..7ff60860627 100644 --- a/src/mainboard/google/glados/cfr.c +++ b/src/mainboard/google/glados/cfr.c @@ -16,6 +16,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/hatch/cfr.c b/src/mainboard/google/hatch/cfr.c index f30487de473..6a7be57bf1d 100644 --- a/src/mainboard/google/hatch/cfr.c +++ b/src/mainboard/google/hatch/cfr.c @@ -36,6 +36,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/octopus/cfr.c b/src/mainboard/google/octopus/cfr.c index 494e807130a..dab332b9554 100644 --- a/src/mainboard/google/octopus/cfr.c +++ b/src/mainboard/google/octopus/cfr.c @@ -19,6 +19,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/poppy/cfr.c b/src/mainboard/google/poppy/cfr.c index 4956438eec6..205f1aa0242 100644 --- a/src/mainboard/google/poppy/cfr.c +++ b/src/mainboard/google/poppy/cfr.c @@ -37,6 +37,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/puff/cfr.c b/src/mainboard/google/puff/cfr.c index f8de5749385..d7e1d8b7034 100644 --- a/src/mainboard/google/puff/cfr.c +++ b/src/mainboard/google/puff/cfr.c @@ -17,6 +17,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/reef/cfr.c b/src/mainboard/google/reef/cfr.c index 69ce3e190df..ed7683f1f43 100644 --- a/src/mainboard/google/reef/cfr.c +++ b/src/mainboard/google/reef/cfr.c @@ -19,6 +19,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/rex/cfr.c b/src/mainboard/google/rex/cfr.c index 276f50b8126..5b44b6b11b5 100644 --- a/src/mainboard/google/rex/cfr.c +++ b/src/mainboard/google/rex/cfr.c @@ -16,6 +16,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss, diff --git a/src/mainboard/google/sarien/cfr.c b/src/mainboard/google/sarien/cfr.c index 5c1394270d1..72e8501ce05 100644 --- a/src/mainboard/google/sarien/cfr.c +++ b/src/mainboard/google/sarien/cfr.c @@ -22,6 +22,7 @@ static struct sm_obj_form system = { &me_state, &me_state_counter, &me_heci1, + &me_pavp, &pciexp_aspm, &pciexp_clk_pm, &pciexp_l1ss,