From f80ddfcc5cd9af9125f4e3d663d5e1834b2fbedf Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 03:18:34 +0000 Subject: [PATCH 01/16] ESP32: Xtensa LX6 cores in the machine framework, and the SoC that boots ESP-IDF Two LX6 cores (core/mcu/xtensa/lx6.c, lx6fp.c) as core-isa.h configures the ESP32: windowed registers, loops, XEA2 exceptions, seven interrupt levels, CCOUNT/CCOMPARE timers, MAC16, booleans, single-precision FPU, region protection, the debug option; backend "xtensa" in build.c. The ESP32 description (catalog/mcus/espressif/esp32): the memory map, the ROM image built from Espressif's esp32_rev300_rom.elf (equal to QEMU's esp32-v3-rom.bin), the register file from esp32.svd, and models for DPORT (APP_CPU control, caches and flash MMU, interrupt matrix, the APP_CPU's own ROM view), RTC_CNTL, eFuse, APB_CTRL clocks, GPIO/IO_MUX with strapping, UART0-2, TIMG0/1, SPI0/1 and the GT25Q32A flash, SHA, the internal analog I2C, RNG and the AHB view. Espressif's ROM, ESP-IDF v5.4's second-stage bootloader and hello_world run unmodified to Hello world! --- catalog/boards/esp32_devkitc/board.json | 25 + .../espressif/esp32/LICENSES/Apache-2.0.txt | 13 + catalog/mcus/espressif/esp32/mcu.json | 310 + catalog/mcus/espressif/esp32/registers.json | 51212 ++++++++++++++++ catalog/mcus/espressif/esp32/rom.bin | Bin 0 -> 458752 bytes catalog/mcus/espressif/esp32/wroom32e.json | 205 + core/mcu/build.c | 4 + core/mcu/esp32/soc/apbctrl.c | 98 + core/mcu/esp32/soc/dport.c | 346 + core/mcu/esp32/soc/efuse.c | 261 + core/mcu/esp32/soc/esp32.h | 105 + core/mcu/esp32/soc/gpio.c | 534 + core/mcu/esp32/soc/misc.c | 93 + core/mcu/esp32/soc/nor.c | 365 + core/mcu/esp32/soc/regi2c.c | 100 + core/mcu/esp32/soc/rtc.c | 398 + core/mcu/esp32/soc/sha.c | 202 + core/mcu/esp32/soc/spi.c | 354 + core/mcu/esp32/soc/timg.c | 434 + core/mcu/esp32/soc/uart.c | 452 + core/mcu/models.c | 11 + core/mcu/rf.c | 9 + core/mcu/rf.h | 2 + core/mcu/xtensa/lx6.c | 2244 + core/mcu/xtensa/lx6.h | 63 + core/mcu/xtensa/lx6fp.c | 418 + tools/importers/esprom.py | 4 +- 27 files changed, 58261 insertions(+), 1 deletion(-) create mode 100644 catalog/boards/esp32_devkitc/board.json create mode 100644 catalog/mcus/espressif/esp32/LICENSES/Apache-2.0.txt create mode 100644 catalog/mcus/espressif/esp32/mcu.json create mode 100644 catalog/mcus/espressif/esp32/registers.json create mode 100644 catalog/mcus/espressif/esp32/rom.bin create mode 100644 catalog/mcus/espressif/esp32/wroom32e.json create mode 100644 core/mcu/esp32/soc/apbctrl.c create mode 100644 core/mcu/esp32/soc/dport.c create mode 100644 core/mcu/esp32/soc/efuse.c create mode 100644 core/mcu/esp32/soc/esp32.h create mode 100644 core/mcu/esp32/soc/gpio.c create mode 100644 core/mcu/esp32/soc/misc.c create mode 100644 core/mcu/esp32/soc/nor.c create mode 100644 core/mcu/esp32/soc/regi2c.c create mode 100644 core/mcu/esp32/soc/rtc.c create mode 100644 core/mcu/esp32/soc/sha.c create mode 100644 core/mcu/esp32/soc/spi.c create mode 100644 core/mcu/esp32/soc/timg.c create mode 100644 core/mcu/esp32/soc/uart.c create mode 100644 core/mcu/xtensa/lx6.c create mode 100644 core/mcu/xtensa/lx6.h create mode 100644 core/mcu/xtensa/lx6fp.c diff --git a/catalog/boards/esp32_devkitc/board.json b/catalog/boards/esp32_devkitc/board.json new file mode 100644 index 000000000..2068109da --- /dev/null +++ b/catalog/boards/esp32_devkitc/board.json @@ -0,0 +1,25 @@ +{ + "schema_version": 1, + "kind": "board", + "id": "emblink/esp32_devkitc", + "version": "0.1.0", + "name": "ESP32-DevKitC V4", + "description": "Espressif's ESP32-DevKitC V4 with an ESP32-WROOM-32E module.", + "keywords": ["esp32", "devkitc", "esp32-wroom-32e", "xtensa", "espressif"], + "revision": "V4", + "mcu": {"ref": "espressif/esp32", "package": "wroom32e", "instance": "U1"}, + "oscillators": {"hse": {"hz": 40000000, "source": "external_crystal"}}, + "components": [], + "nets": { + "3V3": ["U1.VDD3P3"], + "GND": ["U1.GND"], + "EN": ["U1.CHIP_EN"], + "GPIO0": ["U1.GPIO0"], + "GPIO1": ["U1.GPIO1"], + "GPIO3": ["U1.GPIO3"] + }, + "ports": {}, + "console": {"peripheral": "UART0", "tx": "GPIO1", "rx": "GPIO3", "baud": 115200}, + "fidelity": {"functional": {"claims": "Work in progress.", "omissions": [], "validation": []}}, + "provenance": {"author": "EmbSIM", "license": "Apache-2.0", "sources": []} +} diff --git a/catalog/mcus/espressif/esp32/LICENSES/Apache-2.0.txt b/catalog/mcus/espressif/esp32/LICENSES/Apache-2.0.txt new file mode 100644 index 000000000..439f2cf82 --- /dev/null +++ b/catalog/mcus/espressif/esp32/LICENSES/Apache-2.0.txt @@ -0,0 +1,13 @@ +Copyright (c) 2026 Microchip Technology Inc. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. \ No newline at end of file diff --git a/catalog/mcus/espressif/esp32/mcu.json b/catalog/mcus/espressif/esp32/mcu.json new file mode 100644 index 000000000..62e1209d2 --- /dev/null +++ b/catalog/mcus/espressif/esp32/mcu.json @@ -0,0 +1,310 @@ +{ + "schema_version": 1, + "kind": "mcu", + "id": "espressif/esp32", + "version": "0.1.0", + "name": "ESP32", + "description": "Espressif ESP32 (ESP32-D0WD-V3, chip revision v3.1): two Xtensa LX6 cores at up to 240 MHz, 520 KiB of SRAM, 448 KiB of ROM, 16 KiB of RTC memory, external SPI flash behind the cores' caches, Wi-Fi and Bluetooth.", + "keywords": [ + "xtensa", + "lx6", + "espressif", + "esp32", + "esp32-d0wd-v3", + "dual-core" + ], + "vendor": "espressif", + "family": "esp32", + "core": { + "backend": "xtensa", + "model": "esp32-lx6", + "cores": 2, + "timing_tier": "estimated", + "fpu": true, + "mpu": false, + "endian": "little", + "reset_pc": "0x40000400" + }, + "memory": [ + { + "name": "rom", + "base": "0x40000000", + "size": "448K", + "kind": "rom", + "file": "rom.bin", + "doc": "Internal ROM0 (384 KiB) and ROM1 (64 KiB) on the instruction bus (TRM v5 table 3.3-1, ESP-IDF's SOC_IROM_MASK_HIGH 0x40070000): the boot ROM of chip revision v3, its image made by tools/importers/esprom.py (--base 0x40000000 --size 0x70000 --data-table 0x4000D4EC:0x4000D4F8, the Bluetooth controller's entry; --data-table 0x4000D4F8:0x4000D5C8, the ROM's copy table of its RAM variables' initial values) from Espressif's esp32_rev300_rom.elf (espressif/esp-rom-elfs 20241011, Apache-2.0: LICENSES/Apache-2.0.txt; the ROM's code is Copyright (c) 2015-2022 Espressif Systems (Shanghai) Co. Ltd.). It equals byte for byte the image Espressif's QEMU loads (esp32-v3-rom.bin, sha256 9115bbcd...258b) over its 455,722 bytes; the rest reads zeros" + }, + { + "name": "rom1_data", + "base": "0x3FF90000", + "size": "64K", + "kind": "alias", + "target": "0x40060000", + "doc": "Internal ROM1 on the data bus" + }, + { + "name": "sram0", + "base": "0x40070000", + "size": "192K", + "kind": "ram", + "doc": "Internal SRAM0 on the instruction bus: its first 64 KiB the cores' flash caches once they are enabled, the rest IRAM" + }, + { + "name": "sram2", + "base": "0x3FFAE000", + "size": "200K", + "kind": "ram", + "doc": "Internal SRAM2 on the data bus (DRAM)" + }, + { + "name": "sram1", + "base": "0x3FFE0000", + "size": "128K", + "kind": "ram", + "main": true, + "doc": "Internal SRAM1 on the data bus (DRAM), where the ROM keeps its data and stacks" + }, + { + "name": "rtc_fast", + "base": "0x3FF80000", + "size": "8K", + "kind": "ram", + "doc": "RTC FAST memory on the data bus, kept in deep sleep" + }, + { + "name": "rtc_fast_ibus", + "base": "0x400C0000", + "size": "8K", + "kind": "alias", + "target": "0x3FF80000", + "doc": "RTC FAST memory on the instruction bus" + }, + { + "name": "rtc_slow", + "base": "0x50000000", + "size": "8K", + "kind": "ram", + "doc": "RTC SLOW memory, kept in deep sleep, the ULP coprocessor's" + }, + { + "name": "flash", + "base": "0x0", + "size": "4M", + "kind": "external", + "erased": "0xFFFFFFFF", + "doc": "The module's 4 MB SPI flash, reached through SPI0 and SPI1 and read in place through the caches" + }, + { + "name": "flash_drom", + "base": "0x3F400000", + "size": "4M", + "kind": "window", + "doc": "The data bus's window on the flash (DROM0, TRM table 3.3-3): 64 pages of 64 KB that MMU entries 0-63 map" + }, + { + "name": "flash_irom", + "base": "0x400D0000", + "size": "0x330000", + "kind": "window", + "doc": "The instruction bus's window on the flash (IROM0 from the first whole page after RTC FAST memory to 0x403FFFFF): MMU entries 77-127" + } + ], + "clocks": { + "sources": [ + { + "name": "xtal", + "hz": 40000000, + "doc": "The module's 40 MHz crystal (XTL_CLK); the CPU runs from it out of reset" + }, + { + "name": "rc_fast", + "hz": 8000000, + "doc": "The internal 8 MHz RC oscillator (RC_FAST_CLK, 8MD256 its /256)" + }, + { + "name": "rc_slow", + "hz": 150000, + "doc": "The internal 150 kHz RC oscillator (RTC_SLOW_CLK's default)" + }, + { + "name": "pll", + "hz": 320000000, + "doc": "PLL_CLK, 320 MHz (or 480 MHz) from the crystal" + } + ], + "reset_core_hz": 40000000, + "max_core_hz": 240000000 + }, + "register_file": { + "format": "embsim", + "file": "registers.json", + "vendored": true, + "license": "Apache-2.0 (converted from Espressif's esp32.svd, Copyright 2024 Espressif Systems (Shanghai) PTE LTD; LICENSES/Apache-2.0.txt)" + }, + "peripherals": [ + { + "match": "DPORT", + "model": "esp32-dport", + "order": 0 + }, + { + "match": "RTC_CNTL", + "model": "esp32-rtc", + "order": 1 + }, + { + "match": "APB_CTRL", + "model": "esp32-apbctrl", + "order": 1 + }, + { + "match": "EFUSE", + "model": "esp32-efuse" + }, + { + "match": "UART?", + "model": "esp32-uart" + }, + { + "match": "IO_MUX", + "model": "esp32-iomux", + "order": 0 + }, + { + "match": "GPIO", + "model": "esp32-gpio", + "order": 1 + }, + { + "match": "SPI0", + "model": "esp32-spi" + }, + { + "match": "SPI1", + "model": "esp32-spi" + }, + { + "match": "TIMG?", + "model": "esp32-timg" + }, + { + "match": "SHA", + "model": "esp32-sha" + } + ], + "io": { + "family": "cmos_3v3", + "ports": [ + { + "name": "GPIO", + "pins": 40, + "mask": "0xFFFFFFFFFF" + } + ], + "electrical": { + "vdd": 3.3, + "voh": 2.64, + "vol": 0.33, + "rout": 20, + "vih": 2.475, + "vil": 0.825, + "hysteresis": 0.1, + "rpull": 45000, + "leak_a": 5e-08, + "ioh_max": 0.04, + "iol_max": 0.028 + } + }, + "console": { + "default": "UART0" + }, + "fidelity": { + "functional": { + "claims": "Work in progress.", + "omissions": [], + "validation": [] + }, + "timed": { + "claims": "Instruction timing estimated.", + "omissions": [], + "validation": [] + }, + "electrical": { + "claims": "GPIO pin-model defaults at 3.3 V.", + "omissions": [], + "validation": [] + } + }, + "provenance": { + "author": "EmbSIM", + "license": "Apache-2.0", + "sources": [ + { + "title": "ESP32 Technical Reference Manual", + "rev": "v5.2" + }, + { + "title": "ESP32 Series Datasheet", + "rev": "v4.8" + }, + { + "title": "Espressif esp32.svd (espressif/svd)", + "rev": "be20aa1" + }, + { + "title": "Espressif esp-rom-elfs, esp32_rev300_rom.elf", + "rev": "20241011" + } + ], + "notes": "The register description is converted from Espressif's Apache-2.0 SVD; the boot ROM's image from Espressif's Apache-2.0 ROM ELF." + }, + "signals": [ + "GPIO0", + "GPIO1", + "GPIO2", + "GPIO3", + "GPIO4", + "GPIO5", + "GPIO6", + "GPIO7", + "GPIO8", + "GPIO9", + "GPIO10", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "GPIO15", + "GPIO16", + "GPIO17", + "GPIO18", + "GPIO19", + "GPIO21", + "GPIO22", + "GPIO23", + "GPIO25", + "GPIO26", + "GPIO27", + "GPIO32", + "GPIO33", + "GPIO34", + "GPIO35", + "GPIO36", + "GPIO37", + "GPIO38", + "GPIO39", + "CHIP_EN", + "GND", + "LNA_IN", + "VDD3P3", + "VDD3P3_CPU", + "VDD3P3_RTC", + "VDDA", + "VDD_SDIO", + "XTAL_N", + "XTAL_P" + ], + "packages": { + "wroom32e": "wroom32e.json" + } +} \ No newline at end of file diff --git a/catalog/mcus/espressif/esp32/registers.json b/catalog/mcus/espressif/esp32/registers.json new file mode 100644 index 000000000..7287b6ae6 --- /dev/null +++ b/catalog/mcus/espressif/esp32/registers.json @@ -0,0 +1,51212 @@ +{ + "schema_version": 1, + "kind": "registers", + "id": "espressif/esp32/registers", + "version": "1.0.0", + "device": "ESP32", + "source": "converted from esp32.svd by tools/importers/svd2regs.py; peripherals left out: RNG (the random number generator's one register (RNG_DATA, TRM 26), which the SVD puts at the AHB address 0x60035144; the chip's model answers at 0x3FF75144 and its AHB alias (misc.c))", + "interrupts": { + "WIFI_MAC": 0, + "WIFI_NMI": 1, + "WIFI_BB": 2, + "BT_MAC": 3, + "BT_BB": 4, + "BT_BB_NMI": 5, + "RWBT": 6, + "RWBLE": 7, + "RWBT_NMI": 8, + "RWBLE_NMI": 9, + "UHCI0": 12, + "UHCI1": 13, + "TG0_T0_LEVEL": 14, + "TG0_T1_LEVEL": 15, + "TG0_WDT_LEVEL": 16, + "TG0_LACT_LEVEL": 17, + "TG1_T0_LEVEL": 18, + "TG1_T1_LEVEL": 19, + "TG1_WDT_LEVEL": 20, + "TG1_LACT_LEVEL": 21, + "GPIO": 22, + "GPIO_NMI": 23, + "FROM_CPU_INTR0": 24, + "FROM_CPU_INTR1": 25, + "FROM_CPU_INTR2": 26, + "FROM_CPU_INTR3": 27, + "SPI0": 28, + "SPI1": 29, + "SPI2": 30, + "SPI3": 31, + "I2S0": 32, + "I2S1": 33, + "UART0": 34, + "UART1": 35, + "UART2": 36, + "SDIO_HOST": 37, + "ETH_MAC": 38, + "MCPWM0": 39, + "MCPWM1": 40, + "MCPWM2": 41, + "MCPWM3": 42, + "LEDC": 43, + "EFUSE": 44, + "TWAI0": 45, + "RTC_CORE": 46, + "RMT": 47, + "PCNT": 48, + "I2C_EXT0": 49, + "I2C_EXT1": 50, + "RSA": 51, + "SPI1_DMA": 52, + "SPI2_DMA": 53, + "SPI3_DMA": 54, + "WDT": 55, + "TIMER1": 56, + "TIMER2": 57, + "TG0_T0_EDGE": 58, + "TG0_T1_EDGE": 59, + "TG0_WDT_EDGE": 60, + "TG0_LACT_EDGE": 61, + "TG1_T0_EDGE": 62, + "TG1_T1_EDGE": 63, + "TG1_WDT_EDGE": 64, + "TG1_LACT_EDGE": 65, + "MMU_IA": 66, + "MPU_IA": 67, + "CACHE_IA": 68 + }, + "peripherals": [ + { + "name": "DPORT", + "base": "0x3FF00000", + "interrupts": [ + "WIFI_MAC", + "WIFI_NMI", + "WIFI_BB", + "BT_MAC", + "BT_BB", + "BT_BB_NMI", + "RWBT", + "RWBLE", + "RWBT_NMI", + "RWBLE_NMI", + "FROM_CPU_INTR0", + "FROM_CPU_INTR1", + "FROM_CPU_INTR2", + "FROM_CPU_INTR3", + "SDIO_HOST", + "ETH_MAC", + "WDT", + "MMU_IA", + "MPU_IA", + "CACHE_IA" + ], + "registers": [ + { + "name": "PRO_BOOT_REMAP_CTRL", + "offset": "0x00", + "fields": [ + [ + "PRO_BOOT_REMAP", + 0, + 1 + ] + ] + }, + { + "name": "APP_BOOT_REMAP_CTRL", + "offset": "0x04", + "fields": [ + [ + "APP_BOOT_REMAP", + 0, + 1 + ] + ] + }, + { + "name": "ACCESS_CHECK", + "offset": "0x08", + "fields": [ + [ + "PRO", + 0, + 1, + "r" + ], + [ + "APP", + 8, + 1, + "r" + ] + ] + }, + { + "name": "PRO_DPORT_APB_MASK0", + "offset": "0x0C", + "fields": [ + [ + "PRODPORT_APB_MASK0", + 0, + 32 + ] + ] + }, + { + "name": "PRO_DPORT_APB_MASK1", + "offset": "0x10", + "fields": [ + [ + "PRODPORT_APB_MASK1", + 0, + 32 + ] + ] + }, + { + "name": "APP_DPORT_APB_MASK0", + "offset": "0x14", + "fields": [ + [ + "APPDPORT_APB_MASK0", + 0, + 32 + ] + ] + }, + { + "name": "APP_DPORT_APB_MASK1", + "offset": "0x18", + "fields": [ + [ + "APPDPORT_APB_MASK1", + 0, + 32 + ] + ] + }, + { + "name": "PERI_CLK_EN", + "offset": "0x1C", + "fields": [ + [ + "PERI_CLK_EN", + 0, + 32 + ] + ] + }, + { + "name": "PERI_RST_EN", + "offset": "0x20", + "fields": [ + [ + "PERI_RST_EN", + 0, + 32 + ] + ] + }, + { + "name": "WIFI_BB_CFG", + "offset": "0x24", + "fields": [ + [ + "WIFI_BB_CFG", + 0, + 32 + ] + ] + }, + { + "name": "WIFI_BB_CFG_2", + "offset": "0x28", + "fields": [ + [ + "WIFI_BB_CFG_2", + 0, + 32 + ] + ] + }, + { + "name": "APPCPU_CTRL_A", + "offset": "0x2C", + "reset": "0x00000001", + "fields": [ + [ + "APPCPU_RESETTING", + 0, + 1 + ] + ] + }, + { + "name": "APPCPU_CTRL_B", + "offset": "0x30", + "fields": [ + [ + "APPCPU_CLKGATE_EN", + 0, + 1 + ] + ] + }, + { + "name": "APPCPU_CTRL_C", + "offset": "0x34", + "fields": [ + [ + "APPCPU_RUNSTALL", + 0, + 1 + ] + ] + }, + { + "name": "APPCPU_CTRL_D", + "offset": "0x38", + "fields": [ + [ + "APPCPU_BOOT_ADDR", + 0, + 32 + ] + ] + }, + { + "name": "CPU_PER_CONF", + "offset": "0x3C", + "fields": [ + [ + "CPUPERIOD_SEL", + 0, + 2 + ], + [ + "LOWSPEED_CLK_SEL", + 2, + 1 + ], + [ + "FAST_CLK_RTC_SEL", + 3, + 1 + ] + ] + }, + { + "name": "PRO_CACHE_CTRL", + "offset": "0x40", + "reset": "0x00000010", + "fields": [ + [ + "PRO_CACHE_MODE", + 2, + 1 + ], + [ + "PRO_CACHE_ENABLE", + 3, + 1 + ], + [ + "PRO_CACHE_FLUSH_ENA", + 4, + 1 + ], + [ + "PRO_CACHE_FLUSH_DONE", + 5, + 1, + "r" + ], + [ + "PRO_CACHE_LOCK_0_EN", + 6, + 1 + ], + [ + "PRO_CACHE_LOCK_1_EN", + 7, + 1 + ], + [ + "PRO_CACHE_LOCK_2_EN", + 8, + 1 + ], + [ + "PRO_CACHE_LOCK_3_EN", + 9, + 1 + ], + [ + "PRO_SINGLE_IRAM_ENA", + 10, + 1 + ], + [ + "PRO_DRAM_SPLIT", + 11, + 1 + ], + [ + "PRO_AHB_SPI_REQ", + 12, + 1, + "r" + ], + [ + "PRO_SLAVE_REQ", + 13, + 1, + "r" + ], + [ + "AHB_SPI_REQ", + 14, + 1, + "r" + ], + [ + "SLAVE_REQ", + 15, + 1, + "r" + ], + [ + "PRO_DRAM_HL", + 16, + 1 + ] + ] + }, + { + "name": "PRO_CACHE_CTRL1", + "offset": "0x44", + "reset": "0x000008FF", + "fields": [ + [ + "PRO_CACHE_MASK_IRAM0", + 0, + 1 + ], + [ + "PRO_CACHE_MASK_IRAM1", + 1, + 1 + ], + [ + "PRO_CACHE_MASK_IROM0", + 2, + 1 + ], + [ + "PRO_CACHE_MASK_DRAM1", + 3, + 1 + ], + [ + "PRO_CACHE_MASK_DROM0", + 4, + 1 + ], + [ + "PRO_CACHE_MASK_OPSDRAM", + 5, + 1 + ], + [ + "PRO_CMMU_SRAM_PAGE_MODE", + 6, + 3 + ], + [ + "PRO_CMMU_FLASH_PAGE_MODE", + 9, + 2 + ], + [ + "PRO_CMMU_FORCE_ON", + 11, + 1 + ], + [ + "PRO_CMMU_PD", + 12, + 1 + ], + [ + "PRO_CACHE_MMU_IA_CLR", + 13, + 1 + ] + ] + }, + { + "name": "PRO_CACHE_LOCK_0_ADDR", + "offset": "0x48", + "fields": [ + [ + "PRE", + 0, + 14 + ], + [ + "MIN", + 14, + 4 + ], + [ + "MAX", + 18, + 4 + ] + ] + }, + { + "name": "PRO_CACHE_LOCK_1_ADDR", + "offset": "0x4C", + "fields": [ + [ + "PRE", + 0, + 14 + ], + [ + "MIN", + 14, + 4 + ], + [ + "MAX", + 18, + 4 + ] + ] + }, + { + "name": "PRO_CACHE_LOCK_2_ADDR", + "offset": "0x50", + "fields": [ + [ + "PRE", + 0, + 14 + ], + [ + "MIN", + 14, + 4 + ], + [ + "MAX", + 18, + 4 + ] + ] + }, + { + "name": "PRO_CACHE_LOCK_3_ADDR", + "offset": "0x54", + "fields": [ + [ + "PRE", + 0, + 14 + ], + [ + "MIN", + 14, + 4 + ], + [ + "MAX", + 18, + 4 + ] + ] + }, + { + "name": "APP_CACHE_CTRL", + "offset": "0x58", + "reset": "0x00000010", + "fields": [ + [ + "APP_CACHE_MODE", + 2, + 1 + ], + [ + "APP_CACHE_ENABLE", + 3, + 1 + ], + [ + "APP_CACHE_FLUSH_ENA", + 4, + 1 + ], + [ + "APP_CACHE_FLUSH_DONE", + 5, + 1, + "r" + ], + [ + "APP_CACHE_LOCK_0_EN", + 6, + 1 + ], + [ + "APP_CACHE_LOCK_1_EN", + 7, + 1 + ], + [ + "APP_CACHE_LOCK_2_EN", + 8, + 1 + ], + [ + "APP_CACHE_LOCK_3_EN", + 9, + 1 + ], + [ + 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"fields": [ + [ + "PRO_CPU_INTR_FROM_CPU_1_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_CPU_INTR_FROM_CPU_2_MAP", + "offset": "0x16C", + "reset": "0x00000010", + "fields": [ + [ + "PRO_CPU_INTR_FROM_CPU_2_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_CPU_INTR_FROM_CPU_3_MAP", + "offset": "0x170", + "reset": "0x00000010", + "fields": [ + [ + "PRO_CPU_INTR_FROM_CPU_3_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_SPI_INTR_0_MAP", + "offset": "0x174", + "reset": "0x00000010", + "fields": [ + [ + "PRO_SPI_INTR_0_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_SPI_INTR_1_MAP", + "offset": "0x178", + "reset": "0x00000010", + "fields": [ + [ + "PRO_SPI_INTR_1_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_SPI_INTR_2_MAP", + "offset": "0x17C", + "reset": "0x00000010", + "fields": [ + [ + "PRO_SPI_INTR_2_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_SPI_INTR_3_MAP", + "offset": "0x180", + "reset": "0x00000010", + "fields": [ + [ + "PRO_SPI_INTR_3_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_I2S0_INT_MAP", + "offset": "0x184", + "reset": "0x00000010", + "fields": [ + [ + "PRO_I2S0_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_I2S1_INT_MAP", + "offset": "0x188", + "reset": "0x00000010", + "fields": [ + [ + "PRO_I2S1_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_UART_INTR_MAP", + "offset": "0x18C", + "reset": "0x00000010", + "fields": [ + [ + "PRO_UART_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_UART1_INTR_MAP", + "offset": "0x190", + "reset": "0x00000010", + "fields": [ + [ + "PRO_UART1_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_UART2_INTR_MAP", + "offset": "0x194", + "reset": "0x00000010", + "fields": [ + [ + "PRO_UART2_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_SDIO_HOST_INTERRUPT_MAP", + "offset": "0x198", + "reset": "0x00000010", + "fields": [ + [ + "PRO_SDIO_HOST_INTERRUPT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_EMAC_INT_MAP", + "offset": "0x19C", + "reset": "0x00000010", + "fields": [ + [ + "PRO_EMAC_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_PWM0_INTR_MAP", + "offset": "0x1A0", + "reset": "0x00000010", + "fields": [ + [ + "PRO_PWM0_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_PWM1_INTR_MAP", + "offset": "0x1A4", + "reset": "0x00000010", + "fields": [ + [ + "PRO_PWM1_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_PWM2_INTR_MAP", + "offset": "0x1A8", + "reset": "0x00000010", + "fields": [ + [ + "PRO_PWM2_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_PWM3_INTR_MAP", + "offset": "0x1AC", + "reset": "0x00000010", + "fields": [ + [ + "PRO_PWM3_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_LEDC_INT_MAP", + "offset": "0x1B0", + "reset": "0x00000010", + "fields": [ + [ + "PRO_LEDC_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_EFUSE_INT_MAP", + "offset": "0x1B4", + "reset": "0x00000010", + "fields": [ + [ + "PRO_EFUSE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_CAN_INT_MAP", + "offset": "0x1B8", + "reset": "0x00000010", + "fields": [ + [ + "PRO_CAN_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_RTC_CORE_INTR_MAP", + "offset": "0x1BC", + "reset": "0x00000010", + "fields": [ + [ + "PRO_RTC_CORE_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_RMT_INTR_MAP", + "offset": "0x1C0", + "reset": "0x00000010", + "fields": [ + [ + "PRO_RMT_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_PCNT_INTR_MAP", + "offset": "0x1C4", + "reset": "0x00000010", + "fields": [ + [ + "PRO_PCNT_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_I2C_EXT0_INTR_MAP", + "offset": "0x1C8", + "reset": "0x00000010", + "fields": [ + [ + "PRO_I2C_EXT0_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_I2C_EXT1_INTR_MAP", + "offset": "0x1CC", + "reset": "0x00000010", + "fields": [ + [ + "PRO_I2C_EXT1_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_RSA_INTR_MAP", + "offset": "0x1D0", + "reset": "0x00000010", + "fields": [ + [ + "PRO_RSA_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_SPI1_DMA_INT_MAP", + "offset": "0x1D4", + "reset": "0x00000010", + "fields": [ + [ + "PRO_SPI1_DMA_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_SPI2_DMA_INT_MAP", + "offset": "0x1D8", + "reset": "0x00000010", + "fields": [ + [ + "PRO_SPI2_DMA_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_SPI3_DMA_INT_MAP", + "offset": "0x1DC", + "reset": "0x00000010", + "fields": [ + [ + "PRO_SPI3_DMA_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_WDG_INT_MAP", + "offset": "0x1E0", + "reset": "0x00000010", + "fields": [ + [ + "PRO_WDG_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_TIMER_INT1_MAP", + "offset": "0x1E4", + "reset": "0x00000010", + "fields": [ + [ + "PRO_TIMER_INT1_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_TIMER_INT2_MAP", + "offset": "0x1E8", + "reset": "0x00000010", + "fields": [ + [ + "PRO_TIMER_INT2_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_TG_T0_EDGE_INT_MAP", + "offset": "0x1EC", + "reset": "0x00000010", + "fields": [ + [ + "PRO_TG_T0_EDGE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_TG_T1_EDGE_INT_MAP", + "offset": "0x1F0", + "reset": "0x00000010", + "fields": [ + [ + "PRO_TG_T1_EDGE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_TG_WDT_EDGE_INT_MAP", + "offset": "0x1F4", + "reset": "0x00000010", + "fields": [ + [ + "PRO_TG_WDT_EDGE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_TG_LACT_EDGE_INT_MAP", + "offset": "0x1F8", + "reset": "0x00000010", + "fields": [ + [ + "PRO_TG_LACT_EDGE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_TG1_T0_EDGE_INT_MAP", + "offset": "0x1FC", + "reset": "0x00000010", + "fields": [ + [ + "PRO_TG1_T0_EDGE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_TG1_T1_EDGE_INT_MAP", + "offset": "0x200", + "reset": "0x00000010", + "fields": [ + [ + "PRO_TG1_T1_EDGE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_TG1_WDT_EDGE_INT_MAP", + "offset": "0x204", + "reset": "0x00000010", + "fields": [ + [ + "PRO_TG1_WDT_EDGE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_TG1_LACT_EDGE_INT_MAP", + "offset": "0x208", + "reset": "0x00000010", + "fields": [ + [ + "PRO_TG1_LACT_EDGE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_MMU_IA_INT_MAP", + "offset": "0x20C", + "reset": "0x00000010", + "fields": [ + [ + "PRO_MMU_IA_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_MPU_IA_INT_MAP", + "offset": "0x210", + "reset": "0x00000010", + "fields": [ + [ + "PRO_MPU_IA_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "PRO_CACHE_IA_INT_MAP", + "offset": "0x214", + "reset": "0x00000010", + "fields": [ + [ + "PRO_CACHE_IA_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_MAC_INTR_MAP", + "offset": "0x218", + "reset": "0x00000010", + "fields": [ + [ + "APP_MAC_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_MAC_NMI_MAP", + "offset": "0x21C", + "reset": "0x00000010", + "fields": [ + [ + "APP_MAC_NMI_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_BB_INT_MAP", + "offset": "0x220", + "reset": "0x00000010", + "fields": [ + [ + "APP_BB_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_BT_MAC_INT_MAP", + "offset": "0x224", + "reset": "0x00000010", + "fields": [ + [ + "APP_BT_MAC_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_BT_BB_INT_MAP", + "offset": "0x228", + "reset": "0x00000010", + "fields": [ + [ + "APP_BT_BB_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_BT_BB_NMI_MAP", + "offset": "0x22C", + "reset": "0x00000010", + "fields": [ + [ + "APP_BT_BB_NMI_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_RWBT_IRQ_MAP", + "offset": "0x230", + "reset": "0x00000010", + "fields": [ + [ + "APP_RWBT_IRQ_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_RWBLE_IRQ_MAP", + "offset": "0x234", + "reset": "0x00000010", + "fields": [ + [ + "APP_RWBLE_IRQ_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_RWBT_NMI_MAP", + "offset": "0x238", + "reset": "0x00000010", + "fields": [ + [ + "APP_RWBT_NMI_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_RWBLE_NMI_MAP", + "offset": "0x23C", + "reset": "0x00000010", + "fields": [ + [ + "APP_RWBLE_NMI_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_SLC0_INTR_MAP", + "offset": "0x240", + "reset": "0x00000010", + "fields": [ + [ + "APP_SLC0_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_SLC1_INTR_MAP", + "offset": "0x244", + "reset": "0x00000010", + "fields": [ + [ + "APP_SLC1_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_UHCI0_INTR_MAP", + "offset": "0x248", + "reset": "0x00000010", + "fields": [ + [ + "APP_UHCI0_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_UHCI1_INTR_MAP", + "offset": "0x24C", + "reset": "0x00000010", + "fields": [ + [ + "APP_UHCI1_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG_T0_LEVEL_INT_MAP", + "offset": "0x250", + "reset": "0x00000010", + "fields": [ + [ + "APP_TG_T0_LEVEL_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG_T1_LEVEL_INT_MAP", + "offset": "0x254", + "reset": "0x00000010", + "fields": [ + [ + "APP_TG_T1_LEVEL_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG_WDT_LEVEL_INT_MAP", + "offset": "0x258", + "reset": "0x00000010", + "fields": [ + [ + "APP_TG_WDT_LEVEL_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG_LACT_LEVEL_INT_MAP", + "offset": "0x25C", + "reset": "0x00000010", + "fields": [ + [ + "APP_TG_LACT_LEVEL_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG1_T0_LEVEL_INT_MAP", + "offset": "0x260", + "reset": "0x00000010", + "fields": [ + [ + "APP_TG1_T0_LEVEL_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG1_T1_LEVEL_INT_MAP", + "offset": "0x264", + "reset": "0x00000010", + "fields": [ + [ + "APP_TG1_T1_LEVEL_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG1_WDT_LEVEL_INT_MAP", + "offset": "0x268", + "reset": "0x00000010", + "fields": [ + [ + "APP_TG1_WDT_LEVEL_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG1_LACT_LEVEL_INT_MAP", + "offset": "0x26C", + "reset": "0x00000010", + "fields": [ + [ + "APP_TG1_LACT_LEVEL_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_GPIO_INTERRUPT_MAP", + "offset": "0x270", + "reset": "0x00000010", + "fields": [ + [ + "APP_GPIO_INTERRUPT_APP_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_GPIO_INTERRUPT_NMI_MAP", + "offset": "0x274", + "reset": "0x00000010", + "fields": [ + [ + "APP_GPIO_INTERRUPT_APP_NMI_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_CPU_INTR_FROM_CPU_0_MAP", + "offset": "0x278", + "reset": "0x00000010", + "fields": [ + [ + "APP_CPU_INTR_FROM_CPU_0_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_CPU_INTR_FROM_CPU_1_MAP", + "offset": "0x27C", + "reset": "0x00000010", + "fields": [ + [ + "APP_CPU_INTR_FROM_CPU_1_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_CPU_INTR_FROM_CPU_2_MAP", + "offset": "0x280", + "reset": "0x00000010", + "fields": [ + [ + "APP_CPU_INTR_FROM_CPU_2_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_CPU_INTR_FROM_CPU_3_MAP", + "offset": "0x284", + "reset": "0x00000010", + "fields": [ + [ + "APP_CPU_INTR_FROM_CPU_3_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_SPI_INTR_0_MAP", + "offset": "0x288", + "reset": "0x00000010", + "fields": [ + [ + "APP_SPI_INTR_0_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_SPI_INTR_1_MAP", + "offset": "0x28C", + "reset": "0x00000010", + "fields": [ + [ + "APP_SPI_INTR_1_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_SPI_INTR_2_MAP", + "offset": "0x290", + "reset": "0x00000010", + "fields": [ + [ + "APP_SPI_INTR_2_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_SPI_INTR_3_MAP", + "offset": "0x294", + "reset": "0x00000010", + "fields": [ + [ + "APP_SPI_INTR_3_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_I2S0_INT_MAP", + "offset": "0x298", + "reset": "0x00000010", + "fields": [ + [ + "APP_I2S0_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_I2S1_INT_MAP", + "offset": "0x29C", + "reset": "0x00000010", + "fields": [ + [ + "APP_I2S1_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_UART_INTR_MAP", + "offset": "0x2A0", + "reset": "0x00000010", + "fields": [ + [ + "APP_UART_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_UART1_INTR_MAP", + "offset": "0x2A4", + "reset": "0x00000010", + "fields": [ + [ + "APP_UART1_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_UART2_INTR_MAP", + "offset": "0x2A8", + "reset": "0x00000010", + "fields": [ + [ + "APP_UART2_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_SDIO_HOST_INTERRUPT_MAP", + "offset": "0x2AC", + "reset": "0x00000010", + "fields": [ + [ + "APP_SDIO_HOST_INTERRUPT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_EMAC_INT_MAP", + "offset": "0x2B0", + "reset": "0x00000010", + "fields": [ + [ + "APP_EMAC_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_PWM0_INTR_MAP", + "offset": "0x2B4", + "reset": "0x00000010", + "fields": [ + [ + "APP_PWM0_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_PWM1_INTR_MAP", + "offset": "0x2B8", + "reset": "0x00000010", + "fields": [ + [ + "APP_PWM1_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_PWM2_INTR_MAP", + "offset": "0x2BC", + "reset": "0x00000010", + "fields": [ + [ + "APP_PWM2_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_PWM3_INTR_MAP", + "offset": "0x2C0", + "reset": "0x00000010", + "fields": [ + [ + "APP_PWM3_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_LEDC_INT_MAP", + "offset": "0x2C4", + "reset": "0x00000010", + "fields": [ + [ + "APP_LEDC_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_EFUSE_INT_MAP", + "offset": "0x2C8", + "reset": "0x00000010", + "fields": [ + [ + "APP_EFUSE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_CAN_INT_MAP", + "offset": "0x2CC", + "reset": "0x00000010", + "fields": [ + [ + "APP_CAN_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_RTC_CORE_INTR_MAP", + "offset": "0x2D0", + "reset": "0x00000010", + "fields": [ + [ + "APP_RTC_CORE_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_RMT_INTR_MAP", + "offset": "0x2D4", + "reset": "0x00000010", + "fields": [ + [ + "APP_RMT_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_PCNT_INTR_MAP", + "offset": "0x2D8", + "reset": "0x00000010", + "fields": [ + [ + "APP_PCNT_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_I2C_EXT0_INTR_MAP", + "offset": "0x2DC", + "reset": "0x00000010", + "fields": [ + [ + "APP_I2C_EXT0_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_I2C_EXT1_INTR_MAP", + "offset": "0x2E0", + "reset": "0x00000010", + "fields": [ + [ + "APP_I2C_EXT1_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_RSA_INTR_MAP", + "offset": "0x2E4", + "reset": "0x00000010", + "fields": [ + [ + "APP_RSA_INTR_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_SPI1_DMA_INT_MAP", + "offset": "0x2E8", + "reset": "0x00000010", + "fields": [ + [ + "APP_SPI1_DMA_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_SPI2_DMA_INT_MAP", + "offset": "0x2EC", + "reset": "0x00000010", + "fields": [ + [ + "APP_SPI2_DMA_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_SPI3_DMA_INT_MAP", + "offset": "0x2F0", + "reset": "0x00000010", + "fields": [ + [ + "APP_SPI3_DMA_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_WDG_INT_MAP", + "offset": "0x2F4", + "reset": "0x00000010", + "fields": [ + [ + "APP_WDG_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TIMER_INT1_MAP", + "offset": "0x2F8", + "reset": "0x00000010", + "fields": [ + [ + "APP_TIMER_INT1_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TIMER_INT2_MAP", + "offset": "0x2FC", + "reset": "0x00000010", + "fields": [ + [ + "APP_TIMER_INT2_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG_T0_EDGE_INT_MAP", + "offset": "0x300", + "reset": "0x00000010", + "fields": [ + [ + "APP_TG_T0_EDGE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG_T1_EDGE_INT_MAP", + "offset": "0x304", + "reset": "0x00000010", + "fields": [ + [ + "APP_TG_T1_EDGE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG_WDT_EDGE_INT_MAP", + "offset": "0x308", + "reset": "0x00000010", + "fields": [ + [ + "APP_TG_WDT_EDGE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG_LACT_EDGE_INT_MAP", + "offset": "0x30C", + "reset": "0x00000010", + "fields": [ + [ + "APP_TG_LACT_EDGE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG1_T0_EDGE_INT_MAP", + "offset": "0x310", + "reset": "0x00000010", + "fields": [ + [ + "APP_TG1_T0_EDGE_INT_MAP", + 0, + 5 + ] + ] + }, + { + "name": "APP_TG1_T1_EDGE_INT_MAP", + "offset": "0x314", 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zLkQnT|Azv)Yz5ugre2H! z10h|ZHspNMn22a8o2pJpMQq~)u{B&>q+G_7PMe7&VKXp`#V!fuu@54^R~I%F^9mKN zn;Y_;CMrh!#XP|#WQjLx*tbA7{PX;i1OMc}KRNJE4*Zh?|Kz|wIq**o P{F4L!s), div = (esk_rf_read(k->p, SYSCLK_CONF, 4) & 0x3ffu) + 1u; + if (sel == 1 || sel == 3) { + u32 per = esk_esp32_dport_cpuperiod(k->s); + return per == 2 ? 240000000u : per == 1 ? 160000000u : 80000000u; + } + return (sel == 2 ? RC_FAST_HZ : ESP32_XTAL_HZ) / div; +} + +static u32 core_hz(struct esk_mach *m) +{ + struct e32_apbctrl *k = (struct e32_apbctrl *)m->clock_ctx; + if (!k) + return ESP32_XTAL_HZ; + k->hz = cpu_hz(k); + return k->hz; +} + +u32 esk_esp32_cpu_hz(struct esk_mach *m) +{ + return core_hz(m); +} + +u32 esk_esp32_apb_hz(struct esk_mach *m) +{ + u32 sel = esk_esp32_rtc_soc_clk_sel(m); + return sel == 1 || sel == 3 ? 80000000u : core_hz(m); +} + +static u32 ap_read(void *ctx, u32 off, int n) +{ + struct e32_apbctrl *k = (struct e32_apbctrl *)ctx; + return esk_rf_read(k->p, off, n); +} + +static void ap_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_apbctrl *k = (struct e32_apbctrl *)ctx; + esk_rf_write(k->p, off, n, v); + if (off == SYSCLK_CONF) + k->s->yield = 1; /* the runtime sees the core's new clock now */ +} + +static void ap_reset(void *ctx) +{ + struct e32_apbctrl *k = (struct e32_apbctrl *)ctx; + k->hz = ESP32_XTAL_HZ; +} + +const struct esk_dev_ops esk_esp32_apbctrl_ops = { + "esp32-apbctrl", ap_read, ap_write, ap_reset, 0, 0, +}; + +void *esk_esp32_apbctrl_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_apbctrl *k = (struct e32_apbctrl *)esk_mach_alloc(s, sizeof *k); + struct esk_rf_reg *date = esk_rf_reg_at(p, DATE); + if (!k) + return 0; + k->s = s; + k->p = p; + k->hz = ESP32_XTAL_HZ; + if (date) + esk_rf_set_reset(date, date->reset | 0x80000000u); + s->core_hz = core_hz; + s->clock_ctx = k; + return k; +} diff --git a/core/mcu/esp32/soc/dport.c b/core/mcu/esp32/soc/dport.c new file mode 100644 index 000000000..f72c1c48c --- /dev/null +++ b/core/mcu/esp32/soc/dport.c @@ -0,0 +1,346 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* dport.c -- the ESP32's DPORT registers (TRM v5 chapters 3, 4 and 5): + * + * - the APP_CPU: held in reset while APPCPU_CTRL_A's RESETTING is set + * (1 out of reset), its clock gated while APPCPU_CTRL_B's CLKGATE_EN + * is clear, stalled while APPCPU_CTRL_C's RUNSTALL is set; released, + * it starts at its reset vector, where the ROM reads APPCPU_CTRL_D's + * boot address; + * - the interrupt matrix (chapter 4): 69 peripheral sources, each mapped + * by its PRO_ and APP_ *_MAP register onto one of each CPU's 32 + * interrupts; an interrupt sees the OR of the sources mapped onto it, + * those numbers the CPU drives itself (its timers 6, 15 and 16, its + * software interrupts 7 and 29, profiling 11) none; PRO_ and + * APP_INTR_STATUS_0-2 read the sources' levels; CPU_INTR_FROM_CPU_0-3 + * drive sources 24-27; + * - the caches and their flash MMU (chapter 3.3.2): each CPU's table of + * 64 KB pages at 0x3FF10000 (PRO_CPU) and 0x3FF12000 (APP_CPU), an + * entry's bits [7:0] the flash page and bit 8 invalid; entries 0-63 + * map DROM0 (0x3F400000), 64-127 IRAM0 (0x40000000, of which + * 0x400D0000 up is the description's flash_irom window); the window + * reads the flash's bytes the PRO_CPU's entries name. A cache flush + * (PRO_ or APP_CACHE_CTRL's FLUSH_ENA) is done at once (FLUSH_DONE), + * and the caches' state (PRO_ and APP_DCACHE_DBUG0's CACHE_STATE) + * reads 1, idle, which ESP-IDF waits for before disabling them; + * pages whose flash the program has written since they were mapped + * show it after a flush; + * - CPU_PER_CONF's CPUPERIOD_SEL, which with RTC_CNTL's SOC_CLK_SEL and + * APB_CTRL's divider sets the CPU's clock (apbctrl.c). + * Inside, the caches hold the mapped pages whole rather than 32 KB of + * lines, and both CPUs read through the PRO_CPU's table (ESP-IDF keeps + * the two the same); a CPU's cache enable and the buses' mask bits + * (PRO_CACHE_CTRL1) do not stop accesses. + * Not yet: the cache's lock regions, PSRAM (DRAM1, which the module does + * not have), the boot remap (PRO_BOOT_REMAP_CTRL), the APB and AHB + * access permissions (DPORT_APB_MASK, AHBLITE_MPU_TABLE), the MMU's + * access-error interrupts, the trace memory and the CPU record. */ +#include + +#include "mcu/esp32/soc/esp32.h" +#include "mcu/xtensa/lx6.h" + + +#define APPCPU_CTRL_A 0x2Cu +#define APPCPU_CTRL_B 0x30u +#define APPCPU_CTRL_C 0x34u +#define CPU_PER_CONF 0x3Cu +#define PRO_CACHE_CTRL 0x40u +#define APP_CACHE_CTRL 0x58u +#define FROM_CPU_0 0xDCu +#define PRO_STATUS_0 0xECu +#define APP_STATUS_0 0xF8u +#define PRO_MAP 0x104u +#define APP_MAP 0x218u +#define PRO_DCACHE_DBUG0 0x3F0u +#define APP_DCACHE_DBUG0 0x418u +#define CACHE_FLUSH_ENA 0x10u +#define CACHE_FLUSH_DONE 0x20u + +#define MMU_BASE 0x3FF10000u +#define MMU_WORDS 2048 /* per CPU: 0x2000 bytes */ +#define MMU_INVALID 0x100u +#define PAGE 0x10000u +#define DROM 0x3F400000u +#define IROM 0x400D0000u +#define IROM_FIRST 77 /* 0x400D0000's entry */ +#define INTERNAL_INTS 0x20018840u /* 6, 7, 11, 15, 16, 29: the CPU's own */ + +struct e32_dport { + struct esk_mach *s; + struct esk_rf_periph *p; + u8 src[ESP32_NSOURCES]; + u32 lines[2]; /* each CPU's interrupt inputs as the matrix drives them */ + u32 mmu[2][MMU_WORDS]; + u8 stale[128]; + u8 *app_rom; /* the ROM as the APP_CPU sees it */ +}; + +static struct e32_dport *dport_of(struct esk_mach *m) +{ + return m->rf ? (struct e32_dport *)esk_rf_ctx_of(m->rf, &esk_esp32_dport_ops) : 0; +} + +static u32 reg(struct e32_dport *k, u32 off) +{ + return esk_rf_read(k->p, off, 4); +} + +static void hw(struct e32_dport *k, u32 off, u32 v) +{ + struct esk_rf_reg *r = esk_rf_reg_at(k->p, off); + if (r) + esk_rf_hw(r, v); +} + +/* ---- the interrupt matrix ---------------------------------------------- */ + +static void route(struct e32_dport *k) +{ + int cpu, i, n = esk_lx6_cores(k->s); + for (cpu = 0; cpu < 2; cpu++) { + u32 lines = 0, st[3] = { 0, 0, 0 }; + for (i = 0; i < ESP32_NSOURCES; i++) { + u32 map = reg(k, (cpu ? APP_MAP : PRO_MAP) + 4u * (u32)i) & 31u; + if (!(k->src[i] & (1u << cpu))) + continue; + st[i / 32] |= 1u << (i % 32); + if (!(INTERNAL_INTS & (1u << map))) + lines |= 1u << map; + } + for (i = 0; i < 3; i++) + hw(k, (cpu ? APP_STATUS_0 : PRO_STATUS_0) + 4u * (u32)i, st[i]); + if (cpu < n && lines != k->lines[cpu]) { + u32 ch = lines ^ k->lines[cpu]; + k->lines[cpu] = lines; + for (i = 0; i < 32; i++) + if (ch & (1u << i)) + esk_lx6_irq(k->s, cpu, i, (int)((lines >> i) & 1u)); + } + } +} + +void esk_esp32_source(struct esk_mach *m, int src, int level) +{ + struct e32_dport *k = dport_of(m); + u8 v = level ? 3u : 0u; + if (!k || src < 0 || src >= ESP32_NSOURCES || k->src[src] == v) + return; + k->src[src] = v; + route(k); +} + +void esk_esp32_source_cpu(struct esk_mach *m, int cpu, int src, int level) +{ + struct e32_dport *k = dport_of(m); + u8 v; + if (!k || src < 0 || src >= ESP32_NSOURCES || cpu < 0 || cpu > 1) + return; + v = (u8)(level ? k->src[src] | (1u << cpu) : k->src[src] & ~(1u << cpu)); + if (v == k->src[src]) + return; + k->src[src] = v; + route(k); +} + +/* ---- the flash MMU and the windows ------------------------------------- */ + +static void fill(struct e32_dport *k, int entry) +{ + struct esk_store *st = esk_mach_store(k->s, "flash"); + u32 base = entry < 64 ? DROM + (u32)entry * PAGE : IROM + (u32)(entry - IROM_FIRST) * PAGE; + struct esk_region *w; + u32 e = k->mmu[0][entry]; + u8 *dst; + if (entry >= 64 && entry < IROM_FIRST) + return; + w = esk_bus_region(&k->s->bus, base, PAGE); + if (!w || w->kind != ESK_MEM_WINDOW) + return; + dst = w->mem + (base - w->base); + if ((e & MMU_INVALID) || !st || st->size < PAGE) + memset(dst, 0, PAGE); + else + memcpy(dst, st->mem + ((e & 0xffu) * PAGE) % st->size, PAGE); + if (entry < 128) + k->stale[entry] = 0; + esk_bus_code_changed(&k->s->bus); +} + +void esk_esp32_flash_written(struct esk_mach *m, u32 addr, u32 len) +{ + struct e32_dport *k = dport_of(m); + int i; + if (!k || !len) + return; + for (i = 0; i < 128; i++) { + u32 at = (k->mmu[0][i] & 0xffu) * PAGE; + if (!(k->mmu[0][i] & MMU_INVALID) && addr < at + PAGE && at < addr + len) + k->stale[i] = 1; + } +} + +static void flush(struct e32_dport *k) +{ + int i; + for (i = 0; i < 128; i++) + if (k->stale[i]) + fill(k, i); +} + +static u32 mmu_read(void *ctx, u32 off, int n) +{ + struct e32_dport *k = (struct e32_dport *)ctx; + u32 cpu = off >= 0x2000u, i = (off & 0x1fffu) / 4u; + ES_UNUSED(n); + return k->mmu[cpu][i] >> (8 * (off & 3u)); +} + +static void mmu_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_dport *k = (struct e32_dport *)ctx; + u32 cpu = off >= 0x2000u, i = (off & 0x1fffu) / 4u; + if (n != 4) + return; + v &= 0x1ffu; + if (k->mmu[cpu][i] == v) + return; + k->mmu[cpu][i] = v; + if (cpu == 0 && i < 128) + fill(k, (int)i); +} + +static void mmu_reset(void *ctx) +{ + struct e32_dport *k = (struct e32_dport *)ctx; + int i, c; + for (c = 0; c < 2; c++) + for (i = 0; i < MMU_WORDS; i++) + k->mmu[c][i] = MMU_INVALID; + for (i = 0; i < 128; i++) + fill(k, i); +} + +static const struct esk_dev_ops mmu_ops = { + "esp32-mmu", mmu_read, mmu_write, mmu_reset, 0, 0, +}; + +/* ---- the APP_CPU ------------------------------------------------------- */ + +static void app_cpu(struct e32_dport *k) +{ + esk_lx6_core_stall(k->s, 1, 0, !(reg(k, APPCPU_CTRL_B) & 1u)); + esk_lx6_core_stall(k->s, 1, 1, (int)(reg(k, APPCPU_CTRL_C) & 1u)); + esk_lx6_core_reset(k->s, 1, (int)(reg(k, APPCPU_CTRL_A) & 1u)); +} + +/* ---- the APP_CPU's ROM -------------------------------------------------- */ + +/* The APP_CPU's ROM: the PRO_CPU's with every word that points into the + * PRO_CPU's ROM data (0x3FFE0010-0x3FFE3F20: its .data, .bss and stack) + * pointing into the APP_CPU's (0x3FFE3F20 on: +0x3F10), so that the ROM's + * routines keep each CPU's state apart (ESP-IDF's esp32.rom.ld names + * g_ticks_per_us_pro and _app, and ets_update_cpu_frequency_rom "updates + * g_ticks_per_us on the current CPU only"). Espressif's QEMU loads this + * view as a second image (esp32-v3-rom-app.bin, sha256 6d3240e7...8442): + * the one made here equals it byte for byte over its 455,722 bytes. */ +#define ROM_BASE 0x40000000u +#define ROM_SIZE 0x70000u +#define ROM1_DBUS 0x3FF90000u +#define PRO_DATA_LO 0x3FFE0010u +#define PRO_DATA_HI 0x3FFE3F20u +#define APP_DATA_SHIFT 0x3F10u + +static void app_rom(struct e32_dport *k) +{ + struct esk_region *r = esk_bus_region(&k->s->bus, ROM_BASE, ROM_SIZE); + u32 o; + if (k->app_rom || !r || esk_lx6_cores(k->s) < 2) + return; + k->app_rom = (u8 *)esk_mach_alloc(k->s, ROM_SIZE); + if (!k->app_rom) + return; + memcpy(k->app_rom, r->mem + (ROM_BASE - r->base), ROM_SIZE); + for (o = 0; o < ROM_SIZE; o += 4) { + u8 *p = k->app_rom + o; + u32 v = (u32)p[0] | (u32)p[1] << 8 | (u32)p[2] << 16 | (u32)p[3] << 24; + if (v >= PRO_DATA_LO && v <= PRO_DATA_HI) { + v += APP_DATA_SHIFT; + p[0] = (u8)v; + p[1] = (u8)(v >> 8); + p[2] = (u8)(v >> 16); + p[3] = (u8)(v >> 24); + } + } + (void)esk_lx6_view(k->s, 1, ROM_BASE, ROM_SIZE, k->app_rom); + (void)esk_lx6_view(k->s, 1, ROM1_DBUS, 0x10000u, k->app_rom + 0x60000u); +} + +/* ---- the registers ----------------------------------------------------- */ + +static u32 dp_read(void *ctx, u32 off, int n) +{ + struct e32_dport *k = (struct e32_dport *)ctx; + return esk_rf_read(k->p, off, n); +} + +static void dp_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_dport *k = (struct e32_dport *)ctx; + esk_rf_write(k->p, off, n, v); + if (off >= APPCPU_CTRL_A && off <= APPCPU_CTRL_C) { + app_cpu(k); + } else if (off == PRO_CACHE_CTRL || off == APP_CACHE_CTRL) { + u32 c = reg(k, off); + if (c & CACHE_FLUSH_ENA) { + flush(k); + c |= CACHE_FLUSH_DONE; + } else { + c &= ~CACHE_FLUSH_DONE; + } + hw(k, off, c); + } else if (off >= FROM_CPU_0 && off < FROM_CPU_0 + 16u) { + esk_esp32_source(k->s, 24 + (int)((off - FROM_CPU_0) / 4u), (int)(reg(k, off) & 1u)); + } else if (off >= PRO_MAP && off < APP_MAP + 4u * ESP32_NSOURCES) { + route(k); + } else if (off == CPU_PER_CONF) { + k->s->yield = 1; /* the CPU's clock may change (apbctrl.c) */ + } +} + +static void dp_reset(void *ctx) +{ + struct e32_dport *k = (struct e32_dport *)ctx; + app_rom(k); + memset(k->src, 0, sizeof k->src); + k->lines[0] = k->lines[1] = 0; + hw(k, PRO_CACHE_CTRL, reg(k, PRO_CACHE_CTRL) | CACHE_FLUSH_DONE); + hw(k, APP_CACHE_CTRL, reg(k, APP_CACHE_CTRL) | CACHE_FLUSH_DONE); + hw(k, PRO_DCACHE_DBUG0, 1u << 7); /* CACHE_STATE: idle */ + hw(k, APP_DCACHE_DBUG0, 1u << 7); + route(k); +} + +const struct esk_dev_ops esk_esp32_dport_ops = { + "esp32-dport", dp_read, dp_write, dp_reset, 0, 0, +}; + +void *esk_esp32_dport_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_dport *k = (struct e32_dport *)esk_mach_alloc(s, sizeof *k); + if (!k) + return 0; + k->s = s; + k->p = p; + if (esk_mach_add_dev(s, MMU_BASE, 2u * MMU_WORDS * 4u, &mmu_ops, k) != ES_OK || + esk_esp32_misc_add(s) || esk_esp32_regi2c_add(s)) + return 0; + mmu_reset(k); + return k; +} + +u32 esk_esp32_dport_cpuperiod(struct esk_mach *m) +{ + struct e32_dport *k = dport_of(m); + return k ? reg(k, CPU_PER_CONF) & 3u : 0; +} diff --git a/core/mcu/esp32/soc/efuse.c b/core/mcu/esp32/soc/efuse.c new file mode 100644 index 000000000..050574ec0 --- /dev/null +++ b/core/mcu/esp32/soc/efuse.c @@ -0,0 +1,261 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* efuse.c -- the ESP32's eFuse controller (TRM v5 chapter 20): four blocks + * of one-time-programmable bits (BLOCK0's seven words, BLOCK1-3's eight), + * read into the RDATA registers at a chip reset and again by a read + * command, programmed (bits only from 0 to 1) from the WDATA registers by + * a program command. + * + * - CMD's READ_CMD (bit 0) with CONF's OP_CODE 0x5AA5 loads every block + * into its RDATA registers; PGM_CMD (bit 1) with 0x5A5A ORs every + * block's WDATA into its bits. CMD reads the command until it is done + * (the ROM checks that it does: a CMD that reads 0 at once is a + * glitch, and it resets the chip), then 0, and INT_RAW's READ_DONE or + * PGM_DONE is set; another op code does nothing. The WDATA registers + * keep what is written until written again. + * - Read protection: BLOCK0's RD_DIS bits (16-19) make BLOCK1, BLOCK2 or + * BLOCK3 read 0 (the flash encryption key in BLOCK1 is still used by + * the hardware). Write protection: a block whose WR_DIS bit (7, 8, 9 + * for BLOCK1-3) is set is not programmed; BLOCK0's own fields are + * programmed whatever their WR_DIS bits say (not yet: per field). + * + * The chip's bits out of the factory, those of an ESP32-D0WD-V3 of chip + * revision v3.1 as esptool reads the owner's board: CHIP_PACKAGE 1 + * (D0WD), CHIP_VER_REV1 and CHIP_VER_REV2 set (with APB_CTRL's DATE bit + * 31, the major revision 3), WAFER_VERSION_MINOR 1; Coding Scheme None; + * an ADC reference voltage calibration (ADC_VREF, "Vref calibration in + * eFuse"); the MAC 24:0A:C4:45:6D:62, Espressif's OUI and a serial of the + * model's, with its CRC-8 (the ROM's esp_rom_efuse_mac_address_crc8), or + * the one a board's settings give its chip (settings.mac); every other + * bit 0 (no secure boot, no flash encryption, no keys). + * Inside, a read takes 1 us and a program 1 ms, whatever EFUSE_CLK's + * timing fields say (estimates: the TRM gives the timing parameters, not + * the operations' durations). + * Not yet: the 3/4 coding scheme's check, BLOCK0's per-field write + * protection. */ +#include + +#include "mcu/esp32/soc/esp32.h" + +#define OP_READ 0x5AA5u +#define OP_PGM 0x5A5Au +#define CONF 0xFCu +#define CMD 0x104u +#define INT_RAW 0x108u +#define INT_ST 0x10Cu +#define INT_ENA 0x110u +#define INT_CLR 0x114u + +/* each block's RDATA and WDATA offsets and words */ +static const struct { + u32 rd, wr; + int words; +} blocks[4] = { { 0x00, 0x1C, 7 }, { 0x38, 0x98, 8 }, { 0x58, 0xB8, 8 }, { 0x78, 0xD8, 8 } }; + +struct e32_efuse { + struct esk_mach *s; + struct esk_rf_periph *p; + u32 fuse[4][8]; /* the bits themselves */ + u32 raw; /* INT_RAW */ + int programmed; /* the bits differ from the factory's */ + u32 busy; /* the command in progress (1 read, 2 program), or 0 */ + u64 left; /* its cycles still to go */ + int clocked; +}; + +static void hw(struct esk_rf_periph *p, u32 off, u32 v) +{ + struct esk_rf_reg *r = esk_rf_reg_at(p, off); + if (r) + esk_rf_hw(r, v); +} + +static struct e32_efuse *efuse_of(struct esk_mach *m) +{ + return m->rf ? (struct e32_efuse *)esk_rf_ctx_of(m->rf, &esk_esp32_efuse_ops) : 0; +} + +/* CRC-8, polynomial x^8 + x^5 + x^4 + 1 reflected (0x8C), as the ROM's + * esp_rom_efuse_mac_address_crc8 computes it over the MAC */ +static u8 crc8(const u8 *p, int n) +{ + u8 crc = 0; + int i, b; + for (i = 0; i < n; i++) { + crc ^= p[i]; + for (b = 0; b < 8; b++) + crc = (u8)((crc & 1u) ? (crc >> 1) ^ 0x8Cu : crc >> 1); + } + return crc; +} + +static void factory(struct e32_efuse *k) +{ + static const u8 dflt[6] = { 0x24, 0x0A, 0xC4, 0x45, 0x6D, 0x62 }; + const u8 *mac = k->s->has_factory_mac ? k->s->factory_mac : dflt; + memset(k->fuse, 0, sizeof k->fuse); + /* MAC: byte 0 at bit 72, ..., byte 5 at bit 32; its CRC at bit 80 */ + k->fuse[0][1] = (u32)mac[5] | (u32)mac[4] << 8 | (u32)mac[3] << 16 | (u32)mac[2] << 24; + k->fuse[0][2] = (u32)mac[1] | (u32)mac[0] << 8 | (u32)crc8(mac, 6) << 16; + k->fuse[0][3] = 1u << 9 /* CHIP_PACKAGE 1: D0WD */ + | 1u << 15; /* CHIP_VER_REV1 */ + k->fuse[0][4] = 0x0Au << 8; /* ADC_VREF */ + k->fuse[0][5] = 1u << 20 /* CHIP_VER_REV2 */ + | 1u << 24; /* WAFER_VERSION_MINOR 1 */ +} + +/* the RDATA registers from the bits, with read protection */ +static void reload(struct e32_efuse *k) +{ + u32 rd_dis = (k->fuse[0][0] >> 16) & 15u; + int b, w; + for (b = 0; b < 4; b++) + for (w = 0; w < blocks[b].words; w++) { + u32 v = k->fuse[b][w]; + if (b > 0 && (rd_dis & (1u << (b - 1)))) + v = 0; + hw(k->p, blocks[b].rd + 4u * (u32)w, v); + } +} + +static void program(struct e32_efuse *k) +{ + u32 wr_dis = k->fuse[0][0] & 0xffffu; + int b, w; + for (b = 0; b < 4; b++) { + if (b > 0 && (wr_dis & (1u << (6 + b)))) + continue; + for (w = 0; w < blocks[b].words; w++) + k->fuse[b][w] |= esk_rf_read(k->p, blocks[b].wr + 4u * (u32)w, 4); + } + k->programmed = 1; +} + +static void irq(struct e32_efuse *k) +{ + u32 ena = esk_rf_read(k->p, INT_ENA, 4); + hw(k->p, INT_RAW, k->raw); + hw(k->p, INT_ST, k->raw & ena); + esk_esp32_source(k->s, esk_rf_irq(k->p, "EFUSE"), (k->raw & ena) != 0); +} + +static void start(struct e32_efuse *k, u32 cmd, u32 us) +{ + k->busy = cmd; + k->left = (u64)esk_mach_core_hz(k->s) * us / 1000000u; + if (!k->left) + k->left = 1; + hw(k->p, CMD, cmd); + esk_rf_clock(k->p, &k->clocked, 1); +} + +static void done(struct e32_efuse *k) +{ + if (k->busy == 1) { + reload(k); + k->raw |= 1u; + } else { + program(k); + k->raw |= 2u; + } + k->busy = 0; + hw(k->p, CMD, 0); + esk_rf_clock(k->p, &k->clocked, 0); + irq(k); +} + +static void ef_tick(void *ctx, u32 cycles) +{ + struct e32_efuse *k = (struct e32_efuse *)ctx; + if (!k->busy) + return; + if (k->left > cycles) { + k->left -= cycles; + return; + } + done(k); +} + +static int ef_next(void *ctx, u32 *cycles) +{ + struct e32_efuse *k = (struct e32_efuse *)ctx; + if (!k->busy) + return 0; + *cycles = k->left > 0xffffffffu ? 0xffffffffu : (u32)k->left; + return 1; +} + +static u32 ef_read(void *ctx, u32 off, int n) +{ + struct e32_efuse *k = (struct e32_efuse *)ctx; + return esk_rf_read(k->p, off, n); +} + +static void ef_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_efuse *k = (struct e32_efuse *)ctx; + esk_rf_write(k->p, off, n, v); + if (off == CMD) { + u32 op = esk_rf_read(k->p, CONF, 4) & 0xffffu; + if (!k->busy && (v & 1u) && op == OP_READ) + start(k, 1, 1); + else if (!k->busy && (v & 2u) && op == OP_PGM) + start(k, 2, 1000); + else + hw(k->p, CMD, k->busy); + } else if (off == INT_CLR) { + k->raw &= ~v; + hw(k->p, INT_CLR, 0); + irq(k); + } else if (off == INT_ENA) { + irq(k); + } +} + +static void ef_reset(void *ctx) +{ + struct e32_efuse *k = (struct e32_efuse *)ctx; + if (!k->programmed) + factory(k); /* the board's MAC is known by now */ + k->raw = 0; + k->busy = 0; + k->clocked = 0; + reload(k); +} + +const struct esk_dev_ops esk_esp32_efuse_ops = { + "esp32-efuse", ef_read, ef_write, ef_reset, ef_tick, ef_next, +}; + +void *esk_esp32_efuse_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_efuse *k = (struct e32_efuse *)esk_mach_alloc(s, sizeof *k); + if (!k) + return 0; + k->s = s; + k->p = p; + factory(k); + return k; +} + +int esk_esp32_efuse_flash_crypt(struct esk_mach *m) +{ + struct e32_efuse *k = efuse_of(m); + u32 cnt, ones = 0; + if (!k) + return 0; + cnt = (k->fuse[0][0] >> 20) & 0x7fu; + while (cnt) { + ones += cnt & 1u; + cnt >>= 1; + } + return (int)(ones & 1u); +} + +u32 esk_esp32_efuse_word(struct esk_mach *m, int block, int word) +{ + struct e32_efuse *k = efuse_of(m); + if (!k || block < 0 || block > 3 || word < 0 || word >= blocks[block].words) + return 0; + return k->fuse[block][word]; +} diff --git a/core/mcu/esp32/soc/esp32.h b/core/mcu/esp32/soc/esp32.h new file mode 100644 index 000000000..65cb9db5e --- /dev/null +++ b/core/mcu/esp32/soc/esp32.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* esp32.h -- the ESP32's peripheral models (ESP32 Technical Reference + * Manual v5), over the register file converted from Espressif's esp32.svd, + * for the framework's Xtensa LX6 cores (mcu/xtensa/lx6.c). + * + * efuse.c the eFuse controller and the chip's factory bits + * dport.c DPORT: the APP_CPU's reset, clock and stall, the CPU clock, + * the caches and their flash MMU, the interrupt matrix, the + * cross-CPU interrupts + * rtc.c RTC_CNTL: the reset causes, the RTC timer and watchdog, the + * software resets and stalls, the store registers + * uart.c UART0-2: FIFOs, frames at the baud rate, interrupts + * timg.c TIMG0 and TIMG1: T0, T1, the MWDT, RTC_SLOW_CLK's calibration + * gpio.c the GPIO matrix, the IO MUX and the strapping latch + * spi.c SPI0 and SPI1 in front of the flash, and the flash itself + * apbctrl.c APB_CTRL: the CPU's and APB's clock dividers + * sha.c the SHA accelerator + * misc.c the random number generator, the AHB view of the + * peripherals */ +#ifndef ESK_MCU_ESP32_SOC_H +#define ESK_MCU_ESP32_SOC_H + +#include "mcu/rf.h" + +/* the interrupt matrix's sources (TRM table 4.3-2) */ +#define ESP32_NSOURCES 69 + +/* a peripheral's interrupt source `src` (0-68) is at `level`, for both + * CPUs or (_cpu) one CPU's matrix (GPIO's PRO_CPU and APP_CPU interrupts) */ +void esk_esp32_source(struct esk_mach *m, int src, int level); +void esk_esp32_source_cpu(struct esk_mach *m, int cpu, int src, int level); + +extern const struct esk_dev_ops esk_esp32_efuse_ops; +void *esk_esp32_efuse_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_dport_ops; +void *esk_esp32_dport_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_rtc_ops; +void *esk_esp32_rtc_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_uart_ops; +void *esk_esp32_uart_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_timg_ops; +void *esk_esp32_timg_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_gpio_ops; +void *esk_esp32_gpio_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_iomux_ops; +void *esk_esp32_iomux_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_spi_ops; +void *esk_esp32_spi_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_apbctrl_ops; +void *esk_esp32_apbctrl_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_sha_ops; +void *esk_esp32_sha_create(struct esk_mach *s, struct esk_rf_periph *p); +/* the RNG and the AHB view of the peripherals (misc.c): 0, or -1 */ +int esk_esp32_misc_add(struct esk_mach *s); +/* the internal I2C master to the analog blocks (regi2c.c): 0, or -1 */ +int esk_esp32_regi2c_add(struct esk_mach *s); + +/* the chip's eFuse fields the hardware reads */ +int esk_esp32_efuse_flash_crypt(struct esk_mach *m); +u32 esk_esp32_efuse_word(struct esk_mach *m, int block, int word); + +/* the clocks: the CPU's (CPU_CLK), the APB's, the crystal's, in Hz */ +u32 esk_esp32_cpu_hz(struct esk_mach *m); +u32 esk_esp32_apb_hz(struct esk_mach *m); +#define ESP32_XTAL_HZ 40000000u +/* RTC_CNTL CLK_CONF's SOC_CLK_SEL, and RTC_SLOW_CLK in Hz */ +u32 esk_esp32_rtc_soc_clk_sel(struct esk_mach *m); +double esk_esp32_rtc_slow_hz(struct esk_mach *m); +/* DPORT CPU_PER_CONF's CPUPERIOD_SEL */ +u32 esk_esp32_dport_cpuperiod(struct esk_mach *m); + +/* a reset of TRM table 4.3-? `code` (1 POWERON, 3 SW_SYS, 12 SW_CPU, ...), + * of the whole chip (system) or one CPU */ +void esk_esp32_reset(struct esk_mach *m, int code); +void esk_esp32_cpu_reset(struct esk_mach *m, int core, int code); +/* the reset cause each CPU reports (RTC_CNTL RESET_STATE) */ +void esk_esp32_rtc_reset_cause(struct esk_mach *m, int core, int code); + +/* the flash's bytes from `addr` on, `len` of them, changed: the caches' + * pages over them are stale */ +void esk_esp32_flash_written(struct esk_mach *m, u32 addr, u32 len); + +/* the strapping pins' levels latched at reset (GPIO_STRAP) */ +u32 esk_esp32_strap(struct esk_mach *m); +/* where a UART's TXD (tx) or RXD is: 0 and the runtime's port and bit */ +int esk_esp32_uart_pin(struct esk_mach *m, const char *unit, int tx, int *port, int *bit); +/* the board drove a pin or let it go: the levels again */ +void esk_esp32_pins_changed(struct esk_mach *m); +/* a peripheral output signal of the GPIO matrix (TRM table 4-2) driven by + * its model: its level and enable */ +void esk_esp32_signal(struct esk_mach *m, int sig, int level, int oe); +/* a peripheral input signal's level as the matrix or the IO MUX gives it */ +int esk_esp32_signal_in(struct esk_mach *m, int sig); + +/* the flash chip (spi.c) */ +struct esk_esp32_nor; +struct esk_esp32_nor *esk_esp32_nor_of(struct esk_mach *m); +struct esk_esp32_nor *esk_esp32_nor_create(struct esk_mach *m); +void esk_esp32_nor_power_on(struct esk_esp32_nor *f); +int esk_esp32_nor_busy(struct esk_esp32_nor *f); +/* one transaction: `ntx` bytes the chip receives (the instruction first), + * then `nrx` bytes it answers with */ +void esk_esp32_nor_xfer(struct esk_esp32_nor *f, const u8 *tx, int ntx, u8 *rx, int nrx); +#endif diff --git a/core/mcu/esp32/soc/gpio.c b/core/mcu/esp32/soc/gpio.c new file mode 100644 index 000000000..cbd07fb86 --- /dev/null +++ b/core/mcu/esp32/soc/gpio.c @@ -0,0 +1,534 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* gpio.c -- the ESP32's GPIO matrix and IO MUX (TRM v5 chapter 4, + * "IO_MUX and GPIO Matrix"; ESP32 Series Datasheet's pin tables) on its 34 + * pads GPIO0-19, 21-23, 25-27 and 32-39 (the runtime's port n / 16, bit + * n % 16). The ESP32-C3's model (mcu/esp32c3/gpio.c) on the ESP32's + * registers. + * + * Each pad's IO_MUX register picks its function (MCU_SEL): function 2 is + * the GPIO matrix on every pad, and so is function 0 on the pads whose + * first function is their GPIO; GPIO1's function 0 is U0TXD and GPIO3's + * U0RXD, directly; GPIO6-11 (the module's flash) and the JTAG pads + * (GPIO12-15) leave the pad to their functions, which no model drives. + * - Through the matrix, GPIO_FUNCn_OUT_SEL_CFG's OUT_SEL names the pad's + * output: 256 is GPIO_OUT's (OUT1's) bit, with GPIO_ENABLE's + * (ENABLE1's) as its enable; a peripheral signal (TRM table 4-2) is + * that signal, its enable the peripheral's (1 for the UARTs' TXD, RTS + * and DTR) unless OEN_SEL takes GPIO_ENABLE's; INV_SEL and OEN_INV_SEL + * invert them. A peripheral's model sets its signals' levels and + * enables (esk_esp32_signal); a signal no model drives leaves the pad + * undriven. GPIO34-39 have no output driver. + * - GPIO_PINn's PAD_DRIVER makes the output open-drain; FUN_WPU and + * FUN_WPD pull the pad; FUN_IE lets its level into GPIO_IN (IN1), the + * interrupt and the peripherals' inputs. + * - The pad is its output where enabled; else what the board drives; + * else its pull; else 0. + * - A peripheral input (GPIO_FUNCy_IN_SEL_CFG) comes through the matrix + * from IN_SEL's pad (0x38: 1, 0x30: 0, IN_INV_SEL inverting) when SEL + * is set, else directly from the pad whose IO MUX function it is, else + * 0. + * - Interrupts (GPIO_PINn's INT_TYPE: 1 rising, 2 falling, 3 any edge, + * 4 low level, 5 high level; INT_ENA bit 0 the APP_CPU's, 1 its NMI's, + * 2 the PRO_CPU's, 3 its NMI's) set GPIO_STATUS (STATUS1; W1TS and + * W1TC set and clear it; a level sets it again while it lasts); + * PCPU_INT, PCPU_NMI_INT, ACPU_INT and ACPU_NMI_INT (and their *1) are + * the enabled ones; the matrix sources GPIO (22) and GPIO_NMI (23) + * reach each CPU with that CPU's own. + * - GPIO_STRAP latches at a chip reset the boot-mode pins (TRM 4.? and + * the datasheet's strapping table): MTDI (GPIO12) bit 5, GPIO0 bit 4, + * GPIO2 bit 3, GPIO4 bit 2, MTDO (GPIO15) bit 1, GPIO5 bit 0, each + * its reset pull's level when nothing drives it (GPIO0, MTDO, GPIO5 + * up; GPIO2, GPIO4, MTDI down): 0x13, SPI_FAST_FLASH_BOOT; GPIO0 held + * low gives 0x03, the download mode. It keeps them through every other + * reset. + * IO MUX's pads come out of reset as the datasheet's table has them (each + * pad's IE and pull), not with the SVD's one reset value for all. + * Not yet: the peripherals' signals but the UARTs' (a pad routed to one + * is not driven), the RTC IO MUX (RTC_IO's pad functions, its pulls, the + * hold), the input filter, sleep mode (the MCU_ pad bits, SLP_SEL), the + * drive strengths' effect, the pads' wake-up, the SDIO interrupt. */ +#include +#include + +#include "mcu/esp32/soc/esp32.h" + +#define NPIN 40 +#define SIG_U0TXD 14 +#define SIG_U0RTS 15 +#define SIG_U0DTR 16 +#define SIG_U1TXD 17 +#define SIG_U1RTS 18 +#define SIG_U2TXD 198 +#define SIG_U2RTS 199 +#define SIG_GPIO 256 +#define NSIG 256 + +#define MUX_FUN_WPD (1u << 7) +#define MUX_FUN_WPU (1u << 8) +#define MUX_FUN_IE (1u << 9) + +/* the pads that exist */ +#define PADS 0xFF0EFFFFFFull +/* the datasheet's reset column: 0 IE off; 1 IE; 2 IE and WPD; 3 IE and WPU */ +static const u8 reset_kind[NPIN] = { + 3, 3, 2, 3, 2, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 3, 1, 1, 1, 1, + 0, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +/* function 0 is the pad's GPIO */ +static const u8 f0_is_gpio[NPIN] = { + 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1 }; + +struct e32_gpio { + struct esk_mach *s; + struct esk_rf_periph *p, *mux; + struct esk_rf_reg *out, *out1, *enable, *enable1, *strap, *in, *in1, *status, *status1; + struct esk_rf_reg *pcpu, *pnmi, *acpu, *anmi, *pcpu1, *pnmi1, *acpu1, *anmi1; + struct esk_rf_reg *pin[NPIN], *fout[NPIN], *fin[NSIG], *iomux[NPIN]; + u32 latched; + int have, known, busy, irq[2], irq_nmi[2]; + u64 level, input; + esk_mach_pin cfg[NPIN]; + u8 sig_on[NSIG], sig_lv[NSIG], sig_oe[NSIG]; + int again; +}; + +static u32 reg(const struct esk_rf_reg *r) { return r ? (u32)r->value : 0; } + +static int pad(int n) { return n >= 0 && n < NPIN && ((PADS >> n) & 1u); } + +static struct e32_gpio *gpio_of(struct esk_mach *m) +{ + return m->rf ? (struct e32_gpio *)esk_rf_ctx_of(m->rf, &esk_esp32_gpio_ops) : 0; +} + +static u64 out64(const struct e32_gpio *k) { return (u64)reg(k->out) | (u64)reg(k->out1) << 32; } +static u64 en64(const struct e32_gpio *k) { return (u64)reg(k->enable) | (u64)reg(k->enable1) << 32; } + +/* the pad's IO MUX function: 2 the matrix (also function 0 of the pads + * whose function 0 is their GPIO), else its own */ +static u32 mux_sel(const struct e32_gpio *k, int n) +{ + u32 sel = (reg(k->iomux[n]) >> 12) & 7u; + return sel == 0 && f0_is_gpio[n] ? 2u : sel; +} + +static int signal_out(const struct e32_gpio *k, int sig, int *level, int *oe) +{ + if (sig >= 0 && sig < NSIG && k->sig_on[sig]) { + *level = k->sig_lv[sig]; + *oe = k->sig_oe[sig]; + return 1; + } + switch (sig) { + case SIG_U0TXD: case SIG_U1TXD: case SIG_U2TXD: /* idle high: the frames are the runtime's */ + case SIG_U0RTS: case SIG_U0DTR: case SIG_U1RTS: case SIG_U2RTS: + *level = 1; + *oe = 1; + return 1; + default: + return 0; + } +} + +static int pin_out(const struct e32_gpio *k, int n, int *level, int *oe, int *af) +{ + u32 sel = mux_sel(k, n); + *af = 0; + if (n >= 34) + return 0; /* input only */ + if (sel == 2) { + u32 f = reg(k->fout[n]), sig = f & 0x1ffu; + int lv = 0, en = 0; + if (sig == SIG_GPIO) { + lv = (int)(out64(k) >> n & 1u); + en = (int)(en64(k) >> n & 1u); + } else { + if (!signal_out(k, (int)sig, &lv, &en)) + return 0; + *af = 1; + if (f & (1u << 10)) + en = (int)(en64(k) >> n & 1u); + } + if (f & (1u << 9)) + lv = !lv; + if (f & (1u << 11)) + en = !en; + *level = lv; + *oe = en; + return 1; + } + if (sel == 0 && n == 1) { /* U0TXD */ + *level = 1; + *oe = 1; + *af = 1; + return 1; + } + return 0; +} + +static void irqs(struct e32_gpio *k, u64 rise, u64 fall) +{ + u64 st = (u64)reg(k->status) | (u64)reg(k->status1) << 32, ints[4] = { 0, 0, 0, 0 }; + int n, c; + for (n = 0; n < NPIN; n++) { + u32 pr, type, ena; + int in, hit; + if (!pad(n)) + continue; + pr = reg(k->pin[n]); + type = (pr >> 7) & 7u; + ena = (pr >> 13) & 0x1fu; + in = (int)(k->input >> n & 1u); + hit = (type == 1 && (rise >> n & 1u)) || (type == 2 && (fall >> n & 1u)) || + (type == 3 && ((rise | fall) >> n & 1u)) || (type == 4 && !in) || (type == 5 && in); + if (hit) + st |= 1ull << n; + if (type && (st >> n & 1u)) + for (c = 0; c < 4; c++) + if (ena & (1u << c)) + ints[c] |= 1ull << n; + } + esk_rf_hw(k->status, (u32)st); + esk_rf_hw(k->status1, (u32)(st >> 32) & 0xffu); + esk_rf_hw(k->acpu, (u32)ints[0]); + esk_rf_hw(k->anmi, (u32)ints[1]); + esk_rf_hw(k->pcpu, (u32)ints[2]); + esk_rf_hw(k->pnmi, (u32)ints[3]); + if (k->acpu1) { + esk_rf_hw(k->acpu1, (u32)(ints[0] >> 32)); + esk_rf_hw(k->anmi1, (u32)(ints[1] >> 32)); + esk_rf_hw(k->pcpu1, (u32)(ints[2] >> 32)); + esk_rf_hw(k->pnmi1, (u32)(ints[3] >> 32)); + } + for (c = 0; c < 2; c++) { + int cpu_int = ints[c ? 0 : 2] != 0, cpu_nmi = ints[c ? 1 : 3] != 0; + if (cpu_int != k->irq[c]) { + k->irq[c] = cpu_int; + esk_esp32_source_cpu(k->s, c, 22, cpu_int); + } + if (cpu_nmi != k->irq_nmi[c]) { + k->irq_nmi[c] = cpu_nmi; + esk_esp32_source_cpu(k->s, c, 23, cpu_nmi); + } + } +} + +/* the pads the matrix gives a UART's RX: the runtime reads their frames */ +static u64 uart_rx_pins(const struct e32_gpio *k) +{ + static const int sig[3] = { 14, 17, 198 }; + u64 m = 0; + int i; + for (i = 0; i < 3; i++) { + u32 f = reg(k->fin[sig[i]]), n = f & 0x3fu; + if ((f & (1u << 7)) && n < NPIN) + m |= 1ull << n; + } + return m; +} + +static void settle(struct e32_gpio *k) +{ + struct esk_mach *s = k->s; + u64 lvl = 0, in = 0, rise, fall, rx; + int n; + if (k->busy) { + k->again = 1; + return; + } + k->busy = 1; +again: + k->again = 0; + rx = uart_rx_pins(k); + for (n = 0; n < NPIN; n++) { + u32 mux; + int level = 0, oe = 0, af = 0, drive, ext = 0, pin, wpu, wpd, od; + esk_mach_pin o; + if (!pad(n)) + continue; + mux = reg(k->iomux[n]); + wpu = (mux & MUX_FUN_WPU) != 0; + wpd = (mux & MUX_FUN_WPD) != 0; + od = (reg(k->pin[n]) & (1u << 2)) != 0; + if (!pin_out(k, n, &level, &oe, &af)) + oe = 0; + drive = oe && !(od && level); + memset(&o, 0, sizeof o); + o.drive = oe ? level : -1; + o.open_drain = od; + o.pull = wpu && !wpd ? 1 : wpd && !wpu ? 2 : 0; + o.af = af || (mux_sel(k, n) == 0 && n == 3) /* U0RXD */ || (rx >> n & 1u); + o.analog = !(mux & MUX_FUN_IE) && !oe; + if (s->host.pin_cfg && (!k->known || memcmp(&k->cfg[n], &o, sizeof o) != 0)) + s->host.pin_cfg(s->host.ctx, n / 16, n % 16, &o); + k->cfg[n] = o; + if (drive) + pin = level; + else if (s->host.pin_in && s->host.pin_in(s->host.ctx, n / 16, n % 16, &ext)) + pin = ext != 0; + else + pin = wpu ? 1 : 0; + lvl |= (u64)pin << n; + if (mux & MUX_FUN_IE) + in |= (u64)pin << n; + } + rise = k->known ? in & ~k->input : 0; + fall = k->known ? ~in & k->input : 0; + k->level = lvl; + k->input = in; + k->known = 1; + esk_rf_hw(k->in, (u32)in); + esk_rf_hw(k->in1, (u32)(in >> 32) & 0xffu); + irqs(k, rise, fall); + if (k->again) + goto again; + k->busy = 0; +} + +void esk_esp32_signal(struct esk_mach *m, int sig, int level, int oe) +{ + struct e32_gpio *k = gpio_of(m); + u8 lv = (u8)(level != 0), en = (u8)(oe != 0); + if (!k || sig < 0 || sig >= NSIG) + return; + if (k->sig_on[sig] && k->sig_lv[sig] == lv && k->sig_oe[sig] == en) + return; + k->sig_on[sig] = 1; + k->sig_lv[sig] = lv; + k->sig_oe[sig] = en; + if (k->known) + settle(k); +} + +int esk_esp32_signal_in(struct esk_mach *m, int sig) +{ + struct e32_gpio *k = gpio_of(m); + u32 f; + if (!k || sig < 0 || sig >= NSIG) + return 0; + f = reg(k->fin[sig]); + if (f & (1u << 7)) { + u32 n = f & 0x3fu; + int v = n == 0x38u ? 1 : n == 0x30u ? 0 : n < NPIN ? (int)(k->input >> n & 1u) : 0; + return (f & (1u << 6)) ? !v : v; + } + if (sig == 14 && mux_sel(k, 3) == 0) /* U0RXD */ + return (int)(k->input >> 3 & 1u); + return 0; +} + +void esk_esp32_pins_changed(struct esk_mach *m) +{ + struct e32_gpio *k = gpio_of(m); + if (k) + settle(k); +} + +int esk_esp32_uart_pin(struct esk_mach *m, const char *unit, int tx, int *port, int *bit) +{ + static const int txs[3] = { SIG_U0TXD, SIG_U1TXD, SIG_U2TXD }, rxs[3] = { 14, 17, 198 }; + struct e32_gpio *k = gpio_of(m); + int u, n; + if (!k || strncmp(unit, "UART", 4) || unit[4] < '0' || unit[4] > '2' || unit[5]) + return -1; + u = unit[4] - '0'; + if (tx) { + for (n = 0; n < 34; n++) { + u32 sel; + if (!pad(n)) + continue; + sel = mux_sel(k, n); + if ((sel == 2 && (int)(reg(k->fout[n]) & 0x1ffu) == txs[u]) || (u == 0 && sel == 0 && n == 1)) { + *port = n / 16; + *bit = n % 16; + return 0; + } + } + return -1; + } + { + u32 f = reg(k->fin[rxs[u]]); + if (f & (1u << 7)) { + n = (int)(f & 0x3fu); + if (!pad(n)) + return -1; + } else if (u == 0 && mux_sel(k, 3) == 0) { + n = 3; + } else { + return -1; + } + *port = n / 16; + *bit = n % 16; + return 0; + } +} + +u32 esk_esp32_strap(struct esk_mach *m) +{ + struct e32_gpio *k = gpio_of(m); + return k ? k->latched : 0x13u; +} + +/* ---- the GPIO block ---------------------------------------------------- */ + +static u32 gp_read(void *ctx, u32 off, int n) +{ + struct e32_gpio *k = (struct e32_gpio *)ctx; + return esk_rf_read(k->p, off, n); +} + +static void set_clr(struct esk_rf_reg *r, int set, u32 v, u32 mask) +{ + esk_rf_hw(r, set ? reg(r) | (v & mask) : reg(r) & ~v); +} + +static void gp_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_gpio *k = (struct e32_gpio *)ctx; + const u32 lo = (u32)PADS, hi = (u32)(PADS >> 32) & 0xffu; + switch (off) { + case 0x38: case 0x3C: case 0x40: case 0x60: case 0x64: case 0x68: case 0x6C: + return; /* read-only */ + case 0x08: case 0x0C: set_clr(k->out, off == 0x08, v, lo); break; + case 0x14: case 0x18: set_clr(k->out1, off == 0x14, v, hi); break; + case 0x24: case 0x28: set_clr(k->enable, off == 0x24, v, lo); break; + case 0x30: case 0x34: set_clr(k->enable1, off == 0x30, v, hi); break; + case 0x48: case 0x4C: set_clr(k->status, off == 0x48, v, lo); break; + case 0x54: case 0x58: set_clr(k->status1, off == 0x54, v, hi); break; + default: + esk_rf_write(k->p, off, n, v); + } + settle(k); +} + +static int pin_level(struct e32_gpio *k, int gpio, int dflt) +{ + int level = dflt; + if (k->s->host.pin_in && k->s->host.pin_in(k->s->host.ctx, gpio / 16, gpio % 16, &level)) + return level != 0; + return dflt; +} + +static void gp_reset(void *ctx) +{ + struct e32_gpio *k = (struct e32_gpio *)ctx; + int c; + if (!k->have || k->s->reset_cause == ESK_RESET_POWER || k->s->reset_cause == ESK_RESET_PIN) { + k->latched = (u32)pin_level(k, 12, 0) << 5 | (u32)pin_level(k, 0, 1) << 4 | + (u32)pin_level(k, 2, 0) << 3 | (u32)pin_level(k, 4, 0) << 2 | + (u32)pin_level(k, 15, 1) << 1 | (u32)pin_level(k, 5, 1); + k->have = 1; + } + esk_rf_hw(k->strap, k->latched); + for (c = 0; c < 2; c++) { + k->irq[c] = k->irq_nmi[c] = 0; + esk_esp32_source_cpu(k->s, c, 22, 0); + esk_esp32_source_cpu(k->s, c, 23, 0); + } + k->known = 0; + settle(k); +} + +const struct esk_dev_ops esk_esp32_gpio_ops = { + "esp32-gpio", gp_read, gp_write, gp_reset, 0, 0, +}; + +/* ---- IO MUX ------------------------------------------------------------ */ + +static u32 mx_read(void *ctx, u32 off, int n) +{ + struct esk_rf_periph *p = (struct esk_rf_periph *)ctx; + return esk_rf_read(p, off, n); +} + +static void mx_write(void *ctx, u32 off, int n, u32 v) +{ + struct esk_rf_periph *p = (struct esk_rf_periph *)ctx; + esk_rf_write(p, off, n, v); + esk_esp32_pins_changed(p->sim); +} + +static void mx_reset(void *ctx) +{ + struct esk_rf_periph *p = (struct esk_rf_periph *)ctx; + char name[16]; + int i; + for (i = 0; i < NPIN; i++) { + struct esk_rf_reg *r; + u32 v = 2u << 10; /* FUN_DRV 2 */ + snprintf(name, sizeof name, "GPIO%d", i); + r = esk_rf_reg(p, name); + if (!r || !pad(i)) + continue; + switch (reset_kind[i]) { + case 1: v |= MUX_FUN_IE; break; + case 2: v |= MUX_FUN_IE | MUX_FUN_WPD; break; + case 3: v |= MUX_FUN_IE | MUX_FUN_WPU; break; + default: break; + } + esk_rf_hw(r, v); + } + esk_esp32_pins_changed(p->sim); +} + +const struct esk_dev_ops esk_esp32_iomux_ops = { + "esp32-iomux", mx_read, mx_write, mx_reset, 0, 0, +}; + +void *esk_esp32_iomux_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + ES_UNUSED(s); + return esk_rf_reg(p, "GPIO39") ? p : 0; +} + +void *esk_esp32_gpio_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_gpio *k = (struct e32_gpio *)esk_mach_alloc(s, sizeof *k); + char name[32]; + int i; + if (!k) + return 0; + k->s = s; + k->p = p; + k->mux = esk_rf_periph(s->rf, "IO_MUX"); + k->out = esk_rf_reg(p, "OUT"); + k->out1 = esk_rf_reg(p, "OUT1"); + k->enable = esk_rf_reg(p, "ENABLE"); + k->enable1 = esk_rf_reg(p, "ENABLE1"); + k->strap = esk_rf_reg(p, "STRAP"); + k->in = esk_rf_reg(p, "IN"); + k->in1 = esk_rf_reg(p, "IN1"); + k->status = esk_rf_reg(p, "STATUS"); + k->status1 = esk_rf_reg(p, "STATUS1"); + k->acpu = esk_rf_reg(p, "ACPU_INT"); + k->anmi = esk_rf_reg(p, "ACPU_NMI_INT"); + k->pcpu = esk_rf_reg(p, "PCPU_INT"); + k->pnmi = esk_rf_reg(p, "PCPU_NMI_INT"); + k->acpu1 = esk_rf_reg(p, "ACPU_INT1"); + k->anmi1 = esk_rf_reg(p, "ACPU_NMI_INT1"); + k->pcpu1 = esk_rf_reg(p, "PCPU_INT1"); + k->pnmi1 = esk_rf_reg(p, "PCPU_NMI_INT1"); + if (!k->mux || !k->out || !k->out1 || !k->enable || !k->enable1 || !k->strap || !k->in || !k->in1 || + !k->status || !k->status1 || !k->acpu || !k->anmi || !k->pcpu || !k->pnmi) + return 0; + for (i = 0; i < NPIN; i++) { + if (!pad(i)) + continue; + snprintf(name, sizeof name, "PIN%d", i); + k->pin[i] = esk_rf_reg(p, name); + snprintf(name, sizeof name, "FUNC%d_OUT_SEL_CFG", i); + k->fout[i] = esk_rf_reg(p, name); + snprintf(name, sizeof name, "GPIO%d", i); + k->iomux[i] = esk_rf_reg(k->mux, name); + if (!k->pin[i] || !k->fout[i] || !k->iomux[i]) + return 0; + } + for (i = 0; i < NSIG; i++) { + snprintf(name, sizeof name, "FUNC%d_IN_SEL_CFG", i); + k->fin[i] = esk_rf_reg(p, name); + } + s->pins_changed = esk_esp32_pins_changed; + s->uart_pin = esk_esp32_uart_pin; + return k; +} diff --git a/core/mcu/esp32/soc/misc.c b/core/mcu/esp32/soc/misc.c new file mode 100644 index 000000000..18cd14be0 --- /dev/null +++ b/core/mcu/esp32/soc/misc.c @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* misc.c -- what the ESP32 answers outside its register description: + * + * - the random number generator's RNG_DATA (TRM v5 chapter 26) at + * 0x3FF75144: every read a new 32-bit number. The chip's numbers come + * from the noise of its RF and SAR ADC circuits; the model's from a + * generator (xorshift64* seeded by the chip's MAC), the same sequence + * every run so a run replays, another for each chip; + * - the peripherals' AHB view (TRM 3.1.4): 0x60000000-0x6003FFFF reaches + * the same registers as 0x3FF40000-0x3FF7FFFF (ESP-IDF reads UART FIFOs + * there). Inside, the access is passed to the bus at the DPORT address. */ +#include "mcu/esp32/soc/esp32.h" + +#define RNG_DATA 0x3FF75144u +#define AHB_BASE 0x60000000u +#define AHB_SIZE 0x40000u +#define DPORT_VIEW 0x3FF40000u + +struct e32_rng { + struct esk_mach *s; + u64 state; + int seeded; +}; + +static u32 rng_next(struct e32_rng *k) +{ + if (!k->seeded) { + int i; + k->seeded = 1; + if (k->s->has_factory_mac) + for (i = 0; i < 6; i++) + k->state = (k->state ^ k->s->factory_mac[i]) * 0x100000001B3ull; + if (!k->state) + k->state = 1; + } + k->state ^= k->state >> 12; + k->state ^= k->state << 25; + k->state ^= k->state >> 27; + return (u32)((k->state * 0x2545F4914F6CDD1Dull) >> 32); +} + +static u32 rng_read(void *ctx, u32 off, int n) +{ + ES_UNUSED(n); + return rng_next((struct e32_rng *)ctx) >> (8 * (off & 3u)); +} + +static void rng_write(void *ctx, u32 off, int n, u32 v) +{ + ES_UNUSED(ctx); + ES_UNUSED(off); + ES_UNUSED(n); + ES_UNUSED(v); +} + +const struct esk_dev_ops esk_esp32_rng_ops = { + "esp32-rng", rng_read, rng_write, 0, 0, 0, +}; + +static u32 ahb_read(void *ctx, u32 off, int n) +{ + struct esk_mach *s = (struct esk_mach *)ctx; + u32 v = 0; + if (esk_bus_read(&s->bus, DPORT_VIEW + off, n, &v)) + esk_bus_fault(&s->bus); + return v; +} + +static void ahb_write(void *ctx, u32 off, int n, u32 v) +{ + struct esk_mach *s = (struct esk_mach *)ctx; + if (esk_bus_write(&s->bus, DPORT_VIEW + off, n, v)) + esk_bus_fault(&s->bus); +} + +static const struct esk_dev_ops ahb_ops = { + "esp32-ahb", ahb_read, ahb_write, 0, 0, 0, +}; + +/* the RNG and the AHB view: 0, or -1 */ +int esk_esp32_misc_add(struct esk_mach *s) +{ + struct e32_rng *k = (struct e32_rng *)esk_mach_alloc(s, sizeof *k); + if (!k) + return -1; + k->s = s; + k->state = 0x456D6253696D0032ull; + if (esk_mach_add_dev(s, RNG_DATA, 4, &esk_esp32_rng_ops, k) != ES_OK || + esk_mach_add_dev(s, AHB_BASE, AHB_SIZE, &ahb_ops, s) != ES_OK) + return -1; + return 0; +} diff --git a/core/mcu/esp32/soc/nor.c b/core/mcu/esp32/soc/nor.c new file mode 100644 index 000000000..dee39cc21 --- /dev/null +++ b/core/mcu/esp32/soc/nor.c @@ -0,0 +1,365 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* nor.c -- the module's 4 MB SPI flash: a Giantec GT25Q32A-U (datasheet + * V2.5, section 9; JEDEC ID C4 60 16, the ID esptool reads on the owner's + * ESP32 board, docs/engineering/esp32-giantec-profile.md), what SPI0 and + * SPI1 (spi.c) see of it. Its bytes are the description's `flash` store, + * which keeps them through every reset. The instruction set is the + * ESP32-C3's XMC model's (mcu/esp32c3/nor.c), which the GT25Q32A shares: + * - Write Enable (06h), Volatile SR Write Enable (50h), Write Disable + * (04h); Read Status Register-1, -2, -3 (05h, 35h, 15h); Write Status + * Register-1 (01h, and -2 after it), -2 (31h), -3 (11h); + * - Read Data (03h), Fast Read (0Bh), Dual Output (3Bh), Quad Output + * (6Bh), Dual I/O (BBh), Quad I/O (EBh), Word Read Quad I/O (E7h): the + * quad ones need QE (S9); + * - Page Program (02h), Quad Page Program (32h), Sector Erase (20h), + * Block Erase (52h, D8h), Chip Erase (C7h, 60h), each needing WEL; + * - the three Security Registers (44h, 42h, 48h), Suspend (75h) and + * Resume (7Ah), Power-down (B9h) and Release (ABh: device ID 15h), + * Manufacturer/Device ID (90h: C4h 15h), JEDEC ID (9Fh: C4 60 16), + * Unique ID (4Bh), Enable Reset and Reset (66h, 99h). + * Busy times are the datasheet's maximums as the owner's profile records + * them (a one-byte program 150 us, a page 1.5 ms, a 4, 32 or 64 KB erase + * 8 ms, the chip 16 ms; a status write taken as an erase's), counted on the + * machine's clock. It ships with QE clear: a QIO image's bootloader sets + * it (bootloader_enable_qio_mode), as on the part. + * Not yet: QPI mode, burst wrap, the continuous read mode, SFDP (5Ah + * answers FFh), the block protection bits (kept, protecting nothing). */ +#include + +#include "mcu/esp32/soc/esp32.h" + +#define PAGE 256u +#define NOR_DEVICE_ID 0x15u +#define T_W_PS 8000000000ull /* 8 ms */ +#define T_BP_PS 150000000ull /* 150 us: a one-byte program */ +#define T_PP_PS 1500000000ull /* 1.5 ms */ +#define T_SE_PS 8000000000ull /* 8 ms */ +#define T_BE1_PS 8000000000ull /* 8 ms */ +#define T_BE2_PS 8000000000ull /* 8 ms */ +#define T_CE_PS 16000000000ull /* 16 ms */ + +#define SR1_BUSY 0x01u +#define SR1_WEL 0x02u +#define SR2_QE 0x02u +#define SR2_LB_SHIFT 3 +#define SR2_SUS 0x80u + +static const u8 unique_id[8] = { 0x45, 0x6d, 0x62, 0x53, 0x69, 0x6d, 0x00, 0x03 }; + +struct esk_esp32_nor { + struct esk_mach *m; + struct esk_store *st; + u8 sr[3]; /* the status registers as read */ + u8 sr_nv[3]; /* their non-volatile values */ + int vwe; /* 50h: the next status write is volatile */ + int pd, udpd; /* power-down, ultra-deep power-down */ + int reset_en; /* 66h was the last instruction */ + u64 now_ps, last_cycles; + u64 busy_end; /* the self-timed operation ends then (ps) */ + u64 sus_left; /* a suspended operation's remaining time */ + u8 sec[3][256]; +}; + +static u64 now_ps(struct esk_esp32_nor *f) +{ + u32 hz = esk_mach_core_hz(f->m); + u64 dc = f->m->cycles - f->last_cycles; + f->last_cycles = f->m->cycles; + if (hz) + f->now_ps += (u64)((double)dc * 1e12 / (double)hz); + return f->now_ps; +} + +static void sr_clear(struct esk_esp32_nor *f, int k, u32 bits) +{ + f->sr[k] = (u8)(f->sr[k] & ~bits); +} +static void sr_set(struct esk_esp32_nor *f, int k, u32 bits) +{ + f->sr[k] = (u8)(f->sr[k] | bits); +} + +static int busy(struct esk_esp32_nor *f) +{ + if ((f->sr[0] & SR1_BUSY) && now_ps(f) >= f->busy_end) { + sr_clear(f, 0, SR1_BUSY | SR1_WEL); + } + return (f->sr[0] & SR1_BUSY) != 0; +} + +static void start(struct esk_esp32_nor *f, u64 ps) +{ + sr_set(f, 0, SR1_BUSY); + f->busy_end = now_ps(f) + ps; +} + +static u32 addr24(const u8 *tx, int n) +{ + u32 a = 0; + int i; + for (i = 1; i <= 3; i++) + a = a << 8 | (i < n ? tx[i] : 0xffu); + return a; +} + +static void program(struct esk_esp32_nor *f, u32 a, const u8 *d, int n) +{ + u32 page = a & ~(PAGE - 1u), off = a & (PAGE - 1u); + int i; + for (i = 0; i < n; i++) { + u32 x = (page + ((off + (u32)i) & (PAGE - 1u))) % f->st->size; + f->st->mem[x] = (u8)(f->st->mem[x] & d[i]); + } + esk_esp32_flash_written(f->m, page % f->st->size, PAGE); +} + +static void erase(struct esk_esp32_nor *f, u32 a, u32 size) +{ + u32 base = (a & ~(size - 1u)) % f->st->size; + memset(f->st->mem + base, 0xff, size); + esk_esp32_flash_written(f->m, base, size); +} + +/* the security register an address names (0x1000, 0x2000, 0x3000), or -1 */ +static int sec_reg(u32 a) +{ + u32 r = a >> 12; + return (a >> 16) == 0 && (a & 0xf00u) == 0 && r >= 1 && r <= 3 ? (int)r - 1 : -1; +} + +static void write_sr(struct esk_esp32_nor *f, int k, u8 v) +{ + static const u8 writable[3] = { 0xfc, 0x7b, 0xe4 }; + u8 w = writable[k]; + if (k == 1) { + /* LB3-1 are one-time programmable: once set they stay */ + v = (u8)(v | (f->sr[1] & (7u << SR2_LB_SHIFT))); + } + f->sr[k] = (u8)((f->sr[k] & ~w) | (v & w)); + if (!f->vwe) + f->sr_nv[k] = (u8)((f->sr_nv[k] & ~w) | (v & w)); +} + +static void reset_device(struct esk_esp32_nor *f) +{ + memcpy(f->sr, f->sr_nv, sizeof f->sr); + sr_clear(f, 0, SR1_BUSY | SR1_WEL); + sr_clear(f, 1, SR2_SUS); + f->sus_left = 0; + f->vwe = 0; +} + +static int is_read_status(u8 op) +{ + return op == 0x05 || op == 0x35 || op == 0x15; +} + +void esk_esp32_nor_xfer(struct esk_esp32_nor *f, const u8 *tx, int ntx, u8 *rx, int nrx) +{ + u8 op; + u32 a; + int i, qe, sr; + memset(rx, 0xff, (size_t)nrx); + if (f->udpd) { + f->udpd = 0; /* any /CS pulse brings it out (7.2.40) */ + return; + } + if (ntx < 1) + return; + op = tx[0]; + if (f->pd) { + if (op == 0x79 && !busy(f)) { + f->udpd = 1; + return; + } + if (op != 0xab) + return; + } + if (busy(f) && !is_read_status(op) && op != 0x75 && op != 0x66 && op != 0x99) + return; + if (op != 0x99) + f->reset_en = op == 0x66; + qe = (f->sr[1] & SR2_QE) != 0; + a = addr24(tx, ntx); + switch (op) { + case 0x06: /* write enable */ + sr_set(f, 0, SR1_WEL); + f->vwe = 0; + break; + case 0x50: + f->vwe = 1; + break; + case 0x04: + sr_clear(f, 0, SR1_WEL); + f->vwe = 0; + break; + case 0x05: + case 0x35: + case 0x15: + sr = op == 0x05 ? 0 : op == 0x35 ? 1 : 2; + busy(f); + for (i = 0; i < nrx; i++) + rx[i] = f->sr[sr]; + break; + case 0x01: + case 0x31: + case 0x11: + if (!f->vwe && !(f->sr[0] & SR1_WEL)) + break; + if (ntx < 2) + break; + sr = op == 0x01 ? 0 : op == 0x31 ? 1 : 2; + write_sr(f, sr, tx[1]); + if (op == 0x01 && ntx >= 3) + write_sr(f, 1, tx[2]); + if (f->vwe) + f->vwe = 0; + else + start(f, T_W_PS); /* WEL clears as the cycle ends */ + break; + case 0x6b: + case 0xeb: + case 0xe7: + if (!qe) + break; + /* fall through */ + case 0x03: + case 0x0b: + case 0x3b: + case 0xbb: + for (i = 0; i < nrx; i++) + rx[i] = f->st->mem[(a + (u32)i) % f->st->size]; + break; + case 0x32: + if (!qe) + break; + /* fall through */ + case 0x02: + if (!(f->sr[0] & SR1_WEL) || ntx < 5) + break; + program(f, a, tx + 4, ntx - 4); + start(f, ntx - 4 == 1 ? T_BP_PS : T_PP_PS); + break; + case 0x20: + case 0x52: + case 0xd8: + if (!(f->sr[0] & SR1_WEL) || ntx < 4) + break; + erase(f, a, op == 0x20 ? 4096u : op == 0x52 ? 32768u : 65536u); + start(f, op == 0x20 ? T_SE_PS : op == 0x52 ? T_BE1_PS : T_BE2_PS); + break; + case 0xc7: + case 0x60: + if (!(f->sr[0] & SR1_WEL)) + break; + erase(f, 0, f->st->size); + start(f, T_CE_PS); + break; + case 0x44: + case 0x42: + sr = sec_reg(a); + if (!(f->sr[0] & SR1_WEL) || ntx < 4 || sr < 0 || ((f->sr[1] >> (SR2_LB_SHIFT + sr)) & 1)) { + sr_clear(f, 0, SR1_WEL); + break; + } + if (op == 0x44) { + memset(f->sec[sr], 0xff, 256); + start(f, T_SE_PS); + } else { + for (i = 4; i < ntx; i++) + f->sec[sr][(a + (u32)(i - 4)) & 0xffu] = + (u8)(f->sec[sr][(a + (u32)(i - 4)) & 0xffu] & tx[i]); + start(f, T_PP_PS); + } + break; + case 0x48: + sr = sec_reg(a); + for (i = 0; sr >= 0 && i < nrx; i++) + rx[i] = (u8)((a & 0xffu) + (u32)i < 256u ? f->sec[sr][(a & 0xffu) + (u32)i] : 0xffu); + break; + case 0x75: /* suspend */ + if (busy(f)) { + f->sus_left = f->busy_end - now_ps(f); + sr_clear(f, 0, SR1_BUSY); + sr_set(f, 1, SR2_SUS); + } + break; + case 0x7a: /* resume */ + if (f->sr[1] & SR2_SUS) { + sr_clear(f, 1, SR2_SUS); + start(f, f->sus_left); + f->sus_left = 0; + } + break; + case 0xb9: + f->pd = 1; + break; + case 0xab: + /* the ID after three dummy bytes, repeated: sent as an address or + * counted as dummy clocks, the bytes read are the ID */ + f->pd = 0; + for (i = 0; i < nrx; i++) + rx[i] = NOR_DEVICE_ID; + break; + case 0x90: + case 0x92: + case 0x94: + if (op == 0x94 && !qe) + break; + for (i = 0; i < nrx; i++) + rx[i] = (u8)(((u32)i & 1u) == (a & 1u) ? 0xC4u : NOR_DEVICE_ID); + break; + case 0x9f: + for (i = 0; i < nrx && i < 3; i++) + rx[i] = (u8)(0xC46016u >> (16 - 8 * i)); + break; + case 0x4b: + for (i = 0; i < nrx && i < 8; i++) + rx[i] = unique_id[i]; + break; + case 0x99: + if (f->reset_en) + reset_device(f); + f->reset_en = 0; + break; + default: + break; + } +} + +int esk_esp32_nor_busy(struct esk_esp32_nor *f) +{ + return busy(f); +} + +struct esk_esp32_nor *esk_esp32_nor_create(struct esk_mach *m) +{ + struct esk_esp32_nor *f; + struct esk_store *st = esk_mach_store(m, "flash"); + if (!st || st->size == 0 || (st->size & (st->size - 1u))) + return 0; + f = (struct esk_esp32_nor *)esk_mach_alloc(m, sizeof *f); + if (!f) + return 0; + memset(f, 0, sizeof *f); + f->m = m; + f->st = st; + /* as shipped: no protection, QE 0 (the "G" ordering code), driver + * strength 25% (DRV1-0 = 11b), /HOLD (HOLD/RST 0) */ + f->sr_nv[2] = 0x60; + memcpy(f->sr, f->sr_nv, sizeof f->sr); + memset(f->sec, 0xff, sizeof f->sec); + f->last_cycles = m->cycles; + return f; +} + +/* a power-on: the volatile state from the non-volatile bits (the array, the + * status registers' non-volatile bits and the security registers stay) */ +void esk_esp32_nor_power_on(struct esk_esp32_nor *f) +{ + reset_device(f); + f->pd = f->udpd = f->reset_en = 0; + sr_clear(f, 0, SR1_BUSY | SR1_WEL); + f->last_cycles = f->m->cycles; +} diff --git a/core/mcu/esp32/soc/regi2c.c b/core/mcu/esp32/soc/regi2c.c new file mode 100644 index 000000000..93368e859 --- /dev/null +++ b/core/mcu/esp32/soc/regi2c.c @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* regi2c.c -- the ESP32's internal I2C master to its analog blocks, at + * 0x3FF4E000 (0x6000E000 on the AHB view, where the ROM reaches it): the + * bus over which the BBPLL, the APLL, the bias and the regulators are set + * up. The TRM does not describe it; what is modelled is what the boot + * ROM's rom_chip_i2c_readReg and rom_chip_i2c_writeReg (0x40004110, + * 0x40004168) do with it -- the routines ESP-IDF reaches through + * esp_rom_regi2c_* -- and the registers ESP-IDF's soc/regi2c_*.h name. + * The ESP32-C3's model (mcu/esp32c3/regi2c.c) has the same protocol. + * + * - Host n's control register (+4n, n 0-7): the block's address in bits + * 7:0, the register's in 15:8, the data in 23:16, bit 24 for a write, + * bit 25 busy. A write of it reads or writes the block's register at + * once: busy reads 0, and a read's byte is in bits 23:16. + * - ANA_CONFIG (+0x44, ESP-IDF's ANA_CONFIG_REG: the blocks' I2C enables, + * I2C_BBPLL bit 17, I2C_APLL bit 14) and the words up to +0xFFC: kept as + * written. + * - The blocks keep their registers through every reset but a chip's + * (power-on, CHIP_PU): they are analog, outside the digital system. + * Not yet: the registers' reset values (a block's registers read 0 until + * written), the transfers' time, and what the values do (the PLL's + * frequency comes from DPORT's CPU_PER_CONF and RTC_CNTL's SOC_CLK_SEL, + * the regulators' voltages are not modelled). */ +#include + +#include "mcu/esp32/soc/esp32.h" + +#define REGI2C_BASE 0x3FF4E000u +#define REGI2C_SIZE 0x1000u +#define NBLOCKS 16 /* the blocks' addresses are 0x60 to 0x6F */ + +struct e32_regi2c { + struct esk_mach *s; + u32 word[REGI2C_SIZE / 4u]; + u8 reg[NBLOCKS][256]; +}; + +static u8 *block_reg(struct e32_regi2c *k, u32 block, u32 r) +{ + if (block < 0x60u || block >= 0x60u + NBLOCKS) + return 0; + return &k->reg[block - 0x60u][r & 0xffu]; +} + +static void transfer(struct e32_regi2c *k, u32 w, u32 v) +{ + u32 block = v & 0xffu, r = (v >> 8) & 0xffu, data = (v >> 16) & 0xffu; + u8 *p = block_reg(k, block, r); + if (v & 1u << 24) { + if (p) + *p = (u8)data; + k->word[w / 4u] = v & ~(1u << 25); + } else { + data = p ? *p : 0; + k->word[w / 4u] = (v & ~(0xffu << 16 | 1u << 25)) | data << 16; + } +} + +static u32 ri_read(void *ctx, u32 off, int n) +{ + struct e32_regi2c *k = (struct e32_regi2c *)ctx; + ES_UNUSED(n); + return k->word[(off & ~3u) / 4u] >> (8u * (off & 3u)); +} + +static void ri_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_regi2c *k = (struct e32_regi2c *)ctx; + u32 w = off & ~3u, sh = 8u * (off & 3u); + u32 mask = (n >= 4 ? 0xffffffffu : ((1u << (8 * n)) - 1u)) << sh; + v = (k->word[w / 4u] & ~mask) | (v << sh & mask); + if (w < 0x20u) + transfer(k, w, v); + else + k->word[w / 4u] = v; +} + +static void ri_reset(void *ctx) +{ + struct e32_regi2c *k = (struct e32_regi2c *)ctx; + if (k->s->reset_cause == ESK_RESET_POWER || k->s->reset_cause == ESK_RESET_PIN) { + memset(k->word, 0, sizeof k->word); + memset(k->reg, 0, sizeof k->reg); + } + memset(k->word, 0, 0x20u); /* the hosts are idle */ +} + +static const struct esk_dev_ops regi2c_ops = { + "esp32-regi2c", ri_read, ri_write, ri_reset, 0, 0, +}; + +int esk_esp32_regi2c_add(struct esk_mach *s) +{ + struct e32_regi2c *k = (struct e32_regi2c *)esk_mach_alloc(s, sizeof *k); + if (!k) + return -1; + k->s = s; + return esk_mach_add_dev(s, REGI2C_BASE, REGI2C_SIZE, ®i2c_ops, k) == ES_OK ? 0 : -1; +} diff --git a/core/mcu/esp32/soc/rtc.c b/core/mcu/esp32/soc/rtc.c new file mode 100644 index 000000000..021337b7f --- /dev/null +++ b/core/mcu/esp32/soc/rtc.c @@ -0,0 +1,398 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* rtc.c -- the ESP32's RTC_CNTL (TRM v5 chapters 31 and 32): the reset + * causes, the RTC timer, the RTC watchdog (RWDT), the software resets and + * stalls, the clock selection the CPU's clock follows, the store + * registers and the RTC interrupts. + * + * - RESET_STATE's RESET_CAUSE_PROCPU and RESET_CAUSE_APPCPU report each + * CPU's last reset by the TRM's code: 1 POWERON for a chip reset + * (power-on, CHIP_PU), 3 SW_RESET (OPTIONS0.SW_SYS_RST), 12 SW_CPU + * (SW_PROCPU_RST, SW_APPCPU_RST), 9, 13 and 16 the RWDT's system, CPU + * and RTC resets, 7 and 8 the timer groups' watchdogs + * (esk_esp32_reset); the APP_CPU reports 14 (EXT_CPU) while it was + * held by the PRO_CPU (DPORT); + * - the RTC domain keeps its registers through CPU and system resets + * and loses them in a chip or RTC reset; a CPU reset restarts that CPU + * alone (esk_lx6_core_restart); + * - the RTC timer counts RTC_SLOW_CLK (CLK_CONF's ANA_CLK_RTC_SEL: the + * 150 kHz RC oscillator, the 32.768 kHz crystal, 8MD256) from the chip's + * reset; a write of TIME_UPDATE's bit 31 latches it in TIME0 and TIME1 + * and sets TIME_VALID; SLP_TIMER0/1 with MAIN_TIMER_ALARM_EN raise + * MAIN_TIMER when it reaches them; + * - the RWDT counts RTC_SLOW_CLK through four stages (WDT_STGn_HOLD); + * each stage's action is off, an interrupt (WDT), a CPU, system or RTC + * reset; WDT_EN runs it, and so does WDT_FLASHBOOT_MOD_EN (set at a + * chip reset) with stage 0 an RTC reset; WDTFEED returns it to stage + * 0; WDTCONFIG0-4 and WDTFEED take writes only while WDT_WKEY holds + * 0x50D83AA1; + * - a CPU stalls while its SW_STALL_*CPU_C1 (SW_CPU_STALL) is 0x21 and + * its C0 (OPTIONS0) 2; + * - INT_RAW, INT_ST = INT_RAW & INT_ENA, INT_CLR, and the matrix source + * RTC_CORE (46). + * Not modelled: sleep and wake-up (light and deep sleep, the power + * domains, the ULP coprocessor), brown-out, the slow clocks' error (the + * RC oscillator is exactly 150 kHz), the reset pulse widths + * (WDT_*_RESET_LENGTH), STAT_VECTOR_SEL (the cores always start at the + * ROM). */ +#include + +#include "mcu/esp32/soc/esp32.h" +#include "mcu/xtensa/lx6.h" + +#define RC_SLOW_HZ 150000.0 +#define RC_FAST_HZ 8000000.0 +#define WDT_KEY 0x50D83AA1u +#define CFG0_FLASHBOOT (1u << 10) +#define CFG0_EN (1u << 31) +#define INT_WDT (1u << 3) +#define INT_MAIN_TIMER (1u << 8) +#define OPT0_SW_APPCPU_RST (1u << 4) +#define OPT0_SW_PROCPU_RST (1u << 5) +#define OPT0_SW_SYS_RST (1u << 31) + +#define OPTIONS0 0x00u +#define SLP_TIMER0 0x04u +#define SLP_TIMER1 0x08u +#define TIME_UPDATE 0x0Cu +#define TIME0 0x10u +#define TIME1 0x14u +#define RESET_STATE 0x34u +#define INT_ENA 0x3Cu +#define INT_RAW 0x40u +#define INT_ST 0x44u +#define INT_CLR 0x48u +#define CLK_CONF 0x70u +#define WDTCONFIG0 0x8Cu +#define WDTFEED 0xA0u +#define WDTWPROTECT 0xA4u +#define SW_CPU_STALL 0xACu + +enum { ACT_OFF, ACT_INT, ACT_CPU, ACT_SYSTEM, ACT_RTC }; + +struct e32_rtc { + struct esk_mach *s; + struct esk_rf_periph *p; + int code[2]; /* the cause each CPU's next reset reports */ + int level; /* the RTC_CORE source */ + int clocked; + u64 slow, base_cycles; + double frac; + int stage; + u64 wdt_from; +}; + +static struct e32_rtc *rtc_of(struct esk_mach *m) +{ + return m->rf ? (struct e32_rtc *)esk_rf_ctx_of(m->rf, &esk_esp32_rtc_ops) : 0; +} + +static u32 reg(struct e32_rtc *k, u32 off) +{ + struct esk_rf_reg *r = esk_rf_reg_at(k->p, off); + return r ? (u32)r->value : 0; +} + +static void hw(struct e32_rtc *k, u32 off, u32 v) +{ + struct esk_rf_reg *r = esk_rf_reg_at(k->p, off); + if (r) + esk_rf_hw(r, v); +} + +static double slow_hz(struct e32_rtc *k) +{ + switch ((reg(k, CLK_CONF) >> 30) & 3u) { + case 1: + return k->s->lse_hz ? (double)k->s->lse_hz : 32768.0; + case 2: + return RC_FAST_HZ / 256.0; + default: + return RC_SLOW_HZ; + } +} + +u32 esk_esp32_rtc_soc_clk_sel(struct esk_mach *m) +{ + struct e32_rtc *k = rtc_of(m); + return k ? (reg(k, CLK_CONF) >> 27) & 3u : 0; +} + +double esk_esp32_rtc_slow_hz(struct esk_mach *m) +{ + struct e32_rtc *k = rtc_of(m); + return k ? slow_hz(k) : RC_SLOW_HZ; +} + +static void sync(struct e32_rtc *k) +{ + u64 now = k->s->cycles; + double t; + if (now <= k->base_cycles) { + k->base_cycles = now; + return; + } + t = (double)(now - k->base_cycles) * slow_hz(k) / (double)esk_mach_core_hz(k->s) + k->frac; + k->slow += (u64)t; + k->frac = t - (double)(u64)t; + k->base_cycles = now; +} + +static u64 cycles_to(struct e32_rtc *k, u64 n) +{ + double c = ((double)n - k->frac) * (double)esk_mach_core_hz(k->s) / slow_hz(k); + return c <= 1.0 ? 1u : (u64)c + 1u; +} + +static int wdt_on(struct e32_rtc *k) +{ + return (reg(k, WDTCONFIG0) & (CFG0_EN | CFG0_FLASHBOOT)) != 0; +} + +static int stage_action(struct e32_rtc *k, int stage) +{ + u32 c = reg(k, WDTCONFIG0); + if (stage == 0 && (c & CFG0_FLASHBOOT)) + return ACT_RTC; /* flash boot protection */ + return (int)((c >> (28 - 3 * stage)) & 7u); +} + +static u64 stage_hold(struct e32_rtc *k, int stage) +{ + u64 h = reg(k, WDTCONFIG0 + 4u * (u32)(stage + 1)); + return h ? h : 1; +} + +static void update(struct e32_rtc *k) +{ + u32 st = reg(k, INT_RAW) & reg(k, INT_ENA); + hw(k, INT_ST, st); + if ((st != 0) != k->level) { + k->level = st != 0; + esk_esp32_source(k->s, esk_rf_irq(k->p, "RTC_CORE"), k->level); + } +} + +static void clocking(struct e32_rtc *k) +{ + int on = wdt_on(k) || (reg(k, SLP_TIMER1) & (1u << 16)); + esk_rf_clock(k->p, &k->clocked, on); +} + +static void expire(struct e32_rtc *k) +{ + int guard = 4; + if (reg(k, SLP_TIMER1) & (1u << 16)) { + u64 alarm = (u64)reg(k, SLP_TIMER0) | (u64)(reg(k, SLP_TIMER1) & 0xffffu) << 32; + if ((k->slow & 0xffffffffffffull) >= alarm) { + hw(k, INT_RAW, reg(k, INT_RAW) | INT_MAIN_TIMER); + hw(k, SLP_TIMER1, reg(k, SLP_TIMER1) & ~(1u << 16)); + } + } + while (wdt_on(k) && k->slow - k->wdt_from >= stage_hold(k, k->stage) && guard--) { + int act = stage_action(k, k->stage); + k->wdt_from += stage_hold(k, k->stage); + k->stage = (k->stage + 1) & 3; + if (act == ACT_INT) { + hw(k, INT_RAW, reg(k, INT_RAW) | INT_WDT); + } else if (act == ACT_CPU) { + esk_esp32_cpu_reset(k->s, 0, 13); + esk_esp32_cpu_reset(k->s, 1, 13); + break; + } else if (act == ACT_SYSTEM) { + esk_esp32_reset(k->s, 9); + break; + } else if (act == ACT_RTC) { + esk_esp32_reset(k->s, 16); + break; + } + } + update(k); + clocking(k); +} + +static void stalls(struct e32_rtc *k) +{ + u32 o = reg(k, OPTIONS0), c1 = reg(k, SW_CPU_STALL); + esk_lx6_core_stall(k->s, 0, 2, ((o >> 2) & 3u) == 2u && ((c1 >> 26) & 0x3fu) == 0x21u); + esk_lx6_core_stall(k->s, 1, 2, (o & 3u) == 2u && ((c1 >> 20) & 0x3fu) == 0x21u); +} + +static u32 rt_read(void *ctx, u32 off, int n) +{ + struct e32_rtc *k = (struct e32_rtc *)ctx; + sync(k); + return esk_rf_read(k->p, off, n); +} + +static void rt_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_rtc *k = (struct e32_rtc *)ctx; + int keyed = reg(k, WDTWPROTECT) == WDT_KEY; + sync(k); + if (off == WDTFEED) { + if (keyed && (v & (1u << 31))) { + k->stage = 0; + k->wdt_from = k->slow; + } + return; + } + if (off >= WDTCONFIG0 && off <= WDTCONFIG0 + 16u && !keyed) + return; + if (off == INT_CLR) { + hw(k, INT_RAW, reg(k, INT_RAW) & ~v); + update(k); + return; + } + if (off == INT_RAW || off == INT_ST) + return; + if (off == WDTCONFIG0) { + u32 was = reg(k, WDTCONFIG0); + esk_rf_write(k->p, off, n, v); + if (!(was & (CFG0_EN | CFG0_FLASHBOOT)) && wdt_on(k)) { + k->stage = 0; + k->wdt_from = k->slow; + } + } else { + esk_rf_write(k->p, off, n, v); + } + if (off == TIME_UPDATE && (v & (1u << 31))) { + u64 t = k->slow & 0xffffffffffffull; + hw(k, TIME0, (u32)t); + hw(k, TIME1, (u32)(t >> 32)); + hw(k, TIME_UPDATE, (reg(k, TIME_UPDATE) & ~(1u << 31)) | (1u << 30)); + } + if (off == CLK_CONF) + k->s->yield = 1; /* SOC_CLK_SEL: the CPU's clock (apbctrl.c) */ + if (off == OPTIONS0 || off == SW_CPU_STALL) + stalls(k); + if (off == OPTIONS0) { + u32 o = reg(k, OPTIONS0); + hw(k, OPTIONS0, o & ~(OPT0_SW_SYS_RST | OPT0_SW_PROCPU_RST | OPT0_SW_APPCPU_RST)); + if (v & OPT0_SW_SYS_RST) { + esk_esp32_reset(k->s, 3); + return; + } + if (v & OPT0_SW_APPCPU_RST) + esk_esp32_cpu_reset(k->s, 1, 12); + if (v & OPT0_SW_PROCPU_RST) + esk_esp32_cpu_reset(k->s, 0, 12); + } + expire(k); +} + +static void rt_tick(void *ctx, u32 cycles) +{ + struct e32_rtc *k = (struct e32_rtc *)ctx; + ES_UNUSED(cycles); + sync(k); + expire(k); +} + +static int rt_next(void *ctx, u32 *cycles) +{ + struct e32_rtc *k = (struct e32_rtc *)ctx; + u64 best = 0, c; + sync(k); + if (wdt_on(k)) { + u64 hold = stage_hold(k, k->stage), done = k->slow - k->wdt_from; + best = cycles_to(k, hold > done ? hold - done : 1); + } + if (reg(k, SLP_TIMER1) & (1u << 16)) { + u64 alarm = (u64)reg(k, SLP_TIMER0) | (u64)(reg(k, SLP_TIMER1) & 0xffffu) << 32, + now = k->slow & 0xffffffffffffull; + c = cycles_to(k, alarm > now ? alarm - now : 1); + if (!best || c < best) + best = c; + } + if (!best) + return 0; + *cycles = best > 0xffffffffu ? 0xffffffffu : (u32)best; + return 1; +} + +static int rtc_domain_lost(int code) +{ + return code == 1 || code == 16; +} + +static void rt_reset(void *ctx) +{ + struct e32_rtc *k = (struct e32_rtc *)ctx; + int chip = k->s->reset_cause == ESK_RESET_POWER || k->s->reset_cause == ESK_RESET_PIN; + int code = chip ? 1 : k->code[0]; + if (chip || rtc_domain_lost(code)) { + int i; + k->slow = 0; + k->frac = 0; + for (i = 0; i < k->p->nreg; i++) { /* a CHIP_PU reset too: the RTC domain starts again */ + k->p->reg[i]->value = k->p->reg[i]->reset; + k->p->reg[i]->once = 0; + } + } + k->stage = 0; + k->wdt_from = k->slow; + k->base_cycles = 0; + k->clocked = 0; + k->level = 0; + hw(k, RESET_STATE, (reg(k, RESET_STATE) & ~0xfffu) | (u32)code | (u32)(chip ? 1 : k->code[1]) << 6); + k->code[0] = k->code[1] = 1; + k->p->backup = 1; /* kept through the next system reset */ + update(k); + clocking(k); +} + +const struct esk_dev_ops esk_esp32_rtc_ops = { + "esp32-rtc", rt_read, rt_write, rt_reset, rt_tick, rt_next, +}; + +void *esk_esp32_rtc_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_rtc *k = (struct e32_rtc *)esk_mach_alloc(s, sizeof *k); + if (!k) + return 0; + k->s = s; + k->p = p; + k->code[0] = k->code[1] = 1; + return k; +} + +/* a reset of the whole digital system (and of the RTC domain for 1, 16) */ +void esk_esp32_reset(struct esk_mach *m, int code) +{ + struct e32_rtc *k = rtc_of(m); + if (k) { + k->code[0] = k->code[1] = code; + if (rtc_domain_lost(code)) + k->p->backup = 0; + } + m->reset_cpu_only = 0; + m->reset_cause = code == 3 ? ESK_RESET_SOFTWARE : ESK_RESET_WATCHDOG; + m->reset_req = 1; + m->yield = 1; +} + +/* one CPU alone: it restarts at its reset vector and reports `code` */ +void esk_esp32_cpu_reset(struct esk_mach *m, int core, int code) +{ + struct e32_rtc *k = rtc_of(m); + if (k) { + u32 rs = reg(k, RESET_STATE); + if (core == 0) + rs = (rs & ~0x3fu) | (u32)code; + else + rs = (rs & ~0xfc0u) | (u32)code << 6; + hw(k, RESET_STATE, rs); + } + esk_lx6_core_restart(m, core); +} + +void esk_esp32_rtc_reset_cause(struct esk_mach *m, int core, int code) +{ + struct e32_rtc *k = rtc_of(m); + if (k) { + u32 rs = reg(k, RESET_STATE); + rs = core == 0 ? (rs & ~0x3fu) | (u32)code : (rs & ~0xfc0u) | (u32)code << 6; + hw(k, RESET_STATE, rs); + } +} diff --git a/core/mcu/esp32/soc/sha.c b/core/mcu/esp32/soc/sha.c new file mode 100644 index 000000000..5e29d7899 --- /dev/null +++ b/core/mcu/esp32/soc/sha.c @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* sha.c -- the ESP32's SHA accelerator (TRM v5 chapter 23): SHA-1, + * SHA-256, SHA-384 and SHA-512 (FIPS 180-4) over message blocks the + * program writes in SHA_TEXT. + * + * - SHA_TEXT (0x00-0x7C) holds a block as 32-bit words in message order, + * each the big-endian value of four message bytes (ESP-IDF's sha_ll + * swaps them in): 16 words for SHA-1 and SHA-256, 32 for SHA-384 and + * SHA-512 (a 64-bit word's high half first); + * - writing 1 to a type's START (0x80, 0x90, 0xA0, 0xB0) hashes the block + * from the type's initial state, CONTINUE (+4) from the state so far; + * LOAD (+8) puts the state in SHA_TEXT, in the same word order, for + * the program to read; BUSY (+0xC) reads 0: each operation is done by + * the time the next access comes (the TRM gives no cycle counts). + * The state is the accelerator's, so a program that hashes with two types + * in turn without LOAD loses nothing it could see. SHA-384's LOAD puts + * its full 512-bit state, of which the digest is the first 384 bits. + * Not yet: DPORT's SHA clock gate and reset (PERI_CLK_EN, PERI_RST_EN). */ +#include + +#include "mcu/esp32/soc/esp32.h" +#include "util/sha256.h" + +#define TEXT_WORDS 32 + +struct e32_sha { + struct esk_mach *s; + struct esk_rf_periph *p; + u32 text[TEXT_WORDS]; + u32 h1[5], h256[8]; + u64 h512[8]; +}; + +static const u32 iv1[5] = { 0x67452301u, 0xefcdab89u, 0x98badcfeu, 0x10325476u, 0xc3d2e1f0u }; +static const u32 iv256[8] = { 0x6a09e667u, 0xbb67ae85u, 0x3c6ef372u, 0xa54ff53au, + 0x510e527fu, 0x9b05688cu, 0x1f83d9abu, 0x5be0cd19u }; +static const u64 iv384[8] = { 0xcbbb9d5dc1059ed8ull, 0x629a292a367cd507ull, 0x9159015a3070dd17ull, + 0x152fecd8f70e5939ull, 0x67332667ffc00b31ull, 0x8eb44a8768581511ull, + 0xdb0c2e0d64f98fa7ull, 0x47b5481dbefa4fa4ull }; +static const u64 iv512[8] = { 0x6a09e667f3bcc908ull, 0xbb67ae8584caa73bull, 0x3c6ef372fe94f82bull, + 0xa54ff53a5f1d36f1ull, 0x510e527fade682d1ull, 0x9b05688c2b3e6c1full, + 0x1f83d9abfb41bd6bull, 0x5be0cd19137e2179ull }; +static const u64 k512[80] = { + 0x428a2f98d728ae22ull, 0x7137449123ef65cdull, 0xb5c0fbcfec4d3b2full, 0xe9b5dba58189dbbcull, + 0x3956c25bf348b538ull, 0x59f111f1b605d019ull, 0x923f82a4af194f9bull, 0xab1c5ed5da6d8118ull, + 0xd807aa98a3030242ull, 0x12835b0145706fbeull, 0x243185be4ee4b28cull, 0x550c7dc3d5ffb4e2ull, + 0x72be5d74f27b896full, 0x80deb1fe3b1696b1ull, 0x9bdc06a725c71235ull, 0xc19bf174cf692694ull, + 0xe49b69c19ef14ad2ull, 0xefbe4786384f25e3ull, 0x0fc19dc68b8cd5b5ull, 0x240ca1cc77ac9c65ull, + 0x2de92c6f592b0275ull, 0x4a7484aa6ea6e483ull, 0x5cb0a9dcbd41fbd4ull, 0x76f988da831153b5ull, + 0x983e5152ee66dfabull, 0xa831c66d2db43210ull, 0xb00327c898fb213full, 0xbf597fc7beef0ee4ull, + 0xc6e00bf33da88fc2ull, 0xd5a79147930aa725ull, 0x06ca6351e003826full, 0x142929670a0e6e70ull, + 0x27b70a8546d22ffcull, 0x2e1b21385c26c926ull, 0x4d2c6dfc5ac42aedull, 0x53380d139d95b3dfull, + 0x650a73548baf63deull, 0x766a0abb3c77b2a8ull, 0x81c2c92e47edaee6ull, 0x92722c851482353bull, + 0xa2bfe8a14cf10364ull, 0xa81a664bbc423001ull, 0xc24b8b70d0f89791ull, 0xc76c51a30654be30ull, + 0xd192e819d6ef5218ull, 0xd69906245565a910ull, 0xf40e35855771202aull, 0x106aa07032bbd1b8ull, + 0x19a4c116b8d2d0c8ull, 0x1e376c085141ab53ull, 0x2748774cdf8eeb99ull, 0x34b0bcb5e19b48a8ull, + 0x391c0cb3c5c95a63ull, 0x4ed8aa4ae3418acbull, 0x5b9cca4f7763e373ull, 0x682e6ff3d6b2b8a3ull, + 0x748f82ee5defb2fcull, 0x78a5636f43172f60ull, 0x84c87814a1f0ab72ull, 0x8cc702081a6439ecull, + 0x90befffa23631e28ull, 0xa4506cebde82bde9ull, 0xbef9a3f7b2c67915ull, 0xc67178f2e372532bull, + 0xca273eceea26619cull, 0xd186b8c721c0c207ull, 0xeada7dd6cde0eb1eull, 0xf57d4f7fee6ed178ull, + 0x06f067aa72176fbaull, 0x0a637dc5a2c898a6ull, 0x113f9804bef90daeull, 0x1b710b35131c471bull, + 0x28db77f523047d84ull, 0x32caab7b40c72493ull, 0x3c9ebe0a15c9bebcull, 0x431d67c49c100d4cull, + 0x4cc5d4becb3e42b6ull, 0x597f299cfc657e2aull, 0x5fcb6fab3ad6faecull, 0x6c44198c4a475817ull }; + +static u32 rol(u32 x, int n) { return (x << n) | (x >> (32 - n)); } +static u64 ror64(u64 x, int n) { return (x >> n) | (x << (64 - n)); } + +static void sha1_block(u32 h[5], const u32 m[16]) +{ + u32 w[80], a = h[0], b = h[1], c = h[2], d = h[3], e = h[4], f, k, t; + int i; + for (i = 0; i < 16; i++) + w[i] = m[i]; + for (; i < 80; i++) + w[i] = rol(w[i - 3] ^ w[i - 8] ^ w[i - 14] ^ w[i - 16], 1); + for (i = 0; i < 80; i++) { + if (i < 20) { f = (b & c) | (~b & d); k = 0x5a827999u; } + else if (i < 40) { f = b ^ c ^ d; k = 0x6ed9eba1u; } + else if (i < 60) { f = (b & c) | (b & d) | (c & d); k = 0x8f1bbcdcu; } + else { f = b ^ c ^ d; k = 0xca62c1d6u; } + t = rol(a, 5) + f + e + k + w[i]; + e = d; d = c; c = rol(b, 30); b = a; a = t; + } + h[0] += a; h[1] += b; h[2] += c; h[3] += d; h[4] += e; +} + +static void sha512_block(u64 h[8], const u32 m[32]) +{ + u64 w[80], v[8], t1, t2; + int i, j; + for (i = 0; i < 16; i++) + w[i] = (u64)m[2 * i] << 32 | m[2 * i + 1]; + for (; i < 80; i++) { + u64 s0 = ror64(w[i - 15], 1) ^ ror64(w[i - 15], 8) ^ (w[i - 15] >> 7); + u64 s1 = ror64(w[i - 2], 19) ^ ror64(w[i - 2], 61) ^ (w[i - 2] >> 6); + w[i] = w[i - 16] + s0 + w[i - 7] + s1; + } + for (j = 0; j < 8; j++) + v[j] = h[j]; + for (i = 0; i < 80; i++) { + t1 = v[7] + (ror64(v[4], 14) ^ ror64(v[4], 18) ^ ror64(v[4], 41)) + ((v[4] & v[5]) ^ (~v[4] & v[6])) + + k512[i] + w[i]; + t2 = (ror64(v[0], 28) ^ ror64(v[0], 34) ^ ror64(v[0], 39)) + + ((v[0] & v[1]) ^ (v[0] & v[2]) ^ (v[1] & v[2])); + v[7] = v[6]; v[6] = v[5]; v[5] = v[4]; v[4] = v[3] + t1; + v[3] = v[2]; v[2] = v[1]; v[1] = v[0]; v[0] = t1 + t2; + } + for (j = 0; j < 8; j++) + h[j] += v[j]; +} + +static void sha256_words(u32 h[8], const u32 m[16]) +{ + u8 blk[64]; + int i; + for (i = 0; i < 16; i++) { + blk[4 * i] = (u8)(m[i] >> 24); + blk[4 * i + 1] = (u8)(m[i] >> 16); + blk[4 * i + 2] = (u8)(m[i] >> 8); + blk[4 * i + 3] = (u8)m[i]; + } + esk_sha256_block(h, blk); +} + +/* type 0 SHA-1, 1 SHA-256, 2 SHA-384, 3 SHA-512; op 0 start, 1 continue, 2 load */ +static void operate(struct e32_sha *k, int type, int op) +{ + int i; + if (op == 2) { + if (type == 0) + for (i = 0; i < 5; i++) + k->text[i] = k->h1[i]; + else if (type == 1) + for (i = 0; i < 8; i++) + k->text[i] = k->h256[i]; + else + for (i = 0; i < 8; i++) { + k->text[2 * i] = (u32)(k->h512[i] >> 32); + k->text[2 * i + 1] = (u32)k->h512[i]; + } + return; + } + if (type == 0) { + if (op == 0) + memcpy(k->h1, iv1, sizeof k->h1); + sha1_block(k->h1, k->text); + } else if (type == 1) { + if (op == 0) + memcpy(k->h256, iv256, sizeof k->h256); + sha256_words(k->h256, k->text); + } else { + if (op == 0) + memcpy(k->h512, type == 2 ? iv384 : iv512, sizeof k->h512); + sha512_block(k->h512, k->text); + } +} + +static u32 sh_read(void *ctx, u32 off, int n) +{ + struct e32_sha *k = (struct e32_sha *)ctx; + if (off < 4u * TEXT_WORDS) + return k->text[off / 4u] >> (8u * (off & 3u)); + if (off >= 0x80u && off < 0xC0u) + return 0; /* START, CONTINUE, LOAD are write-only; BUSY: done */ + return esk_rf_read(k->p, off, n); +} + +static void sh_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_sha *k = (struct e32_sha *)ctx; + if (off < 4u * TEXT_WORDS) { + if (n == 4) + k->text[off / 4u] = v; + return; + } + if (off >= 0x80u && off < 0xC0u && (off & 0xCu) != 0xCu && (v & 1u)) { + operate(k, (int)((off - 0x80u) / 0x10u), (int)((off & 0xCu) / 4u)); + return; + } + esk_rf_write(k->p, off, n, v); +} + +static void sh_reset(void *ctx) +{ + struct e32_sha *k = (struct e32_sha *)ctx; + memset(k->text, 0, sizeof k->text); +} + +const struct esk_dev_ops esk_esp32_sha_ops = { + "esp32-sha", sh_read, sh_write, sh_reset, 0, 0, +}; + +void *esk_esp32_sha_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_sha *k = (struct e32_sha *)esk_mach_alloc(s, sizeof *k); + if (!k) + return 0; + k->s = s; + k->p = p; + return k; +} diff --git a/core/mcu/esp32/soc/spi.c b/core/mcu/esp32/soc/spi.c new file mode 100644 index 000000000..8e57abbf1 --- /dev/null +++ b/core/mcu/esp32/soc/spi.c @@ -0,0 +1,354 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* spi.c -- the ESP32's SPI0 and SPI1 (TRM v5 chapter 7), the controllers + * in front of the module's flash (nor.c): SPI0 the caches', SPI1 the + * program's. + * + * A write of CMD starts the transaction its bit names, on the flash: + * - FLASH_READ: ADDR[31:24] bytes from ADDR[23:0] into W0-W15, with the + * read instruction CTRL selects (FREAD_QIO EBh, FREAD_DIO BBh, + * FREAD_QUAD 6Bh, FREAD_DUAL 3Bh, FASTRD_MODE 0Bh, else 03h); + * - FLASH_PP: ADDR[31:24] bytes from W0 (02h, or 32h with FWRITE_QUAD); + * FLASH_SE (20h), FLASH_BE (D8h), FLASH_CE (C7h) at ADDR; + * - FLASH_WREN (06h), FLASH_WRDI (04h), FLASH_RDSR (05h into + * RD_STATUS), FLASH_WRSR (01h from RD_STATUS: one byte, two with + * WRSR_2B), FLASH_RDID (9Fh into W0), FLASH_DP (B9h), FLASH_RES (ABh), + * FLASH_HPM (A3h), FLASH_PES (75h), FLASH_PER (7Ah); + * - USR: the user transaction USER enables: the command (USER2's + * USR_COMMAND_VALUE, USR_COMMAND_BITLEN + 1 bits), the address + * (ADDR's USR_ADDR_BITLEN + 1 most significant bits), the dummy + * cycles, MOSI_DLEN + 1 bits out of W0 (W8 with USR_MOSI_HIGHPART) and + * MISO_DLEN + 1 bits into W0 (W8 with USR_MISO_HIGHPART). + * The command's bit reads 1 while the transaction is on the bus -- the + * bits it carries at the SPI clock (CLOCK: APB_CLK with CLK_EQU_SYSCLK, + * else APB_CLK / (CLKDIV_PRE + 1) / (CLKCNT_N + 1)), its address and data + * on two or four lines as the mode says -- and EXT2's ST is not idle; + * then SLAVE's TRANS_DONE is set, and with its INT_EN bit the matrix + * source (SPI0 30, SPI1 31 in the register description's table). + * Bytes in the W buffers are little-endian (RD_BYTE_ORDER and + * WR_BYTE_ORDER 0). + * Not modelled: the byte and bit orders' other settings, the controllers' + * DMA and slave modes (SPI0 and SPI1 are masters on the flash), the CRC, + * the flash encryption on SPI1's writes, PSRAM (SPI0's cache path to it), + * the cache's own reads (dport.c reads the flash directly). */ +#include + +#include "mcu/esp32/soc/esp32.h" + +#define CMD 0x00u +#define ADDR 0x04u +#define CTRL 0x08u +#define RD_STATUS 0x10u +#define CLOCK 0x18u +#define USER 0x1Cu +#define USER1 0x20u +#define USER2 0x24u +#define MOSI_DLEN 0x28u +#define MISO_DLEN 0x2Cu +#define SLAVE 0x38u +#define W0 0x80u +#define EXT2 0xF8u + +#define CMD_USR (1u << 18) +#define CMD_HPM (1u << 19) +#define CMD_RES (1u << 20) +#define CMD_DP (1u << 21) +#define CMD_CE (1u << 22) +#define CMD_BE (1u << 23) +#define CMD_SE (1u << 24) +#define CMD_PP (1u << 25) +#define CMD_WRSR (1u << 26) +#define CMD_RDSR (1u << 27) +#define CMD_RDID (1u << 28) +#define CMD_WRDI (1u << 29) +#define CMD_WREN (1u << 30) +#define CMD_READ (1u << 31) +#define CMD_PES (1u << 17) +#define CMD_PER (1u << 16) +#define CMD_ANY 0xFFFF0000u + +struct e32_spi { + struct esk_mach *s; + struct esk_rf_periph *p; + struct esk_esp32_nor *nor; + int unit, source, level; + u32 busy; /* the command bit in progress */ + u64 left; + int clocked; +}; + +static u32 reg(struct e32_spi *k, u32 off) +{ + return esk_rf_read(k->p, off, 4); +} + +static void hw(struct e32_spi *k, u32 off, u32 v) +{ + struct esk_rf_reg *r = esk_rf_reg_at(k->p, off); + if (r) + esk_rf_hw(r, v); +} + +static void buf_get(struct e32_spi *k, u32 at, u8 *d, int n) +{ + int i; + for (i = 0; i < n && i < 64; i++) + d[i] = (u8)(reg(k, W0 + at + (u32)(i & ~3)) >> (8 * (i & 3))); +} + +static void buf_put(struct e32_spi *k, u32 at, const u8 *d, int n) +{ + int i; + for (i = 0; i < n && i < 64; i += 4) { + u32 w = reg(k, W0 + at + (u32)i); + int b; + for (b = 0; b < 4 && i + b < n; b++) + w = (w & ~(0xffu << (8 * b))) | (u32)d[i + b] << (8 * b); + hw(k, W0 + at + (u32)i, w); + } +} + +/* the SPI clock in Hz */ +static double spi_hz(struct e32_spi *k) +{ + u32 c = reg(k, CLOCK); + double apb = (double)esk_esp32_apb_hz(k->s); + if (c & (1u << 31)) + return apb; + return apb / (double)(((c >> 18) & 0x1fffu) + 1u) / (double)(((c >> 12) & 0x3fu) + 1u); +} + +/* the flash read instruction CTRL selects, and its data lines */ +static u8 read_op(struct e32_spi *k, int *lines) +{ + u32 c = reg(k, CTRL); + *lines = 1; + if (c & (1u << 24)) { *lines = 4; return 0xEB; } + if (c & (1u << 23)) { *lines = 2; return 0xBB; } + if (c & (1u << 20)) { *lines = 4; return 0x6B; } + if (c & (1u << 14)) { *lines = 2; return 0x3B; } + if (c & (1u << 13)) + return 0x0B; + return 0x03; +} + +static void addr3(u8 *tx, u32 a) +{ + tx[1] = (u8)(a >> 16); + tx[2] = (u8)(a >> 8); + tx[3] = (u8)a; +} + +static void update(struct e32_spi *k) +{ + u32 sl = reg(k, SLAVE); + int lv = ((sl & 0x1fu) & ((sl >> 5) & 0x1fu)) != 0; + if (lv != k->level && k->source >= 0) { + k->level = lv; + esk_esp32_source(k->s, k->source, lv); + } +} + +/* the transaction: the flash's part now, its bus time in SPI clocks */ +static u64 run(struct e32_spi *k, u32 cmd) +{ + u8 tx[80], rx[64]; + u32 a = reg(k, ADDR), len = a >> 24, user = reg(k, USER); + int lines = 1, n; + u64 clocks = 8; + memset(tx, 0, sizeof tx); + memset(rx, 0xff, sizeof rx); + if (len > 64) + len = 64; + if (cmd == CMD_READ) { + tx[0] = read_op(k, &lines); + addr3(tx, a); + esk_esp32_nor_xfer(k->nor, tx, 4, rx, (int)len); + buf_put(k, 0, rx, (int)len); + return clocks + (24u + 8u * len) / (u32)lines + (tx[0] == 0x03 ? 0u : 8u); + } + if (cmd == CMD_PP) { + tx[0] = (user & (1u << 13)) ? 0x32 : 0x02; + addr3(tx, a); + buf_get(k, 0, tx + 4, (int)len); + esk_esp32_nor_xfer(k->nor, tx, 4 + (int)len, rx, 0); + return clocks + 24u + 8u * len; + } + if (cmd == CMD_SE || cmd == CMD_BE) { + tx[0] = cmd == CMD_SE ? 0x20 : 0xD8; + addr3(tx, a); + esk_esp32_nor_xfer(k->nor, tx, 4, rx, 0); + return clocks + 24u; + } + if (cmd == CMD_RDSR) { + tx[0] = 0x05; + esk_esp32_nor_xfer(k->nor, tx, 1, rx, 1); + hw(k, RD_STATUS, (reg(k, RD_STATUS) & ~0xffu) | rx[0]); + return clocks + 8u; + } + if (cmd == CMD_WRSR) { + u32 st = reg(k, RD_STATUS); + int two = (reg(k, CTRL) & (1u << 22)) != 0; + tx[0] = 0x01; + tx[1] = (u8)st; + tx[2] = (u8)(st >> 8); + esk_esp32_nor_xfer(k->nor, tx, two ? 3 : 2, rx, 0); + return clocks + (two ? 16u : 8u); + } + if (cmd == CMD_RDID) { + tx[0] = 0x9F; + esk_esp32_nor_xfer(k->nor, tx, 1, rx, 3); + hw(k, W0, (u32)rx[0] | (u32)rx[1] << 8 | (u32)rx[2] << 16); + return clocks + 24u; + } + if (cmd != CMD_USR) { + tx[0] = cmd == CMD_WREN ? 0x06 : cmd == CMD_WRDI ? 0x04 : cmd == CMD_CE ? 0xC7 : cmd == CMD_DP ? 0xB9 + : cmd == CMD_RES ? 0xAB : cmd == CMD_HPM ? 0xA3 : cmd == CMD_PES ? 0x75 : 0x7A; + esk_esp32_nor_xfer(k->nor, tx, 1, rx, 0); + return clocks; + } + /* a user transaction */ + n = 0; + clocks = 0; + if (user & (1u << 31)) { + u32 bits = ((reg(k, USER2) >> 28) & 15u) + 1u, v = reg(k, USER2) & 0xffffu; + int nb = (int)((bits + 7u) / 8u), i; + for (i = 0; i < nb; i++) + tx[n++] = (u8)(v >> (8 * i)); + clocks += bits; + } + if (user & (1u << 30)) { + u32 bits = ((reg(k, USER1) >> 26) & 0x3fu) + 1u; + int nb = (int)((bits + 7u) / 8u), i; + for (i = 0; i < nb && i < 4; i++) + tx[n++] = (u8)(a >> (24 - 8 * i)); + clocks += bits; + } + if (user & (1u << 29)) + clocks += (reg(k, USER1) & 0xffu) + 1u; + if (user & (1u << 27)) { + u32 bits = (reg(k, MOSI_DLEN) & 0xffffffu) + 1u; + int nb = (int)((bits + 7u) / 8u); + if (nb > 64) + nb = 64; + buf_get(k, (user & (1u << 25)) ? 32u : 0u, tx + n, nb); + n += nb; + clocks += bits; + } + { + int nrx = 0; + if (user & (1u << 28)) { + u32 bits = (reg(k, MISO_DLEN) & 0xffffffu) + 1u; + nrx = (int)((bits + 7u) / 8u); + if (nrx > 64) + nrx = 64; + clocks += bits; + } + if (n) + esk_esp32_nor_xfer(k->nor, tx, n, rx, nrx); + if (nrx) + buf_put(k, (user & (1u << 24)) ? 32u : 0u, rx, nrx); + } + return clocks; +} + +static void done(struct e32_spi *k) +{ + k->busy = 0; + hw(k, CMD, reg(k, CMD) & ~CMD_ANY); + hw(k, EXT2, 0); + hw(k, SLAVE, reg(k, SLAVE) | (1u << 4)); /* TRANS_DONE */ + esk_rf_clock(k->p, &k->clocked, 0); + update(k); +} + +static u32 sp_read(void *ctx, u32 off, int n) +{ + struct e32_spi *k = (struct e32_spi *)ctx; + return esk_rf_read(k->p, off, n); +} + +static void sp_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_spi *k = (struct e32_spi *)ctx; + esk_rf_write(k->p, off, n, v); + if (off == CMD && !k->busy && (v & CMD_ANY)) { + u32 cmd = 0x80000000u, clocks; + while (cmd && !(v & cmd)) + cmd >>= 1; + clocks = (u32)run(k, cmd); + k->busy = cmd; + hw(k, CMD, cmd); + hw(k, EXT2, 1); + k->left = (u64)((double)clocks * (double)esk_mach_core_hz(k->s) / spi_hz(k)) + 1u; + esk_rf_clock(k->p, &k->clocked, 1); + } else if (off == CMD && k->busy) { + hw(k, CMD, (reg(k, CMD) & ~CMD_ANY) | k->busy); + } else if (off == SLAVE) { + update(k); + } +} + +static void sp_tick(void *ctx, u32 cycles) +{ + struct e32_spi *k = (struct e32_spi *)ctx; + if (!k->busy) + return; + if (k->left > cycles) { + k->left -= cycles; + return; + } + done(k); +} + +static int sp_next(void *ctx, u32 *cycles) +{ + struct e32_spi *k = (struct e32_spi *)ctx; + if (!k->busy) + return 0; + *cycles = k->left > 0xffffffffu ? 0xffffffffu : (u32)k->left; + return 1; +} + +static void sp_reset(void *ctx) +{ + struct e32_spi *k = (struct e32_spi *)ctx; + k->busy = 0; + k->clocked = 0; + k->level = 0; + if (k->unit == 1 && k->nor && k->s->reset_cause == ESK_RESET_POWER) + esk_esp32_nor_power_on(k->nor); +} + +const struct esk_dev_ops esk_esp32_spi_ops = { + "esp32-spi", sp_read, sp_write, sp_reset, sp_tick, sp_next, +}; + +void *esk_esp32_spi_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_spi *k; + if (strcmp(p->name, "SPI0") && strcmp(p->name, "SPI1")) + return 0; + k = (struct e32_spi *)esk_mach_alloc(s, sizeof *k); + if (!k) + return 0; + k->s = s; + k->p = p; + k->unit = p->name[3] - '0'; + k->source = esk_rf_irq(p, p->name); + k->nor = esk_esp32_nor_of(s); + if (!k->nor) + return 0; + return k; +} + +/* the one flash chip both controllers reach, made by whichever comes first */ +struct esk_esp32_nor *esk_esp32_nor_of(struct esk_mach *m) +{ + struct esk_rf_periph *p; + int i; + for (i = 0; m->rf && (p = esk_rf_periph_at(m->rf, i)) != 0; i++) + if (p->ops == &esk_esp32_spi_ops && p->ctx && ((struct e32_spi *)p->ctx)->nor) + return ((struct e32_spi *)p->ctx)->nor; + return esk_esp32_nor_create(m); +} diff --git a/core/mcu/esp32/soc/timg.c b/core/mcu/esp32/soc/timg.c new file mode 100644 index 000000000..7aa7a9b46 --- /dev/null +++ b/core/mcu/esp32/soc/timg.c @@ -0,0 +1,434 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* timg.c -- the ESP32's timer groups TIMG0 and TIMG1 (TRM v5 chapters 18 + * and 19): in each, the 64-bit timers T0 and T1, the LAC timer (LACT), the + * main system watchdog (MWDT) and the RTC_SLOW_CLK calibration. The + * ESP32-C3's model (mcu/esp32c3/timg.c) on the ESP32's registers. + * + * - T0, T1 and LACT count APB_CLK over DIVIDER (0 is 65536, 1 is 2), up + * or down (INCREASE) over 64 bits while EN is set. A write to UPDATE + * latches the count in LO/HI; one to LOAD loads LOADLO/HI. With + * ALARM_EN a timer alarms when it reaches ALARMLO/HI, or at once when + * the alarm is up to 2^63 behind it in its direction; the alarm clears + * ALARM_EN, sets its INT_RAW bit and reloads with AUTORELOAD. + * - The MWDT counts APB_CLK over WDT_CLK_PRESCALE through four stages + * (WDTCONFIG2-5's holds), each's action off, an interrupt (WDT's + * INT_RAW bit), a CPU reset (TGWDT_CPU_RESET, 11) or a system reset + * (TG0WDT_SYS_RESET 7, TG1WDT_SYS_RESET 8); WDT_EN runs it. With + * WDT_FLASHBOOT_MOD_EN, set out of reset in TIMG0, it runs with stage + * 0 a system reset. WDTFEED returns it to stage 0. While WDTWPROTECT + * is not 0x50D83AA1 the WDT registers ignore writes. + * - RTCCALICFG's START counts MAX cycles of the clock CLK_SEL names + * (RTC_SLOW_CLK as RTC_CNTL selects it, 8MD256's 31.25 kHz, the + * board's 32.768 kHz crystal) against the 40 MHz crystal once; when + * done RDY is set and RTCCALICFG1's VALUE holds the crystal's count; + * a MAX of 0 sets RDY at the clock's next cycle (taken one period + * away). START_CYCLING counts again and again. A clock that does not run (no + * 32 kHz crystal) never makes RDY. + * - INT_ST is INT_RAW and INT_ENA; each bit drives its level source + * (TIMG0's T0 14, T1 15, WDT 16, LACT 17; TIMG1's 18-21), and an alarm + * whose EDGE_INT_EN is set pulses its edge source (TIMG0 51-54, TIMG1 + * 55-58). + * Inside, the RC oscillators run at their nominal frequencies. + * Not yet: LACT's RTC step mode (LACTRTC, RTC_ONLY, CPST_EN: it counts + * APB_CLK), the reset signals' lengths. */ +#include + +#include "mcu/esp32/soc/esp32.h" + +#define HALF63 (1ull << 63) +#define WKEY 0x50D83AA1u + +#define T_ALARM_EN (1u << 10) +#define T_LEVEL_INT_EN (1u << 11) +#define T_EDGE_INT_EN (1u << 12) +#define T_AUTORELOAD (1u << 29) +#define T_INCREASE (1u << 30) +#define T_EN (1u << 31) + +#define W0_FLASHBOOT (1u << 14) +#define W0_EN (1u << 31) + +#define CALI_CYCLING (1u << 12) +#define CALI_RDY (1u << 15) +#define CALI_START (1u << 31) + +#define WDTCONFIG0 0x48u +#define WDTFEED 0x60u +#define WPROTECT 0x64u +#define RTCCALICFG 0x68u +#define RTCCALICFG1 0x6Cu +#define INT_ENA 0x98u +#define INT_RAW 0x9Cu +#define INT_ST 0xA0u +#define INT_CLR 0xA4u + +/* each timer's registers: config, lo, hi, update, alarm lo/hi, load lo/hi, load */ +static const u32 tbase[3] = { 0x00, 0x24, 0x70 }; + +struct e32_timg { + struct esk_mach *s; + struct esk_rf_periph *p; + int group, level[4], clocked; + u64 value[3], frac[3]; + int stage; + u64 wcount, w_frac; + int cali_on; + u64 cali_x, cali_need, x_frac; + u64 cali_wait; /* MAX 0: the crystal's cycles to the next slow cycle */ +}; + +static u32 rd(struct e32_timg *k, u32 off) { return esk_rf_read(k->p, off, 4); } + +static void hw(struct e32_timg *k, u32 off, u32 v) +{ + struct esk_rf_reg *r = esk_rf_reg_at(k->p, off); + if (r) + esk_rf_hw(r, v); +} + +/* a timer's register: 0 config, 1 lo, 2 hi, 3 update, 4/5 alarm, 6/7 load, 8 load trigger */ +static u32 toff(int t, int r) +{ + return tbase[t] + (t == 2 && r > 0 ? 8u : 0u) + 4u * (u32)r - (t == 2 && r > 0 ? 4u : 0u); +} + +static void update(struct e32_timg *k) +{ + u32 st = rd(k, INT_RAW) & rd(k, INT_ENA) & 15u; + int i; + hw(k, INT_ST, st); + for (i = 0; i < 4; i++) { + int l = (int)(st >> i & 1u); + if (l != k->level[i]) { + k->level[i] = l; + esk_esp32_source(k->s, (k->group ? 18 : 14) + i, l); + } + } +} + +static void edge(struct e32_timg *k, int i) +{ + int src = (k->group ? 55 : 51) + i; + esk_esp32_source(k->s, src, 1); + esk_esp32_source(k->s, src, 0); +} + +static u64 ticks(struct e32_timg *k, u32 cycles, u32 src_hz, u32 div, u64 *frac) +{ + u64 hz = (u64)esk_mach_core_hz(k->s) * div, n; + if (!hz) + return 0; + *frac += (u64)cycles * src_hz; + n = *frac / hz; + *frac %= hz; + return n; +} + +static u32 t_div(struct e32_timg *k, int t) +{ + u32 d = (rd(k, toff(t, 0)) >> 13) & 0xffffu; + return d == 0 ? 65536u : d == 1 ? 2u : d; +} + +static u64 pair(struct e32_timg *k, u32 lo) +{ + return (u64)rd(k, lo + 4u) << 32 | rd(k, lo); +} + +static void t_alarm(struct e32_timg *k, int t) +{ + u32 c = rd(k, toff(t, 0)); + hw(k, toff(t, 0), c & ~T_ALARM_EN); + hw(k, INT_RAW, rd(k, INT_RAW) | (t == 2 ? 8u : 1u << t)); + if (c & T_AUTORELOAD) + k->value[t] = pair(k, toff(t, 6)); + if (c & T_EDGE_INT_EN) + edge(k, t == 2 ? 3 : t); +} + +static u64 t_ahead(struct e32_timg *k, int t) +{ + u64 a = pair(k, toff(t, 4)), d; + d = rd(k, toff(t, 0)) & T_INCREASE ? a - k->value[t] : k->value[t] - a; + return d > HALF63 ? 0 : d; +} + +static void t_run(struct e32_timg *k, int t, u32 cycles) +{ + u64 n; + if (!(rd(k, toff(t, 0)) & T_EN)) + return; + n = ticks(k, cycles, esk_esp32_apb_hz(k->s), t_div(k, t), &k->frac[t]); + while (n) { + u64 step = n; + u32 c = rd(k, toff(t, 0)); + if (c & T_ALARM_EN) { + u64 d = t_ahead(k, t); + if (d == 0) { + t_alarm(k, t); + continue; + } + if (d <= n) + step = d; + } + k->value[t] = c & T_INCREASE ? k->value[t] + step : k->value[t] - step; + n -= step; + if ((rd(k, toff(t, 0)) & T_ALARM_EN) && t_ahead(k, t) == 0) + t_alarm(k, t); + } +} + +/* ---- the MWDT ------------------------------------------------------------ */ + +static u32 w0(struct e32_timg *k) { return rd(k, WDTCONFIG0); } +static int flashboot(struct e32_timg *k) { return k->group == 0 && (w0(k) & W0_FLASHBOOT); } +static int wdt_on(struct e32_timg *k) { return (w0(k) & W0_EN) || flashboot(k); } +static u32 prescale(struct e32_timg *k) +{ + u32 p = (rd(k, WDTCONFIG0 + 4u) >> 16) & 0xffffu; + return p ? p : 65536u; +} +static u64 hold(struct e32_timg *k, int s) { return rd(k, WDTCONFIG0 + 8u + 4u * (u32)s); } + +static u32 stage_action(struct e32_timg *k, int s) +{ + if (s == 0 && flashboot(k)) + return 3; + return (w0(k) >> (29 - 2 * s)) & 3u; +} + +static void wdt_expire(struct e32_timg *k) +{ + u32 act = stage_action(k, k->stage); + k->wcount = 0; + k->stage = (k->stage + 1) & 3; + if (act == 1) { + hw(k, INT_RAW, rd(k, INT_RAW) | 4u); + if (w0(k) & (1u << 22)) + edge(k, 2); + } else if (act == 2) { + esk_esp32_cpu_reset(k->s, 0, 11); + esk_esp32_cpu_reset(k->s, 1, 11); + } else if (act == 3) { + esk_esp32_reset(k->s, k->group ? 8 : 7); + } +} + +static void wdt_run(struct e32_timg *k, u32 cycles) +{ + u64 n; + int guard = 8; + if (!wdt_on(k)) + return; + n = ticks(k, cycles, esk_esp32_apb_hz(k->s), prescale(k), &k->w_frac); + while (n && guard--) { + u64 h = hold(k, k->stage), left = h > k->wcount ? h - k->wcount : 0; + if (n < left) { + k->wcount += n; + return; + } + n -= left; + wdt_expire(k); + if (k->s->reset_req) + return; + } +} + +/* ---- the calibration ----------------------------------------------------- */ + +static double cali_hz(struct e32_timg *k) +{ + u32 sel = (rd(k, RTCCALICFG) >> 13) & 3u; + return sel == 0 ? esk_esp32_rtc_slow_hz(k->s) : sel == 1 ? 8000000.0 / 256.0 : (double)k->s->lse_hz; +} + +static void cali_start(struct e32_timg *k, int periodic) +{ + double hz = cali_hz(k); + u32 max = (rd(k, RTCCALICFG) >> 16) & 0x7fffu; + k->cali_on = periodic ? 2 : 1; + k->cali_x = 0; + k->cali_need = hz > 0 ? (u64)((double)max * ESP32_XTAL_HZ / hz + 0.5) : 0; + k->cali_wait = 0; + if (hz > 0 && max == 0) { + /* none counted: RDY at the clock's next cycle (ESP-IDF's + * rtc_clk_wait_for_slow_cycle), taken as one period away */ + k->cali_wait = (u64)((double)ESP32_XTAL_HZ / hz + 0.5); + } + if (!periodic) + hw(k, RTCCALICFG, rd(k, RTCCALICFG) & ~CALI_RDY); +} + +static u64 cali_end(struct e32_timg *k) +{ + return k->cali_need ? k->cali_need : k->cali_wait; +} + +static void cali_run(struct e32_timg *k, u32 cycles) +{ + if (!k->cali_on || !cali_end(k)) + return; + k->cali_x += ticks(k, cycles, ESP32_XTAL_HZ, 1, &k->x_frac); + if (k->cali_x < cali_end(k)) + return; + hw(k, RTCCALICFG1, (u32)(k->cali_need & 0x1ffffffu) << 7); + hw(k, RTCCALICFG, rd(k, RTCCALICFG) | CALI_RDY); + if (k->cali_on == 2) + k->cali_x %= cali_end(k); + else + k->cali_on = 0; +} + +/* ---- the device ---------------------------------------------------------- */ + +static int any_on(struct e32_timg *k) +{ + int t; + for (t = 0; t < 3; t++) + if (rd(k, toff(t, 0)) & T_EN) + return 1; + return wdt_on(k) || (k->cali_on && cali_end(k)); +} + +static void clocking(struct e32_timg *k) +{ + esk_rf_clock(k->p, &k->clocked, any_on(k)); +} + +static void tg_tick(void *ctx, u32 cycles) +{ + struct e32_timg *k = (struct e32_timg *)ctx; + int t; + for (t = 0; t < 3; t++) + t_run(k, t, cycles); + wdt_run(k, cycles); + cali_run(k, cycles); + update(k); + clocking(k); +} + +static u64 to_cycles(struct e32_timg *k, u64 n, double src_hz, u64 div, u64 frac) +{ + double c = ((double)n * (double)esk_mach_core_hz(k->s) * (double)div - (double)frac) / src_hz; + if (src_hz <= 0 || c > 4.0e9) + return 0xffffffffu; + return c < 1.0 ? 1u : (u64)c + 1u; +} + +static int tg_next(void *ctx, u32 *cycles) +{ + struct e32_timg *k = (struct e32_timg *)ctx; + u64 best = 0, c; + int any = 0, t; + for (t = 0; t < 3; t++) { + u32 conf = rd(k, toff(t, 0)); + if ((conf & T_EN) && (conf & T_ALARM_EN)) { + u64 d = t_ahead(k, t); + c = d ? to_cycles(k, d, (double)esk_esp32_apb_hz(k->s), t_div(k, t), k->frac[t]) : 1; + if (!any || c < best) + best = c; + any = 1; + } + } + if (wdt_on(k)) { + u64 h = hold(k, k->stage), left = h > k->wcount ? h - k->wcount : 1; + c = to_cycles(k, left, (double)esk_esp32_apb_hz(k->s), prescale(k), k->w_frac); + if (!any || c < best) + best = c; + any = 1; + } + if (k->cali_on && cali_end(k)) { + u64 left = cali_end(k) > k->cali_x ? cali_end(k) - k->cali_x : 1; + c = to_cycles(k, left, (double)ESP32_XTAL_HZ, 1, k->x_frac); + if (!any || c < best) + best = c; + any = 1; + } + if (!any) + return 0; + *cycles = best == 0 ? 1u : best > 0xffffffffu ? 0xffffffffu : (u32)best; + return 1; +} + +static u32 tg_read(void *ctx, u32 off, int n) +{ + struct e32_timg *k = (struct e32_timg *)ctx; + return esk_rf_read(k->p, off, n); +} + +static void tg_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_timg *k = (struct e32_timg *)ctx; + u32 cali0 = rd(k, RTCCALICFG), conf[3]; + int t; + if (((off >= WDTCONFIG0 && off <= WDTFEED)) && rd(k, WPROTECT) != WKEY) + return; /* write-protected */ + for (t = 0; t < 3; t++) + conf[t] = rd(k, toff(t, 0)); + esk_rf_write(k->p, off, n, v); + for (t = 0; t < 3; t++) { + if (off == toff(t, 3)) { + hw(k, toff(t, 1), (u32)k->value[t]); + hw(k, toff(t, 2), (u32)(k->value[t] >> 32)); + } else if (off == toff(t, 8)) { + k->value[t] = pair(k, toff(t, 6)); + } else if (off == toff(t, 0)) { + if ((rd(k, off) & T_ALARM_EN) && !(conf[t] & T_ALARM_EN) && t_ahead(k, t) == 0) + t_alarm(k, t); + } + } + if (off == WDTFEED) { + k->stage = 0; + k->wcount = 0; + } else if (off == WDTCONFIG0 && !(v & W0_EN) && !(v & W0_FLASHBOOT)) { + k->stage = 0; + k->wcount = 0; + } else if (off == RTCCALICFG) { + u32 now = rd(k, RTCCALICFG); + if ((now & CALI_START) && !(cali0 & CALI_START)) + cali_start(k, 0); + else if ((now & CALI_CYCLING) && !(cali0 & CALI_CYCLING) && !(now & CALI_START)) + cali_start(k, 1); + else if (!(now & (CALI_START | CALI_CYCLING))) + k->cali_on = 0; + } else if (off == INT_CLR) { + hw(k, INT_RAW, rd(k, INT_RAW) & ~(v & 15u)); + } + update(k); + clocking(k); +} + +static void tg_reset(void *ctx) +{ + struct e32_timg *k = (struct e32_timg *)ctx; + int t; + for (t = 0; t < 3; t++) + k->value[t] = k->frac[t] = 0; + k->stage = 0; + k->wcount = k->w_frac = 0; + k->cali_on = 0; + k->cali_x = k->x_frac = 0; + k->clocked = 0; + memset(k->level, 0, sizeof k->level); + update(k); + clocking(k); +} + +const struct esk_dev_ops esk_esp32_timg_ops = { + "esp32-timg", tg_read, tg_write, tg_reset, tg_tick, tg_next, +}; + +void *esk_esp32_timg_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_timg *k; + if (strcmp(p->name, "TIMG0") && strcmp(p->name, "TIMG1")) + return 0; + k = (struct e32_timg *)esk_mach_alloc(s, sizeof *k); + if (!k) + return 0; + k->s = s; + k->p = p; + k->group = p->name[4] == '1'; + return k; +} diff --git a/core/mcu/esp32/soc/uart.c b/core/mcu/esp32/soc/uart.c new file mode 100644 index 000000000..349132885 --- /dev/null +++ b/core/mcu/esp32/soc/uart.c @@ -0,0 +1,452 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* uart.c -- the ESP32's UART0, UART1 and UART2 (ESP32 TRM v5, chapter + * 13), over the register file, at their baud rate (the ESP32-C3's model, + * mcu/esp32c3/uart.c, on the ESP32's registers). + * + * - the clock is APB_CLK, or REF_TICK's 1 MHz while CONF0's + * TICK_REF_ALWAYS_ON is clear; a bit is CLKDIV + FRAG / 16 of its + * cycles; + * - a write of FIFO (here or at its AHB address) queues a byte in the TX + * FIFO (128 bytes times MEM_CONF's TX_SIZE; a write to a full FIFO is + * lost); while nCTS lets it (TX_FLOW_EN) the transmitter sends a frame + * at a time: a start bit, 5 to 8 data bits (BIT_NUM), the parity + * (PARITY_EN, PARITY odd) and 1, 1.5 or 2 stop bits (STOP_BIT_NUM); + * frames in the FIFO go out back to back, and once it has emptied the + * line stays idle TX_IDLE_NUM bit times before the next transfer; + * TXD_BRK sends TX_BRK_NUM NULL characters once the FIFO is empty; + * - bytes arrive from the session's serial input or the RX pin into the + * RX FIFO (128 times RX_SIZE); a frame with no room is lost + * (RXFIFO_OVF); a read of FIFO takes the oldest byte; LOOPBACK sends + * the transmitter's frames to its own receiver; + * - INT_RAW's bits: RXFIFO_FULL while more than RXFIFO_FULL_THRHD bytes + * wait, TXFIFO_EMPTY while fewer than TXFIFO_EMPTY_THRHD do, + * PARITY_ERR and FRM_ERR for a received frame, RXFIFO_OVF, BRK_DET, + * RXFIFO_TOUT after RX_TOUT_THRHD times eight bit times of idle line + * with bytes waiting (RX_TOUT_EN; ESP-IDF's uart_ll converts its + * symbols so), TX_BRK_DONE, TX_BRK_IDLE_DONE, TX_DONE; INT_CLR clears + * them (a level condition sets its bit again while it lasts); INT_ST + * is INT_RAW and INT_ENA, and raises the matrix source (UART0 34, + * UART1 35, UART2 36) while nonzero; + * - STATUS reads the FIFOs' counts (with MEM_CNT_STATUS's high bits) + * and the lines; RXFIFO_RST and TXFIFO_RST empty the FIFOs while set. + * Not modelled: autobaud, IrDA, RS485, the AT_CMD character, software + * flow control (XON/XOFF), the RX glitch filter, light-sleep wake-up, + * UHCI, the FIFO RAM's sharing between the UARTs beyond its sizes. */ +#include + +#include "mcu/esp32/soc/esp32.h" + +#define BLOCK 128 /* bytes of FIFO RAM per block (TRM 26.4.2) */ +#define RAW_RXFIFO_FULL (1u << 0) +#define RAW_TXFIFO_EMPTY (1u << 1) +#define RAW_PARITY_ERR (1u << 2) +#define RAW_FRM_ERR (1u << 3) +#define RAW_RXFIFO_OVF (1u << 4) +#define RAW_BRK_DET (1u << 7) +#define RAW_RXFIFO_TOUT (1u << 8) +#define RAW_TX_BRK_DONE (1u << 12) +#define RAW_TX_BRK_IDLE_DONE (1u << 13) +#define RAW_TX_DONE (1u << 14) +#define CONF0_PARITY (1u << 0) +#define CONF0_PARITY_EN (1u << 1) +#define CONF0_TXD_BRK (1u << 8) +#define CONF0_LOOPBACK (1u << 14) +#define CONF0_TX_FLOW_EN (1u << 15) +#define CONF0_RXFIFO_RST (1u << 17) +#define CONF0_TXFIFO_RST (1u << 18) +#define CONF1_RX_TOUT_EN (1u << 31) +#define CONF0_TICK_REF (1u << 27) +#define REF_TICK_HZ 1000000.0 + +struct e32_uart { + struct esk_mach *s; + struct esk_rf_periph *p; + struct esk_rf_reg *fifo, *raw, *st, *ena, *clr, *clkdiv, *status, *conf0, *conf1, *idle, *mem, + *memcnt; + int unit, source, level; + u8 tx[4 * BLOCK], rx[2 * BLOCK]; + int ntx, nrx; + int busy; /* a frame, a break or the idle gap is on the TX line */ + int clocked; /* the device's clock runs (esk_rf_clock) */ + int phase; /* 0 a frame, 1 the idle after it, 2 a break */ + int brk_left; /* NULL characters of a break still to send */ + u64 left, since; + u64 rx_idle; /* bit times of idle RX line, for RXFIFO_TOUT */ + int rx_any; /* a byte arrived since the FIFO was last empty */ + int cts; /* nCTS high: the peer is not ready */ +}; + +static u32 reg(const struct esk_rf_reg *r) { return (u32)r->value; } + +static int tx_cap(const struct e32_uart *u) +{ + int n = (int)((reg(u->mem) >> 7) & 15u); + return (n ? (n > 8 ? 8 : n) : 1) * BLOCK; +} + +static int rx_cap(const struct e32_uart *u) +{ + int n = (int)((reg(u->mem) >> 3) & 15u); + return (n ? (n > 8 ? 8 : n) : 1) * BLOCK; +} + +/* the UART's clock, in Hz */ +static double sclk_hz(const struct e32_uart *u) +{ + return (reg(u->conf0) & CONF0_TICK_REF) ? (double)esk_esp32_apb_hz(u->s) : REF_TICK_HZ; +} + +/* a bit's time in core cycles */ +static u32 bit_cycles(const struct e32_uart *u) +{ + u32 d = reg(u->clkdiv), div = d & 0xfffffu, frag = (d >> 20) & 15u; + double per = (double)div + (double)frag / 16.0, baud, c; + if (per < 1.0) + per = 1.0; + baud = sclk_hz(u) / per; + c = (double)esk_mach_core_hz(u->s) / baud; + return c < 1.0 ? 1u : (u32)(c + 0.5); +} + +/* RXFIFO_TOUT's threshold in bit times: RX_TOUT_THRHD (with MEM_CONF's + * three high bits) times eight */ +static u64 timeout_bits(const struct e32_uart *u) +{ + u64 t = ((reg(u->conf1) >> 24) & 0x7fu) | (u64)((reg(u->mem) >> 18) & 7u) << 7; + return t * 8u; +} + +static int data_bits(const struct e32_uart *u) { return 5 + (int)((reg(u->conf0) >> 2) & 3u); } + +/* STOP_BIT_NUM: 1 one bit, 2 one and a half, 3 two */ +static int stop_halves(const struct e32_uart *u) +{ + u32 n = (reg(u->conf0) >> 4) & 3u; + return n == 2 ? 3 : n == 3 ? 4 : 2; +} + +static int nbits(const struct e32_uart *u) { return data_bits(u) + ((reg(u->conf0) & CONF0_PARITY_EN) ? 1 : 0); } + +static u32 with_parity(const struct e32_uart *u, u32 c) +{ + int n = data_bits(u), ones = 0, i; + c &= (1u << n) - 1u; + if (!(reg(u->conf0) & CONF0_PARITY_EN)) + return c; + for (i = 0; i < n; i++) + ones += (int)((c >> i) & 1u); + /* PARITY 0 even, 1 odd */ + return c | (u32)((ones & 1) ^ ((reg(u->conf0) & CONF0_PARITY) ? 1 : 0)) << n; +} + +static int parity_ok(const struct e32_uart *u, u32 bits) +{ + int n = data_bits(u); + if (!(reg(u->conf0) & CONF0_PARITY_EN)) + return 1; + return with_parity(u, bits) == (bits & ((2u << n) - 1u)); +} + +/* the level conditions, INT_ST and the matrix source */ +static void update(struct e32_uart *u) +{ + u32 raw = reg(u->raw), c1 = reg(u->conf1); + if ((u32)u->nrx > (c1 & 0x7fu)) + raw |= RAW_RXFIFO_FULL; + if ((u32)u->ntx < ((c1 >> 8) & 0x7fu)) + raw |= RAW_TXFIFO_EMPTY; + esk_rf_hw(u->raw, raw); + esk_rf_hw(u->st, raw & reg(u->ena)); + esk_rf_hw(u->status, (reg(u->status) & ~(0xffu | 0xffu << 16)) | ((u32)u->nrx & 0xffu) | + ((u32)u->ntx & 0xffu) << 16); + if (u->memcnt) + esk_rf_hw(u->memcnt, (u32)(u->nrx >> 8) | (u32)(u->ntx >> 8) << 3); + if ((reg(u->st) != 0) != u->level) { + u->level = reg(u->st) != 0; + esk_esp32_source(u->s, u->source, u->level); + } +} + +static void set_raw(struct e32_uart *u, u32 bits) +{ + esk_rf_hw(u->raw, reg(u->raw) | bits); +} + +static void receive(struct e32_uart *u, u32 bits, int framing_error, int brk); + +/* the clock runs while the line is busy or a receive timeout counts */ +static void clocking(struct e32_uart *u) +{ + int on = u->busy || (u->rx_any && (reg(u->conf1) & CONF1_RX_TOUT_EN)); + if (on != u->clocked) { + if (on) + u->since = u->s->cycles; + esk_rf_clock(u->p, &u->clocked, on); + } +} + +static void run(struct e32_uart *u, u64 cycles) +{ + u->left = cycles; + u->since = u->s->cycles; + u->busy = 1; + clocking(u); +} + +/* the next thing on the TX line: a frame, or a break once the FIFO is empty */ +static void tx_next(struct e32_uart *u) +{ + struct esk_mach *s = u->s; + u64 b; + int n; + if (u->busy) + return; + b = bit_cycles(u); + n = nbits(u); + if (u->ntx && !((reg(u->conf0) & CONF0_TX_FLOW_EN) && u->cts)) { + u32 c = u->tx[0], bits = with_parity(u, c); + memmove(u->tx, u->tx + 1, (size_t)(u->ntx - 1)); + u->ntx--; + u->phase = 0; + run(u, b * (u64)(1 + n) + (b * (u64)stop_halves(u) + 1) / 2); + if (s->host.uart_frame) + s->host.uart_frame(s->host.ctx, u->p->name, (int)(c & ((1u << data_bits(u)) - 1u)), bits, n, + stop_halves(u), (u32)b); + else if (s->host.uart_tx) + s->host.uart_tx(s->host.ctx, u->p->name, (int)c, (u32)b); + if (reg(u->conf0) & CONF0_LOOPBACK) + receive(u, bits, 0, 0); + return; + } + if (!u->ntx && u->brk_left > 0) { + u->phase = 2; + u->brk_left--; + run(u, b * (u64)(1 + n + 1)); + if (s->host.uart_frame) + s->host.uart_frame(s->host.ctx, u->p->name, -1, 0, n + 1, 2, (u32)b); + } +} + +/* ---- the receiver ------------------------------------------------------------------ */ + +static void receive(struct e32_uart *u, u32 bits, int framing_error, int brk) +{ + int n = data_bits(u); + if (reg(u->conf0) & CONF0_RXFIFO_RST) + return; + u->rx_idle = 0; + if (brk) { + set_raw(u, RAW_BRK_DET); + } else { + if (!parity_ok(u, bits)) + set_raw(u, RAW_PARITY_ERR); + if (framing_error) + set_raw(u, RAW_FRM_ERR); + if (u->nrx < rx_cap(u)) { + u->rx[u->nrx++] = (u8)(bits & ((1u << n) - 1u)); + u->rx_any = 1; + } else { + set_raw(u, RAW_RXFIFO_OVF); + } + } + clocking(u); /* the timeout counts in ticks */ + update(u); +} + +static int ur_room(void *ctx) +{ + const struct e32_uart *u = (const struct e32_uart *)ctx; + return !(reg(u->conf0) & CONF0_RXFIFO_RST); +} + +static void ur_put(void *ctx, int c) +{ + struct e32_uart *u = (struct e32_uart *)ctx; + receive(u, with_parity(u, (u32)c), 0, 0); +} + +static u32 ur_format(void *ctx) +{ + const struct e32_uart *u = (const struct e32_uart *)ctx; + return (u32)nbits(u) | (u32)stop_halves(u) << 8; +} + +static void ur_put_frame(void *ctx, u32 bits, int framing_error) +{ + struct e32_uart *u = (struct e32_uart *)ctx; + /* all zeros with a framing error: a break */ + receive(u, bits, framing_error, framing_error && !bits); +} + +static void ur_started(void *ctx) +{ + struct e32_uart *u = (struct e32_uart *)ctx; + u->rx_idle = 0; +} + +static u32 ur_bit_cycles(void *ctx) { return bit_cycles((const struct e32_uart *)ctx); } + +/* ---- the registers -------------------------------------------------------------------- */ + +static u32 ur_read(void *ctx, u32 off, int n) +{ + struct e32_uart *u = (struct e32_uart *)ctx; + if (off == esk_rf_off(u->fifo)) { + u32 v; + if (!u->nrx) + return 0; + v = u->rx[0]; + if (!u->s->bus.debug) { + memmove(u->rx, u->rx + 1, (size_t)(u->nrx - 1)); + u->nrx--; + if (!u->nrx) + u->rx_any = 0; + update(u); + } + return v; + } + return esk_rf_read(u->p, off, n); +} + +static void ur_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_uart *u = (struct e32_uart *)ctx; + if (off == esk_rf_off(u->fifo)) { + if (!(reg(u->conf0) & CONF0_TXFIFO_RST) && u->ntx < tx_cap(u)) + u->tx[u->ntx++] = (u8)v; + } else if (off == esk_rf_off(u->clr)) { + esk_rf_hw(u->raw, reg(u->raw) & ~v); + } else if (off == esk_rf_off(u->raw) || off == esk_rf_off(u->st) || off == esk_rf_off(u->status)) { + /* read only */ + } else { + u32 was0 = reg(u->conf0); + esk_rf_write(u->p, off, n, v); + if (off == esk_rf_off(u->conf0)) { + if (reg(u->conf0) & CONF0_TXFIFO_RST) + u->ntx = 0; + if (reg(u->conf0) & CONF0_RXFIFO_RST) { + u->nrx = 0; + u->rx_any = 0; + } + if ((reg(u->conf0) & CONF0_TXD_BRK) && !(was0 & CONF0_TXD_BRK)) + u->brk_left = (int)((reg(u->idle) >> 20) & 0xffu); + } + } + tx_next(u); + update(u); +} + +static void ur_tick(void *ctx, u32 cycles) +{ + struct e32_uart *u = (struct e32_uart *)ctx; + u64 b = bit_cycles(u); + cycles = esk_mach_after(u->s, cycles, u->since); + if (u->rx_any && (reg(u->conf1) & CONF1_RX_TOUT_EN)) { + u64 thr = timeout_bits(u); + u->rx_idle += cycles; + if (u->rx_idle >= thr * b && u->nrx) { + set_raw(u, RAW_RXFIFO_TOUT); + u->rx_any = 0; + update(u); + } + } + if (!u->busy) { + clocking(u); + return; + } + if (u->left > cycles) { + u->left -= cycles; + return; + } + u->left = 0; + if (u->phase == 0) { + /* the frame is out; the FIFO empty, the transfer is over: at least + * TX_IDLE_NUM bit times of idle line before the next */ + u64 idle = (reg(u->idle) >> 10) & 0x3ffu; + if (!u->ntx) + set_raw(u, RAW_TX_DONE); + if (idle && !u->ntx) { + u->phase = 1; + u->left = idle * b; + u->since = u->s->cycles; + update(u); + return; + } + } else if (u->phase == 2) { + if (u->brk_left <= 0) + set_raw(u, RAW_TX_BRK_DONE | RAW_TX_BRK_IDLE_DONE); + } + u->busy = 0; + tx_next(u); + clocking(u); + update(u); +} + +static int ur_next(void *ctx, u32 *cycles) +{ + struct e32_uart *u = (struct e32_uart *)ctx; + u64 c = u->busy ? u->left : 0; + if (u->rx_any && (reg(u->conf1) & CONF1_RX_TOUT_EN)) { + u64 thr = timeout_bits(u) * bit_cycles(u); + u64 t = thr > u->rx_idle ? thr - u->rx_idle : 1; + if (!c || t < c) + c = t; + } + if (!c) + return 0; + *cycles = c > 0xffffffffu ? 0xffffffffu : (u32)c; + return 1; +} + +static void ur_reset(void *ctx) +{ + struct e32_uart *u = (struct e32_uart *)ctx; + u->ntx = u->nrx = 0; + u->busy = 0; + u->clocked = 0; + u->left = 0; + u->brk_left = 0; + u->rx_any = 0; + u->rx_idle = 0; + u->level = 0; + u->cts = 0; + update(u); +} + +const struct esk_dev_ops esk_esp32_uart_ops = { + "esp32-uart", ur_read, ur_write, ur_reset, ur_tick, ur_next, +}; + +void *esk_esp32_uart_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_uart *c; + if (strcmp(p->name, "UART0") && strcmp(p->name, "UART1") && strcmp(p->name, "UART2")) + return 0; + c = (struct e32_uart *)esk_mach_alloc(s, sizeof *c); + if (!c) + return 0; + memset(c, 0, sizeof *c); + c->s = s; + c->p = p; + c->unit = p->name[4] - '0'; + c->source = esk_rf_irq(p, p->name); + c->fifo = esk_rf_reg(p, "FIFO"); + c->raw = esk_rf_reg(p, "INT_RAW"); + c->st = esk_rf_reg(p, "INT_ST"); + c->ena = esk_rf_reg(p, "INT_ENA"); + c->clr = esk_rf_reg(p, "INT_CLR"); + c->clkdiv = esk_rf_reg(p, "CLKDIV"); + c->status = esk_rf_reg(p, "STATUS"); + c->conf0 = esk_rf_reg(p, "CONF0"); + c->conf1 = esk_rf_reg(p, "CONF1"); + c->idle = esk_rf_reg(p, "IDLE_CONF"); + c->mem = esk_rf_reg(p, "MEM_CONF"); + c->memcnt = esk_rf_reg(p, "MEM_CNT_STATUS"); + if (!c->fifo || !c->raw || !c->st || !c->ena || !c->clr || !c->clkdiv || !c->status || !c->conf0 || + !c->conf1 || !c->idle || !c->mem) + return 0; + esk_mach_rx_port(s, p->name, ur_room, ur_put, ur_bit_cycles, c); + esk_mach_rx_frames(s, ur_format, ur_put_frame, ur_started); + return c; +} diff --git a/core/mcu/models.c b/core/mcu/models.c index a2dbc1c5f..954533580 100644 --- a/core/mcu/models.c +++ b/core/mcu/models.c @@ -5,6 +5,7 @@ #include #include "mcu/avr/avr.h" +#include "mcu/esp32/soc/esp32.h" #include "mcu/esp32c3/esp32c3.h" #include "mcu/nrf52/nrf52.h" #include "mcu/pic24/pic24.h" @@ -61,6 +62,16 @@ static const struct esk_rf_model_type model_types[] = { { "fe310-aon", &esk_fe310_aon_ops, esk_fe310_aon_create }, { "fe310-pwm", &esk_fe310_pwm_ops, esk_fe310_pwm_create }, { "fe310-spi", &esk_fe310_spi_ops, esk_fe310_spi_create }, + { "esp32-dport", &esk_esp32_dport_ops, esk_esp32_dport_create }, + { "esp32-efuse", &esk_esp32_efuse_ops, esk_esp32_efuse_create }, + { "esp32-rtc", &esk_esp32_rtc_ops, esk_esp32_rtc_create }, + { "esp32-uart", &esk_esp32_uart_ops, esk_esp32_uart_create }, + { "esp32-apbctrl", &esk_esp32_apbctrl_ops, esk_esp32_apbctrl_create }, + { "esp32-gpio", &esk_esp32_gpio_ops, esk_esp32_gpio_create }, + { "esp32-spi", &esk_esp32_spi_ops, esk_esp32_spi_create }, + { "esp32-timg", &esk_esp32_timg_ops, esk_esp32_timg_create }, + { "esp32-sha", &esk_esp32_sha_ops, esk_esp32_sha_create }, + { "esp32-iomux", &esk_esp32_iomux_ops, esk_esp32_iomux_create }, { "esp32c3-intmtx", &esk_esp32c3_intmtx_ops, esk_esp32c3_intmtx_create }, { "esp32c3-uart", &esk_esp32c3_uart_ops, esk_esp32c3_uart_create }, { "esp32c3-rtc", &esk_esp32c3_rtc_ops, esk_esp32c3_rtc_create }, diff --git a/core/mcu/rf.c b/core/mcu/rf.c index fb8fa4750..09688157d 100644 --- a/core/mcu/rf.c +++ b/core/mcu/rf.c @@ -853,6 +853,15 @@ struct esk_rf_reg *esk_rf_reg(struct esk_rf_periph *p, const char *name) return 0; } +struct esk_rf_reg *esk_rf_reg_at(struct esk_rf_periph *p, u32 off) +{ + int i; + for (i = 0; p && i < p->nreg; i++) + if (p->reg[i]->addr - p->base == off) + return p->reg[i]; + return 0; +} + u64 esk_rf_mask(const struct esk_rf_reg *r, const char *field) { int i; diff --git a/core/mcu/rf.h b/core/mcu/rf.h index 71286b003..9afc95be6 100644 --- a/core/mcu/rf.h +++ b/core/mcu/rf.h @@ -221,6 +221,8 @@ struct esk_rf_periph *esk_rf_periph_at(struct esk_rf *rf, int i); * answer is kept, as a model's context does not move once created */ void *esk_rf_ctx_of(struct esk_rf *rf, const void *ops); struct esk_rf_reg *esk_rf_reg(struct esk_rf_periph *p, const char *name); +/* the register at offset `off` from the peripheral's base, or 0 */ +struct esk_rf_reg *esk_rf_reg_at(struct esk_rf_periph *p, u32 off); /* the bits of the register's field of that name, or 0 */ u64 esk_rf_mask(const struct esk_rf_reg *r, const char *field); /* the program's read and write, as the description says the fields behave */ diff --git a/core/mcu/xtensa/lx6.c b/core/mcu/xtensa/lx6.c new file mode 100644 index 000000000..f6df523be --- /dev/null +++ b/core/mcu/xtensa/lx6.c @@ -0,0 +1,2244 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* lx6.c -- the ESP32's Xtensa LX6 cores (Cadence's Xtensa Instruction Set + * Architecture Reference Manual; the configuration of Espressif's + * core-isa.h for the ESP32, esp32_v3_49_prod, LX6.0.3), two of them as + * the chip's PRO_CPU and APP_CPU behind the machine's one core interface. + * + * The configuration, as core-isa.h states it: + * - the core instructions with the density (16-bit) instructions, + * zero-overhead loops, NSA/NSAU, MIN/MAX, SEXT, CLAMPS, MUL16, MULL, + * MULUH/MULSH, QUOS/QUOU/REMS/REMU, ADDX/SUBX, ABS, L32AI/S32RI, + * S32C1I with SCOMPARE1 and ATOMCTL, booleans (16), THREADPTR, four + * MISC registers, PRID (0xCDCD on PRO_CPU, 0xABAB on APP_CPU), the + * external registers' RER/WER, the MAC16 package and the single + * precision floating-point coprocessor (CP0, lx6fp.c); + * - the windowed registers: 64 physical, WindowBase and WindowStart, + * CALL4/8/12, ENTRY, RETW, MOVSP, ROTW, the window overflow check of + * every instruction while PS.WOE is set and PS.EXCM clear (the frame + * of the first live window above the registers it names spilled by + * the WindowOverflow4/8/12 vector), RETW's underflow, RFWO/RFWU, and + * L32E/S32E for the handlers; + * - the exception architecture XEA2: EPC1, EXCCAUSE, EXCVADDR, the + * kernel, user and double exception vectors, DEPC; relocatable + * vectors (VECBASE, 0x40000000 at reset); + * - 32 interrupts at core-isa.h's levels (1-5, the debug level 6, the + * NMI at 7) and types (level, edge, software 7 and 29, timers 6, 15 + * and 16 from CCOMPARE0-2 against CCOUNT, profiling 11), INTERRUPT, + * INTSET, INTCLEAR, INTENABLE, EXCMLEVEL 3, RSIL, WAITI, RFI; + * - the debug option's BREAK, BREAK.N, two IBREAKs, two DBREAKs and + * ICOUNT, raising the debug exception (level 6) with DEBUGCAUSE; + * - region protection: eight 512 MB regions in each of the instruction + * and data TLBs, attribute 2 at reset, 15 a region no access reaches + * (InstFetchProhibited, LoadProhibited, StoreProhibited); + * - unaligned loads and stores done by the hardware (no alignment + * exception); the ESP32's instruction bus (0x40000000-0x40BFFFFF: + * ROM, IRAM, the flash's instruction window) takes 32-bit aligned + * loads and stores only, others raising LoadStoreError, as the + * chip's TRM says (chapter 1.3.2.2); + * - no MMU, no Xtensa caches (the cache instructions do nothing), one + * ring, MEMCTL's loop buffer as storage (it changes no result). + * An access nothing answers raises the PIF address error (14 for a + * fetch, 15 for a load or store), and is reported (esk_mach_bus_error). + * + * Where it differs inside: each instruction takes an estimated time (one + * cycle, a taken branch, jump, call or return three, a load one, MULL + * and the high products two, a division twelve, an exception's entry + * three); the pipeline, its interlocks and the loop buffer's timing are + * not modelled. CCOUNT counts those cycles. + * + * Two cores share the machine as mcu/cortexm/smp.c's do: each keeps its + * own time, the one furthest behind runs next, the devices see the + * earliest. APP_CPU starts held in reset, its clock gated, until the + * part's DPORT model releases it (esk_lx6_core_reset, _stall). + * + * Written for EmbSIM from the ISA reference and core-isa.h; it shares no + * code with the experimental engine in windows.c and execute.c, whose + * notes on the ESP32's interrupt levels and types it agrees with. */ +#include +#include +#include +#include + +#include "mcu/xtensa/lx6.h" + +#define NCORES 2 + +/* PS */ +#define PS_INTLEVEL 0xfu +#define PS_EXCM 0x10u +#define PS_UM 0x20u +#define PS_OWB_SHIFT 8 +#define PS_OWB (0xfu << PS_OWB_SHIFT) +#define PS_CALLINC_SHIFT 16 +#define PS_CALLINC (3u << PS_CALLINC_SHIFT) +#define PS_WOE 0x40000u +#define PS_MASK 0x00070f3fu + +/* EXCCAUSE */ +#define EXC_ILLEGAL 0u +#define EXC_SYSCALL 1u +#define EXC_LOADSTORE 3u +#define EXC_LEVEL1 4u +#define EXC_ALLOCA 5u +#define EXC_DIVZERO 6u +#define EXC_IFETCH_ADDR 14u +#define EXC_LS_ADDR 15u +#define EXC_IFETCH_PROHIBITED 20u +#define EXC_LOAD_PROHIBITED 28u +#define EXC_STORE_PROHIBITED 29u +#define EXC_CP0_DISABLED 32u + +/* DEBUGCAUSE */ +#define DBG_ICOUNT 0x1u +#define DBG_IBREAK 0x2u +#define DBG_DBREAK 0x4u +#define DBG_BREAK 0x8u +#define DBG_BREAKN 0x10u + +/* the interrupts' types and levels (core-isa.h) */ +#define INT_SOFTWARE 0x20000080u +#define INT_EDGE 0x50400400u +#define INT_NMI 0x00004000u +#define INT_LATCHED (INT_SOFTWARE | INT_EDGE | INT_NMI) +static const u32 level_mask[8] = { 0, 0x000637ffu, 0x00380000u, 0x28c08800u, 0x53000000u, + 0x84010000u, 0, 0x00004000u }; +static const int timer_int[3] = { 6, 15, 16 }; +#define EXCM_LEVEL 3u +#define DEBUG_LEVEL 6u + +/* the vectors' offsets from VECBASE */ +#define VEC_OF4 0x000u +#define VEC_UF4 0x040u +#define VEC_OF8 0x080u +#define VEC_UF8 0x0c0u +#define VEC_OF12 0x100u +#define VEC_UF12 0x140u +static const u32 level_vec[8] = { 0, 0, 0x180u, 0x1c0u, 0x200u, 0x240u, 0x280u, 0x2c0u }; +#define VEC_KERNEL 0x300u +#define VEC_USER 0x340u +#define VEC_DOUBLE 0x3c0u + +#define CONFIGID0 0xC2BCFFFEu +#define CONFIGID1 0x1CC5FE96u + +struct smp; + +struct lx6 { + struct esk_cpu cpu; /* first */ + struct esk_mach *m; + struct smp *x; + int id; + u32 ar[64]; + u32 pc, npc; + u32 wb, ws; /* WindowBase, WindowStart */ + u32 ps, sar, lbeg, lend, lcount, br, scompare1; + u32 acclo, acchi, mr[4]; + u32 epc[8], eps[8], excsave[8], depc, exccause, excvaddr, debugcause; + u32 intenable, lines, latched; + u32 vecbase, ccompare[3]; + u64 ccount_at; /* the core's time CCOUNT counts from */ + u32 ccount_base; + u32 cpenable, threadptr, fcr, fsr, f[16], misc[4], prid, atomctl, memctl; + u32 expstate, f64r_lo, f64r_hi, f64s; /* the ESP32's double-precision accelerator's state */ + u32 ibreakenable, ibreaka[2], dbreaka[2], dbreakc[2], icount, icountlevel, ddr; + u32 itlb[8], dtlb[8]; + u32 reset_vector; + /* the core's own view of read-only memory, ahead of the bus (the + * ESP32's APP_CPU's ROM): base, size and bytes */ + struct { + u32 base, size; + const u8 *mem; + } view[2]; + int nview; + int exc; /* the instruction took an exception: nothing more of it */ + int jumped; /* it branched, jumped, called or returned: no loop-back */ + int waiti; /* waiting in WAITI */ + u32 cost; + char xml[1]; /* no target description */ +}; + +enum { CORE_RUN, CORE_SLEEP, CORE_HELD, CORE_STALLED }; + +struct smp { + struct esk_cpu cpu; /* first */ + struct esk_mach *m; + int n; + struct lx6 *c[NCORES]; + int state[NCORES]; + int held[NCORES], stalled[NCORES]; + u64 lt[NCORES]; + int cur, stepping; + int running; +}; + +/* ---- registers -------------------------------------------------------- */ + +#define AR(c, i) ((c)->ar[((c)->wb * 4u + (u32)(i)) & 63u]) + +static u32 sext(u32 v, int bits) +{ + u32 b = 1u << (bits - 1); + v &= (b << 1) - 1u; + return (v ^ b) - b; +} + +/* the core's time: the machine's while its instruction runs */ +static u64 now(const struct lx6 *c) +{ + return c->m->cycles; +} + +static u32 ccount(const struct lx6 *c) +{ + return c->ccount_base + (u32)(now(c) - c->ccount_at); +} + +static u32 interrupt_reg(const struct lx6 *c) +{ + return (c->lines & ~INT_LATCHED) | c->latched; +} + +/* WindowStart turned so that bit 0 is WindowBase's */ +static u32 ws_rot(const struct lx6 *c) +{ + u32 w = c->ws | c->ws << 16; + return (w >> c->wb) & 0xffffu; +} + +/* ---- exceptions ------------------------------------------------------- */ + +static void to(struct lx6 *c, u32 pc) +{ + c->npc = pc; + c->exc = 1; +} + +static void exception(struct lx6 *c, u32 cause) +{ + c->exccause = cause; + if (c->ps & PS_EXCM) { + c->depc = c->pc; + to(c, c->vecbase + VEC_DOUBLE); + } else { + c->epc[1] = c->pc; + to(c, c->vecbase + ((c->ps & PS_UM) ? VEC_USER : VEC_KERNEL)); + c->ps |= PS_EXCM; + } + c->cost += 2; + esk_mach_exc(c->m, c->id, (int)cause, c->pc); +} + +static void mem_exception(struct lx6 *c, u32 cause, u32 a) +{ + c->excvaddr = a; + exception(c, cause); +} + +void esk_lx6_illegal(struct lx6 *c) +{ + exception(c, EXC_ILLEGAL); +} + +/* a high-priority interrupt or the debug exception at `level` */ +static void level_entry(struct lx6 *c, u32 level, u32 epc) +{ + c->epc[level] = epc; + c->eps[level] = c->ps; + c->ps = (c->ps & ~PS_INTLEVEL) | level | PS_EXCM; + to(c, c->vecbase + level_vec[level]); + c->cost += 2; +} + +static void debug_exception(struct lx6 *c, u32 cause) +{ + if ((c->ps & PS_INTLEVEL) >= DEBUG_LEVEL) + return; + c->debugcause = cause; + level_entry(c, DEBUG_LEVEL, c->pc); + esk_mach_exc(c->m, c->id, 64 + (int)DEBUG_LEVEL, c->pc); +} + +/* the window overflow check: registers up to `hi` must be the frame's */ +static int win(struct lx6 *c, u32 hi) +{ + u32 n, w, owb, k; + if (hi < 4 || (c->ps & (PS_WOE | PS_EXCM)) != PS_WOE) + return 0; + w = ws_rot(c) >> 1; + if (!(w & ((1u << (hi >> 2)) - 1u))) + return 0; + /* the first live frame above is spilled: rotate to it */ + for (n = 1; !(w & 1u); n++) + w >>= 1; + w >>= 1; + owb = c->wb; + c->wb = (c->wb + n) & 15u; + c->ps = (c->ps & ~PS_OWB) | owb << PS_OWB_SHIFT | PS_EXCM; + c->epc[1] = c->pc; + for (k = 0; k < 3 && !(w & 1u); k++) + w >>= 1; + to(c, c->vecbase + (k == 0 ? VEC_OF4 : k == 1 ? VEC_OF8 : VEC_OF12)); + c->cost += 2; + return 1; +} + +/* ---- memory ----------------------------------------------------------- */ + +static int prohibited(u32 attr) +{ + return attr == 15u; +} + +/* the ESP32's instruction bus: 32-bit aligned data accesses only */ +static int ibus_narrow(u32 a, int n) +{ + return a >= 0x40000000u && a < 0x40c00000u && (n != 4 || (a & 3u)); +} + +static int dbreak_hit(struct lx6 *c, u32 a, int n, int store) +{ + int i; + for (i = 0; i < 2; i++) { + u32 ctl = c->dbreakc[i], mask; + if (!(ctl & (store ? 0x80000000u : 0x40000000u))) + continue; + mask = ~(ctl & 0x3fu); + if (((a ^ c->dbreaka[i]) & mask) == 0 || + (((a + (u32)n - 1u) ^ c->dbreaka[i]) & mask) == 0) { + if ((c->ps & PS_INTLEVEL) < DEBUG_LEVEL) { + c->debugcause = DBG_DBREAK | (u32)i << 8; + level_entry(c, DEBUG_LEVEL, c->pc); + return 1; + } + } + } + return 0; +} + +int esk_lx6_load(struct lx6 *c, u32 a, int n, u32 *v) +{ + struct esk_bus *b = &c->m->bus; + struct esk_region *r; + int i; + *v = 0; + if (prohibited(c->dtlb[a >> 29])) { + mem_exception(c, EXC_LOAD_PROHIBITED, a); + return -1; + } + if (ibus_narrow(a, n)) { + mem_exception(c, EXC_LOADSTORE, a); + return -1; + } + if (b->nwatch && esk_bus_watch_check(b, a, n, 0)) { + c->m->yield = 1; + c->exc = 2; /* not run: the debugger stops before it */ + return -1; + } + if ((c->dbreakc[0] | c->dbreakc[1]) && dbreak_hit(c, a, n, 0)) + return -1; + for (i = 0; i < c->nview; i++) + if (a - c->view[i].base < c->view[i].size && c->view[i].size - (a - c->view[i].base) >= (u32)n) { + const u8 *p = c->view[i].mem + (a - c->view[i].base); + u32 x = 0; + int j; + for (j = n - 1; j >= 0; j--) + x = x << 8 | p[j]; + *v = x; + return 0; + } + r = esk_bus_region(b, a, (u32)n); + if (r) { + const u8 *p = r->mem + (a - r->base); + u32 x = 0; + for (i = n - 1; i >= 0; i--) + x = x << 8 | p[i]; + *v = x; + if (b->trace) + esk_bus_traced(b, a, n, 0, x, 0); + return 0; + } + for (i = 0; i < n;) { + u32 x; + int k = n - i >= 4 && !((a + (u32)i) & 3u) ? 4 : n - i >= 2 && !((a + (u32)i) & 1u) ? 2 : 1; + if (esk_bus_read(b, a + (u32)i, k, &x)) { + esk_bus_traced(b, a + (u32)i, k, 0, 0, 1); + esk_mach_bus_error(c->m, a, n, 0); + mem_exception(c, EXC_LS_ADDR, a); + return -1; + } + esk_bus_traced(b, a + (u32)i, k, 0, x, 0); + *v |= x << (8 * i); + i += k; + } + return 0; +} + +int esk_lx6_store(struct lx6 *c, u32 a, int n, u32 v) +{ + struct esk_bus *b = &c->m->bus; + struct esk_region *r; + int i; +#ifdef LX6_DEBUG_TRACE + if (getenv("LX6_WATCH") && a == (u32)strtoul(getenv("LX6_WATCH"), 0, 16)) + fprintf(stderr, "WATCH core %d pc %08x writes %08x a0=%08x\n", c->id, (unsigned)c->pc, (unsigned)v, (unsigned)AR(c, 0)); +#endif + if (prohibited(c->dtlb[a >> 29])) { + mem_exception(c, EXC_STORE_PROHIBITED, a); + return -1; + } + if (ibus_narrow(a, n)) { + mem_exception(c, EXC_LOADSTORE, a); + return -1; + } + if (b->nwatch && esk_bus_watch_check(b, a, n, 1)) { + c->m->yield = 1; + c->exc = 2; + return -1; + } + if ((c->dbreakc[0] | c->dbreakc[1]) && dbreak_hit(c, a, n, 1)) + return -1; + r = esk_bus_region(b, a, (u32)n); + if (r) { + if (!r->rom) { + u8 *p = r->mem + (a - r->base); + for (i = 0; i < n; i++) + p[i] = (u8)(v >> (8 * i)); + } + if (b->trace) + esk_bus_traced(b, a, n, 1, v, 0); + return 0; + } + for (i = 0; i < n;) { + int k = n - i >= 4 && !((a + (u32)i) & 3u) ? 4 : n - i >= 2 && !((a + (u32)i) & 1u) ? 2 : 1; + u32 x = v >> (8 * i); + if (k < 4) + x &= (1u << (8 * k)) - 1u; + if (esk_bus_write(b, a + (u32)i, k, x)) { + esk_bus_traced(b, a + (u32)i, k, 1, x, 1); + esk_mach_bus_error(c->m, a, n, 1); + mem_exception(c, EXC_LS_ADDR, a); + return -1; + } + esk_bus_traced(b, a + (u32)i, k, 1, x, 0); + i += k; + } + return 0; +} + +/* the instruction's bytes at pc: 0, or -1 (nothing answers) */ +static int fetch(struct lx6 *c, u32 pc, u32 *w) +{ + struct esk_bus *b = &c->m->bus; + struct esk_region *r; + u32 lo, hi = 0; + int i; + for (i = 0; i < c->nview; i++) + if (pc - c->view[i].base < c->view[i].size && c->view[i].size - (pc - c->view[i].base) >= 3u) { + const u8 *p = c->view[i].mem + (pc - c->view[i].base); + *w = (u32)p[0] | (u32)p[1] << 8 | (u32)p[2] << 16; + return 0; + } + r = esk_bus_region(b, pc, 3); + if (r) { + const u8 *p = r->mem + (pc - r->base); + *w = (u32)p[0] | (u32)p[1] << 8 | (u32)p[2] << 16; + return 0; + } + r = esk_bus_region(b, pc, 2); + if (r) { /* a narrow instruction at a region's end */ + const u8 *p = r->mem + (pc - r->base); + *w = (u32)p[0] | (u32)p[1] << 8; + if ((p[0] & 15u) < 8u) { + if (esk_bus_read(b, pc + 2u, 1, &hi)) + return -1; + *w |= (hi & 0xffu) << 16; + } + return 0; + } + if (esk_bus_read(b, pc & ~3u, 4, &lo)) + return -1; + if ((pc & 3u) >= 2u) { + u32 need = (pc & 3u) == 3u ? 3u : ((lo >> 16) & 15u) < 8u ? 3u : 2u; + if (need > 4u - (pc & 3u) && esk_bus_read(b, (pc & ~3u) + 4u, 4, &hi)) + return -1; + } + *w = (u32)(((u64)hi << 32 | lo) >> (8 * (pc & 3u))) & 0xffffffu; + return 0; +} + +/* ---- special registers ------------------------------------------------ */ + +static void timer_check(struct lx6 *c, u32 from, u32 cycles) +{ + int i; + for (i = 0; i < 3; i++) { + u32 d = c->ccompare[i] - from; + if (d && d <= cycles) + c->latched |= 1u << timer_int[i]; + } +} + +static void set_ccount(struct lx6 *c, u32 v) +{ + c->ccount_base = v; + c->ccount_at = now(c); +} + +/* RSR: 0, or -1 for no such register */ +static int rsr(struct lx6 *c, u32 sr, u32 *v) +{ + switch (sr) { + case 0: *v = c->lbeg; return 0; + case 1: *v = c->lend; return 0; + case 2: *v = c->lcount; return 0; + case 3: *v = c->sar; return 0; + case 4: *v = c->br; return 0; + case 12: *v = c->scompare1; return 0; + case 16: *v = c->acclo; return 0; + case 17: *v = sext(c->acchi, 8); return 0; + case 32: case 33: case 34: case 35: *v = c->mr[sr - 32]; return 0; + case 72: *v = c->wb; return 0; + case 73: *v = c->ws; return 0; + case 96: *v = c->ibreakenable; return 0; + case 97: *v = c->memctl; return 0; + case 99: *v = c->atomctl; return 0; + case 104: *v = c->ddr; return 0; + case 128: case 129: *v = c->ibreaka[sr - 128]; return 0; + case 144: case 145: *v = c->dbreaka[sr - 144]; return 0; + case 160: case 161: *v = c->dbreakc[sr - 160]; return 0; + case 176: *v = CONFIGID0; return 0; + case 208: *v = CONFIGID1; return 0; + case 192: *v = c->depc; return 0; + case 224: *v = c->cpenable; return 0; + case 226: *v = interrupt_reg(c); return 0; + case 228: *v = c->intenable; return 0; + case 230: *v = c->ps; return 0; + case 231: *v = c->vecbase; return 0; + case 232: *v = c->exccause; return 0; + case 233: *v = c->debugcause; return 0; + case 234: *v = ccount(c); return 0; + case 235: *v = c->prid; return 0; + case 236: *v = c->icount; return 0; + case 237: *v = c->icountlevel; return 0; + case 238: *v = c->excvaddr; return 0; + case 240: case 241: case 242: *v = c->ccompare[sr - 240]; return 0; + case 244: case 245: case 246: case 247: *v = c->misc[sr - 244]; return 0; + } + if (sr >= 177 && sr <= 183) { + *v = c->epc[sr - 176]; + return 0; + } + if (sr >= 194 && sr <= 199) { + *v = c->eps[sr - 192]; + return 0; + } + if (sr >= 209 && sr <= 215) { + *v = c->excsave[sr - 208]; + return 0; + } + return -1; +} + +static int wsr(struct lx6 *c, u32 sr, u32 v) +{ + switch (sr) { + case 0: c->lbeg = v; return 0; + case 1: c->lend = v; return 0; + case 2: c->lcount = v; return 0; + case 3: c->sar = v & 0x3fu; return 0; + case 4: c->br = v & 0xffffu; return 0; + case 12: c->scompare1 = v; return 0; + case 16: c->acclo = v; return 0; + case 17: c->acchi = v & 0xffu; return 0; + case 32: case 33: case 34: case 35: c->mr[sr - 32] = v; return 0; + case 72: c->wb = v & 15u; return 0; + case 73: c->ws = v & 0xffffu; return 0; + case 96: c->ibreakenable = v & 3u; return 0; + case 97: c->memctl = v; return 0; + case 99: c->atomctl = v & 0x3fu; return 0; + case 104: c->ddr = v; return 0; + case 128: case 129: c->ibreaka[sr - 128] = v; return 0; + case 144: case 145: c->dbreaka[sr - 144] = v; return 0; + case 160: case 161: c->dbreakc[sr - 160] = v & 0xc000003fu; return 0; + case 192: c->depc = v; return 0; + case 224: c->cpenable = v & 0xffu; return 0; + case 226: c->latched |= v & INT_SOFTWARE; return 0; /* INTSET */ + case 227: c->latched &= ~(v & (INT_SOFTWARE | INT_EDGE)); return 0; /* INTCLEAR */ + case 228: c->intenable = v; return 0; + case 230: c->ps = v & PS_MASK; return 0; + case 231: c->vecbase = v & ~0x3ffu; return 0; + case 232: c->exccause = v & 0x3fu; return 0; + case 233: return 0; /* DEBUGCAUSE: read-only */ + case 234: set_ccount(c, v); return 0; + case 235: return 0; /* PRID: read-only */ + case 236: c->icount = v; return 0; + case 237: c->icountlevel = v & 15u; return 0; + case 238: c->excvaddr = v; return 0; + case 240: case 241: case 242: + c->ccompare[sr - 240] = v; + c->latched &= ~(1u << timer_int[sr - 240]); + return 0; + case 244: case 245: case 246: case 247: c->misc[sr - 244] = v; return 0; + } + if (sr >= 177 && sr <= 183) { + c->epc[sr - 176] = v; + return 0; + } + if (sr >= 194 && sr <= 199) { + c->eps[sr - 192] = v & PS_MASK; + return 0; + } + if (sr >= 209 && sr <= 215) { + c->excsave[sr - 208] = v; + return 0; + } + if (sr == 176 || sr == 208) + return 0; /* CONFIGID: read-only */ + return -1; +} + +/* the user registers: THREADPTR, the FPU's FCR and FSR, and the ESP32's + * EXPSTATE and double-precision accelerator registers F64R_LO, F64R_HI, + * F64S (core-isa.h's XCHAL_HAVE_DFP_ACCEL; Espressif's xtensa-modules) */ +static u32 *dfp_ur(struct lx6 *c, u32 ur) +{ + switch (ur) { + case 230: return &c->expstate; + case 234: return &c->f64r_lo; + case 235: return &c->f64r_hi; + case 236: return &c->f64s; + } + return 0; +} + +static int rur(struct lx6 *c, u32 ur, u32 *v) +{ + if (ur == 231) { + *v = c->threadptr; + return 0; + } + if (dfp_ur(c, ur)) { + *v = *dfp_ur(c, ur); + return 0; + } + if (ur == 232 || ur == 233) { + if (!(c->cpenable & 1u)) { + exception(c, EXC_CP0_DISABLED); + return 1; + } + *v = ur == 232 ? c->fcr : c->fsr; + return 0; + } + return -1; +} + +static int wur(struct lx6 *c, u32 ur, u32 v) +{ + if (ur == 231) { + c->threadptr = v; + return 0; + } + if (dfp_ur(c, ur)) { + *dfp_ur(c, ur) = v; + return 0; + } + if (ur == 232 || ur == 233) { + if (!(c->cpenable & 1u)) { + exception(c, EXC_CP0_DISABLED); + return 1; + } + if (ur == 232) + c->fcr = v & 0x7fu; + else + c->fsr = v & 0xf80u; + return 0; + } + return -1; +} + +/* ---- the instructions ------------------------------------------------- */ + +#define OP0(w) ((w) & 15u) +#define FT(w) (((w) >> 4) & 15u) +#define FS(w) (((w) >> 8) & 15u) +#define FR(w) (((w) >> 12) & 15u) +#define OP1(w) (((w) >> 16) & 15u) +#define OP2(w) (((w) >> 20) & 15u) +#define IMM8(w) (((w) >> 16) & 255u) + +static const u32 b4const[16] = { 0xffffffffu, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 }; +static const u32 b4constu[16] = { 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256 }; + +static u32 max3(u32 a, u32 b, u32 c) +{ + u32 m = a > b ? a : b; + return m > c ? m : c; +} + +static void branch(struct lx6 *c, int taken, u32 target) +{ + if (taken) { + c->npc = target; + c->jumped = 1; + c->cost += 2; + } +} + +/* a call: return address and CALLINC, then the target */ +static void call(struct lx6 *c, u32 n, u32 target, u32 len) +{ + if (n) { + AR(c, n * 4u) = n << 30 | ((c->pc + len) & 0x3fffffffu); + c->ps = (c->ps & ~PS_CALLINC) | n << PS_CALLINC_SHIFT; + } else { + AR(c, 0) = c->pc + len; + } + c->npc = target; + c->jumped = 1; + c->cost += 2; +} + +static void retw(struct lx6 *c) +{ + u32 a0 = AR(c, 0), n = a0 >> 30, owb = c->wb, m = 0, k; + for (k = 1; k <= 3; k++) + if ((c->ws >> ((c->wb - k) & 15u)) & 1u) { + m = k; + break; + } + if (n == 0 || (m != 0 && m != n) || (c->ps & (PS_WOE | PS_EXCM)) != PS_WOE) { + esk_lx6_illegal(c); + return; + } + c->wb = (c->wb - n) & 15u; + c->cost += 2; + if ((c->ws >> c->wb) & 1u) { + c->ws &= ~(1u << owb); + c->jumped = 1; + c->npc = (c->pc & 0xc0000000u) | (a0 & 0x3fffffffu); + } else { + /* the caller's frame was spilled: the underflow handler brings + * it back, and RETW runs again */ + c->ps = (c->ps & ~PS_OWB) | owb << PS_OWB_SHIFT | PS_EXCM; + c->epc[1] = c->pc; + to(c, c->vecbase + (n == 1 ? VEC_UF4 : n == 2 ? VEC_UF8 : VEC_UF12)); + } +} + +static void entry(struct lx6 *c, u32 s, u32 imm) +{ + u32 callinc = (c->ps & PS_CALLINC) >> PS_CALLINC_SHIFT, v; + if (s > 3 || (c->ps & (PS_WOE | PS_EXCM)) != PS_WOE) { + esk_lx6_illegal(c); + return; + } + if (win(c, callinc * 4u + s)) + return; + v = AR(c, s) - imm; + AR(c, callinc * 4u + s) = v; + c->wb = (c->wb + callinc) & 15u; + c->ws |= 1u << c->wb; +} + +static void rfwo(struct lx6 *c, int underflow) +{ + if (underflow) + c->ws |= 1u << c->wb; + else + c->ws &= ~(1u << c->wb); + c->wb = (c->ps & PS_OWB) >> PS_OWB_SHIFT; + c->ps &= ~PS_EXCM; + c->npc = c->epc[1]; + c->cost += 2; +} + +static u32 nsa(u32 v) +{ + u32 n = 0; + v ^= (u32)((s32)v >> 31); + if (!v) + return 31; + while (!(v & 0x80000000u)) { + v <<= 1; + n++; + } + return n - 1u; +} + +static u32 nsau(u32 v) +{ + u32 n = 0; + if (!v) + return 32; + while (!(v & 0x80000000u)) { + v <<= 1; + n++; + } + return n; +} + +/* the external registers (RER/WER): the debug, trace and performance + * monitor blocks, which no one drives here: reads are 0 */ +static u32 rer(struct lx6 *c, u32 a) +{ + ES_UNUSED(c); + ES_UNUSED(a); + return 0; +} + +/* the MAC16 package: 16 x 16-bit products of the operands' halves into + * the 40-bit accumulator ACCHI:ACCLO (UMUL, MUL: set; MULA: add; MULS: + * subtract), the operands from AR (A) or M0-M3 (D), and the forms that + * load an M register meanwhile (LDINC, LDDEC: the address register moves + * by 4 first). op2: 0 DD.LDINC, 1 DD.LDDEC, 2 DD, 3 AD, 4 DA.LDINC, + * 5 DA.LDDEC, 6 DA, 7 AA, 8 LDINC, 9 LDDEC; op1: the operation (bits 3:2) + * and the halves (bit 0 the first operand's high half, bit 1 the + * second's) */ +static void mac16(struct lx6 *c, u32 w) +{ + u32 op2 = OP2(w), op1 = OP1(w), r = FR(w), s = FS(w), t = FT(w); + u32 x, y, oper = op1 >> 2, lda = 0, ldv = 0, hi = 0; + int ld = op2 <= 1 || op2 == 4 || op2 == 5 || op2 == 8 || op2 == 9; + int dec = op2 == 1 || op2 == 5 || op2 == 9; + int first_m = op2 <= 2 || (op2 >= 4 && op2 <= 6); + int second_m = op2 <= 3; + s64 acc, p; + if (op2 > 9 || (op2 >= 8 && (op1 || t)) || (op2 < 8 && oper == 0 && op2 != 7)) { + esk_lx6_illegal(c); + return; + } + if (op2 < 8) { + if (!first_m) + hi = s; + if (!second_m) + hi = t > hi ? t : hi; + } + if (ld) + hi = s > hi ? s : hi; + if (win(c, hi)) + return; + if (ld) { + lda = AR(c, s) + (dec ? (u32)-4 : 4u); + if (esk_lx6_load(c, lda, 4, &ldv)) + return; + } + if (op2 < 8) { + x = first_m ? c->mr[(r >> 2) & 1u] : AR(c, s); + y = second_m ? c->mr[2u + ((t >> 2) & 1u)] : AR(c, t); + x = (op1 & 1u) ? x >> 16 : x & 0xffffu; + y = (op1 & 2u) ? y >> 16 : y & 0xffffu; + if (oper == 0) + p = (s64)((u64)(x & 0xffffu) * (u64)(y & 0xffffu)); + else + p = (s64)(s32)sext(x, 16) * (s64)(s32)sext(y, 16); + acc = (s64)(((u64)(c->acchi & 0xffu) << 32 | c->acclo) << 24) >> 24; + acc = oper <= 1 ? p : oper == 2 ? acc + p : acc - p; + c->acclo = (u32)(u64)acc; + c->acchi = (u32)((u64)acc >> 32) & 0xffu; + } + if (ld) { + c->mr[r & 3u] = ldv; + AR(c, s) = lda; + } +} + +/* the ESP32's double-precision accelerator instructions (F64ITER, + * F64RND, F64ADDC, F64SUBC, F64SIG, F64CMPL, F64CMPH, F64NORM, F64SEXP, + * RF64R: Espressif's xtensa-modules): Espressif publishes their encodings, + * not what they do, so the run ends here rather than guessing */ +static void dfp(struct lx6 *c, u32 w) +{ + esk_mach_end(c->m, ESK_MACH_LOCKUP, + "core %d at 0x%08x: the double-precision accelerator's instruction 0x%06x is not modelled", + c->id, (unsigned)c->pc, (unsigned)w); + c->exc = 1; + c->npc = c->pc; +} + +static int cp0(struct lx6 *c) +{ + if (c->cpenable & 1u) + return 0; + exception(c, EXC_CP0_DISABLED); + return 1; +} + +/* RST0's ST0: the calls through a register, returns, syncs, the returns + * from exceptions, BREAK, SYSCALL, RSIL, WAITI and the boolean groups */ +static void st0(struct lx6 *c, u32 w) +{ + u32 r = FR(w), s = FS(w), t = FT(w), v; + switch (r) { + case 0: { /* SNM0 */ + u32 m = t >> 2, n = t & 3u; + if (m == 0 && n == 0) { + esk_lx6_illegal(c); + } else if (m == 2 && n == 0) { /* RET */ + if (win(c, 0)) + return; + c->npc = AR(c, 0); + c->jumped = 1; + c->cost += 2; + } else if (m == 2 && n == 1) { /* RETW */ + retw(c); + } else if (m == 2 && n == 2) { /* JX */ + if (win(c, s)) + return; + c->npc = AR(c, s); + c->jumped = 1; + c->cost += 2; + } else if (m == 3) { /* CALLX0, 4, 8, 12 */ + if (win(c, s > n * 4u ? s : n * 4u)) + return; + v = AR(c, s); + call(c, n, v, 3); + } else { + esk_lx6_illegal(c); + } + return; + } + case 1: /* MOVSP at, as */ + if (win(c, s > t ? s : t)) + return; + if (!(((c->ws >> ((c->wb - 1u) & 15u)) | (c->ws >> ((c->wb - 2u) & 15u)) | + (c->ws >> ((c->wb - 3u) & 15u))) & 1u)) { + exception(c, EXC_ALLOCA); + return; + } + AR(c, t) = AR(c, s); + return; + case 2: /* SYNC: ISYNC RSYNC ESYNC DSYNC EXCW MEMW EXTW NOP */ + if (s || (t > 3 && t != 8 && t != 12 && t != 13 && t != 15)) + esk_lx6_illegal(c); + return; + case 3: /* RFEI */ + if (t == 0) { + switch (s) { + case 0: /* RFE */ + c->ps &= ~PS_EXCM; + c->npc = c->epc[1]; + c->cost += 2; + esk_mach_exc_return(c->m, c->id); + return; + case 1: /* RFUE: XEA1 only */ + esk_lx6_illegal(c); + return; + case 2: /* RFDE */ + c->npc = c->depc; + c->cost += 2; + esk_mach_exc_return(c->m, c->id); + return; + case 4: rfwo(c, 0); return; + case 5: rfwo(c, 1); return; + } + } else if (t == 1 && s >= 2 && s <= 7) { /* RFI level */ + c->ps = c->eps[s]; + c->npc = c->epc[s]; + c->cost += 2; + esk_mach_exc_return(c->m, c->id); + return; + } + esk_lx6_illegal(c); + return; + case 4: /* BREAK s, t */ + debug_exception(c, DBG_BREAK); + return; + case 5: /* SYSCALL, SIMCALL (no simulator: nothing) */ + if (t == 0 && s == 0) + exception(c, EXC_SYSCALL); + else if (!(t == 0 && s == 1)) + esk_lx6_illegal(c); + return; + case 6: /* RSIL at, level */ + if (win(c, t)) + return; + AR(c, t) = c->ps; + c->ps = (c->ps & ~PS_INTLEVEL) | s; + return; + case 7: /* WAITI */ + c->ps = (c->ps & ~PS_INTLEVEL) | s; + c->waiti = 1; + return; + case 8: case 9: case 10: case 11: { /* ANY4 ALL4 ANY8 ALL8 */ + u32 width = r < 10 ? 4u : 8u, mask = (1u << width) - 1u, bits; + if (s & (width - 1u)) { + esk_lx6_illegal(c); + return; + } + bits = (c->br >> s) & mask; + v = (r & 1u) ? bits == mask : bits != 0; + c->br = (c->br & ~(1u << t)) | v << t; + return; + } + } + esk_lx6_illegal(c); +} + +/* region protection's TLB instructions (RST0's op2 5) */ +static void tlb(struct lx6 *c, u32 w) +{ + u32 r = FR(w), s = FS(w), t = FT(w), a, *tl; + if (win(c, s > t ? s : t)) + return; + a = AR(c, s); + tl = r < 8 ? c->itlb : c->dtlb; + switch (r & 7u) { + case 3: AR(c, t) = a & 0xe0000000u; return; /* R?TLB0 */ + case 4: return; /* I?TLB */ + case 5: AR(c, t) = (a & 0xe0000000u) | 1u; return; /* P?TLB */ + case 6: tl[a >> 29] = AR(c, t) & 15u; return; /* W?TLB */ + case 7: AR(c, t) = (a & 0xe0000000u) | tl[a >> 29]; return; /* R?TLB1 */ + } + esk_lx6_illegal(c); +} + +/* one instruction `w` of `len` bytes at c->pc */ +static void exec(struct lx6 *c, u32 w, u32 len) +{ + u32 op0 = OP0(w), r = FR(w), s = FS(w), t = FT(w), op1 = OP1(w), op2 = OP2(w); + u32 a, v, x, y; + switch (op0) { + case 0: /* QRST */ + switch (op1) { + case 0: /* RST0 */ + switch (op2) { + case 0: st0(c, w); return; + case 1: case 2: case 3: /* AND OR XOR */ + if (win(c, max3(r, s, t))) + return; + x = AR(c, s); + y = AR(c, t); + AR(c, r) = op2 == 1 ? x & y : op2 == 2 ? x | y : x ^ y; + return; + case 4: /* ST1 */ + switch (r) { + case 0: case 1: case 2: case 3: + if (win(c, s)) + return; + x = AR(c, s); + c->sar = r == 0 ? x & 31u : r == 1 ? 32u - (x & 31u) : r == 2 ? (x & 3u) * 8u + : 32u - (x & 3u) * 8u; + return; + case 4: /* SSAI */ + c->sar = s | (t & 1u) << 4; + return; + case 6: /* RER */ + if (win(c, s > t ? s : t)) + return; + AR(c, t) = rer(c, AR(c, s)); + return; + case 7: /* WER */ + if (win(c, s > t ? s : t)) + return; + return; + case 8: /* ROTW */ + c->wb = (c->wb + t) & 15u; + return; + case 14: case 15: /* NSA NSAU */ + if (win(c, s > t ? s : t)) + return; + AR(c, t) = r == 14 ? nsa(AR(c, s)) : nsau(AR(c, s)); + return; + } + break; + case 5: tlb(c, w); return; + case 6: /* NEG ABS */ + if (s > 1) + break; + if (win(c, r > t ? r : t)) + return; + x = AR(c, t); + AR(c, r) = s == 0 ? 0u - x : (x & 0x80000000u) ? 0u - x : x; + return; + case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15: + if (win(c, max3(r, s, t))) + return; + x = AR(c, s) << (op2 & 3u); + y = AR(c, t); + AR(c, r) = op2 < 12 ? x + y : x - y; + return; + } + break; + case 1: /* RST1 */ + switch (op2) { + case 0: case 1: /* SLLI */ + if (win(c, r > s ? r : s)) + return; + AR(c, r) = (u32)((u64)AR(c, s) << (32u - (t | (op2 & 1u) << 4))); + return; + case 2: case 3: /* SRAI */ + if (win(c, r > t ? r : t)) + return; + AR(c, r) = (u32)((s32)AR(c, t) >> (s | (op2 & 1u) << 4)); + return; + case 4: /* SRLI */ + if (win(c, r > t ? r : t)) + return; + AR(c, r) = AR(c, t) >> s; + return; + case 6: /* XSR */ + if (win(c, t)) + return; + if (rsr(c, r << 4 | s, &v)) { + esk_lx6_illegal(c); + return; + } + x = AR(c, t); + if (wsr(c, r << 4 | s, x)) { + esk_lx6_illegal(c); + return; + } + AR(c, t) = v; + return; + case 8: /* SRC */ + if (win(c, max3(r, s, t))) + return; + AR(c, r) = (u32)(((u64)AR(c, s) << 32 | AR(c, t)) >> c->sar); + return; + case 9: /* SRL */ + if (win(c, r > t ? r : t)) + return; + AR(c, r) = (u32)((u64)AR(c, t) >> c->sar); + return; + case 10: /* SLL */ + if (win(c, r > s ? r : s)) + return; + AR(c, r) = (u32)(((u64)AR(c, s) << 32) >> c->sar); + return; + case 11: /* SRA */ + if (win(c, r > t ? r : t)) + return; + AR(c, r) = (u32)((s64)(s32)AR(c, t) >> (c->sar > 63u ? 63u : c->sar)); + return; + case 12: /* MUL16U */ + if (win(c, max3(r, s, t))) + return; + AR(c, r) = (AR(c, s) & 0xffffu) * (AR(c, t) & 0xffffu); + return; + case 13: /* MUL16S */ + if (win(c, max3(r, s, t))) + return; + AR(c, r) = (u32)((s32)sext(AR(c, s), 16) * (s32)sext(AR(c, t), 16)); + return; + } + break; + case 2: /* RST2 */ + if (op2 <= 4) { /* ANDB ANDBC ORB ORBC XORB */ + u32 bs = (c->br >> s) & 1u, bt = (c->br >> t) & 1u, b; + b = op2 == 0 ? bs & bt : op2 == 1 ? bs & !bt : op2 == 2 ? bs | bt : op2 == 3 ? bs | !bt + : bs ^ bt; + c->br = (c->br & ~(1u << r)) | b << r; + return; + } + if (op2 < 8 || op2 == 9) + break; + if (win(c, max3(r, s, t))) + return; + x = AR(c, s); + y = AR(c, t); + switch (op2) { + case 8: AR(c, r) = x * y; c->cost += 1; return; /* MULL */ + case 10: AR(c, r) = (u32)(((u64)x * y) >> 32); c->cost += 1; return; /* MULUH */ + case 11: AR(c, r) = (u32)((u64)((s64)(s32)x * (s32)y) >> 32); c->cost += 1; return; /* MULSH */ + } + if (!y) { + exception(c, EXC_DIVZERO); + return; + } + c->cost += 11; + switch (op2) { + case 12: AR(c, r) = x / y; return; /* QUOU */ + case 13: /* QUOS */ + AR(c, r) = (x == 0x80000000u && y == 0xffffffffu) ? x : (u32)((s32)x / (s32)y); + return; + case 14: AR(c, r) = x % y; return; /* REMU */ + case 15: /* REMS */ + AR(c, r) = (x == 0x80000000u && y == 0xffffffffu) ? 0u : (u32)((s32)x % (s32)y); + return; + } + break; + case 3: /* RST3 */ + switch (op2) { + case 0: /* RSR */ + if (win(c, t)) + return; + if (rsr(c, r << 4 | s, &v)) { + esk_lx6_illegal(c); + return; + } + AR(c, t) = v; + return; + case 1: /* WSR */ + if (win(c, t)) + return; + if (wsr(c, r << 4 | s, AR(c, t))) + esk_lx6_illegal(c); + return; + case 2: /* SEXT */ + if (win(c, r > s ? r : s)) + return; + AR(c, r) = sext(AR(c, s), (int)t + 8); + return; + case 3: { /* CLAMPS */ + s32 lim = (s32)(1u << (t + 7u)), z; + if (win(c, r > s ? r : s)) + return; + z = (s32)AR(c, s); + AR(c, r) = (u32)(z < -lim ? -lim : z > lim - 1 ? lim - 1 : z); + return; + } + case 4: case 5: case 6: case 7: /* MIN MAX MINU MAXU */ + if (win(c, max3(r, s, t))) + return; + x = AR(c, s); + y = AR(c, t); + if (op2 == 4) + AR(c, r) = (s32)x < (s32)y ? x : y; + else if (op2 == 5) + AR(c, r) = (s32)x < (s32)y ? y : x; + else if (op2 == 6) + AR(c, r) = x < y ? x : y; + else + AR(c, r) = x < y ? y : x; + return; + case 8: case 9: case 10: case 11: { /* MOVEQZ MOVNEZ MOVLTZ MOVGEZ */ + int mv; + if (win(c, max3(r, s, t))) + return; + y = AR(c, t); + mv = op2 == 8 ? y == 0 : op2 == 9 ? y != 0 : op2 == 10 ? (s32)y < 0 : (s32)y >= 0; + if (mv) + AR(c, r) = AR(c, s); + return; + } + case 12: case 13: /* MOVF MOVT */ + if (win(c, r > s ? r : s)) + return; + if (((c->br >> t) & 1u) == (op2 == 13)) + AR(c, r) = AR(c, s); + return; + case 14: { /* RUR */ + int k; + if (win(c, r)) + return; + k = rur(c, s << 4 | t, &v); + if (k < 0) + esk_lx6_illegal(c); + else if (k == 0) + AR(c, r) = v; + return; + } + case 15: /* WUR */ + if (win(c, t)) + return; + if (wur(c, r << 4 | s, AR(c, t)) < 0) + esk_lx6_illegal(c); + return; + } + break; + case 4: case 5: /* EXTUI */ + if (win(c, r > t ? r : t)) + return; + x = AR(c, t) >> (s | (op1 & 1u) << 4); + AR(c, r) = x & (u32)((1ull << (op2 + 1u)) - 1u); + return; + case 8: case 10: case 11: /* LSCX, FP0, FP1 */ + if (op1 == 11 && (op2 == 0 || op2 == 14 || op2 == 15)) { + dfp(c, w); /* F64ADDC, F64SUBC, F64CMPL, RF64R */ + return; + } + if (cp0(c)) + return; + if (esk_lx6_fp(c, w) < 0) + esk_lx6_illegal(c); + return; + case 14: case 15: /* the double-precision accelerator's other instructions */ + if ((op1 == 14 && op2 <= 8) || (op1 == 15 && op2 == 0)) { + dfp(c, w); + return; + } + break; + case 9: /* LSC4: L32E S32E */ + if (op2 != 0 && op2 != 4) + break; + if (win(c, s > t ? s : t)) + return; + a = AR(c, s) + ((r << 2) | 0xffffffc0u); + if (op2 == 0) { + if (esk_lx6_load(c, a, 4, &v) == 0) + AR(c, t) = v; + } else { + (void)esk_lx6_store(c, a, 4, AR(c, t)); + } + return; + } + esk_lx6_illegal(c); + return; + case 1: /* L32R */ + if (win(c, t)) + return; + a = ((c->pc + 3u) & ~3u) + ((0xffff0000u | (w >> 8)) << 2); + if (esk_lx6_load(c, a, 4, &v) == 0) + AR(c, t) = v; + return; + case 2: { /* LSAI */ + u32 imm = IMM8(w); + switch (r) { + case 0: case 1: case 2: case 9: case 11: { /* L8UI L16UI L32I L16SI L32AI */ + int n = r == 0 ? 1 : r == 1 || r == 9 ? 2 : 4; + if (win(c, s > t ? s : t)) + return; + a = AR(c, s) + imm * (u32)n; + if (esk_lx6_load(c, a, n, &v)) + return; + AR(c, t) = r == 9 ? sext(v, 16) : v; + return; + } + case 4: case 5: case 6: case 15: { /* S8I S16I S32I S32RI */ + int n = r == 4 ? 1 : r == 5 ? 2 : 4; + if (win(c, s > t ? s : t)) + return; + a = AR(c, s) + imm * (u32)n; + (void)esk_lx6_store(c, a, n, AR(c, t)); + return; + } + case 7: /* CACHE: no caches, nothing to do (DPFR, IPF, ...) */ + if (win(c, s)) + return; + return; + case 10: /* MOVI */ + if (win(c, t)) + return; + AR(c, t) = sext(imm | s << 8, 12); + return; + case 12: /* ADDI */ + if (win(c, s > t ? s : t)) + return; + AR(c, t) = AR(c, s) + sext(imm, 8); + return; + case 13: /* ADDMI */ + if (win(c, s > t ? s : t)) + return; + AR(c, t) = AR(c, s) + (sext(imm, 8) << 8); + return; + case 14: /* S32C1I */ + if (win(c, s > t ? s : t)) + return; + a = AR(c, s) + imm * 4u; + if (esk_lx6_load(c, a, 4, &v)) + return; + if (v == c->scompare1 && esk_lx6_store(c, a, 4, AR(c, t))) + return; + AR(c, t) = v; + return; + } + esk_lx6_illegal(c); + return; + } + case 3: /* LSCI: LSI SSI (LSIU, SSIU are not in this configuration) */ + if (r != 0 && r != 4) { + esk_lx6_illegal(c); + return; + } + if (cp0(c)) + return; + if (win(c, s)) + return; + a = AR(c, s) + IMM8(w) * 4u; + if (r == 0) { + if (esk_lx6_load(c, a, 4, &v) == 0) + c->f[t] = v; + } else { + (void)esk_lx6_store(c, a, 4, c->f[t]); + } + return; + case 4: /* MAC16 */ + mac16(c, w); + return; + case 5: { /* CALLN */ + u32 n = (w >> 4) & 3u; + if (win(c, n * 4u)) + return; + call(c, n, (c->pc & ~3u) + 4u + (sext(w >> 6, 18) << 2), 3); + return; + } + case 6: { /* SI */ + u32 n = (w >> 4) & 3u, m = (w >> 6) & 3u; + if (n == 0) { /* J */ + c->npc = c->pc + 4u + sext(w >> 6, 18); + c->jumped = 1; + c->cost += 2; + return; + } + if (n == 1) { /* BZ */ + if (win(c, s)) + return; + x = AR(c, s); + branch(c, m == 0 ? x == 0 : m == 1 ? x != 0 : m == 2 ? (s32)x < 0 : (s32)x >= 0, + c->pc + 4u + sext(w >> 12, 12)); + return; + } + if (n == 2) { /* BI0 */ + if (win(c, s)) + return; + x = AR(c, s); + y = b4const[r]; + branch(c, m == 0 ? x == y : m == 1 ? x != y : m == 2 ? (s32)x < (s32)y : (s32)x >= (s32)y, + c->pc + 4u + sext(IMM8(w), 8)); + return; + } + /* BI1 */ + if (m == 0) { /* ENTRY */ + entry(c, s, (w >> 12) << 3); + return; + } + if (m == 1) { /* B1 */ + switch (r) { + case 0: case 1: /* BF BT */ + branch(c, ((c->br >> s) & 1u) == r, c->pc + 4u + sext(IMM8(w), 8)); + return; + case 8: case 9: case 10: /* LOOP LOOPNEZ LOOPGTZ */ + if (win(c, s)) + return; + x = AR(c, s); + c->lcount = x - 1u; + c->lbeg = c->pc + 3u; + c->lend = c->pc + 4u + IMM8(w); + if ((r == 9 && x == 0) || (r == 10 && (s32)x <= 0)) { + c->npc = c->lend; + c->jumped = 1; + c->cost += 2; + } + return; + } + esk_lx6_illegal(c); + return; + } + if (win(c, s)) + return; + x = AR(c, s); + y = b4constu[r]; + branch(c, m == 2 ? x < y : x >= y, c->pc + 4u + sext(IMM8(w), 8)); /* BLTUI BGEUI */ + return; + } + case 7: { /* B */ + int taken; + u32 bit; + if (win(c, (r & 7u) == 6u || (r & 7u) == 7u ? s : s > t ? s : t)) + return; + x = AR(c, s); + switch (r) { + case 0: taken = (x & AR(c, t)) == 0; break; /* BNONE */ + case 1: taken = x == AR(c, t); break; /* BEQ */ + case 2: taken = (s32)x < (s32)AR(c, t); break; /* BLT */ + case 3: taken = x < AR(c, t); break; /* BLTU */ + case 4: taken = (~x & AR(c, t)) == 0; break; /* BALL */ + case 5: taken = !((x >> (AR(c, t) & 31u)) & 1u); break; /* BBC */ + case 6: case 7: bit = t | (r & 1u) << 4; taken = !((x >> bit) & 1u); break; /* BBCI */ + case 8: taken = (x & AR(c, t)) != 0; break; /* BANY */ + case 9: taken = x != AR(c, t); break; /* BNE */ + case 10: taken = (s32)x >= (s32)AR(c, t); break; /* BGE */ + case 11: taken = x >= AR(c, t); break; /* BGEU */ + case 12: taken = (~x & AR(c, t)) != 0; break; /* BNALL */ + case 13: taken = (x >> (AR(c, t) & 31u)) & 1u; break; /* BBS */ + default: bit = t | (r & 1u) << 4; taken = (x >> bit) & 1u; break; /* BBSI */ + } + branch(c, taken, c->pc + 4u + sext(IMM8(w), 8)); + return; + } + case 8: /* L32I.N */ + if (win(c, s > t ? s : t)) + return; + if (esk_lx6_load(c, AR(c, s) + r * 4u, 4, &v) == 0) + AR(c, t) = v; + return; + case 9: /* S32I.N */ + if (win(c, s > t ? s : t)) + return; + (void)esk_lx6_store(c, AR(c, s) + r * 4u, 4, AR(c, t)); + return; + case 10: /* ADD.N */ + if (win(c, max3(r, s, t))) + return; + AR(c, r) = AR(c, s) + AR(c, t); + return; + case 11: /* ADDI.N */ + if (win(c, r > s ? r : s)) + return; + AR(c, r) = AR(c, s) + (t ? t : 0xffffffffu); + return; + case 12: /* ST2: MOVI.N BEQZ.N BNEZ.N */ + if (win(c, s)) + return; + if (!(t & 8u)) { + v = r | (t & 7u) << 4; + AR(c, s) = v >= 96u ? v - 128u : v; + } else { + x = AR(c, s); + branch(c, (t & 4u) ? x != 0 : x == 0, c->pc + 4u + (r | (t & 3u) << 4)); + } + return; + case 13: /* ST3 */ + if (r == 0) { /* MOV.N */ + if (win(c, s > t ? s : t)) + return; + AR(c, t) = AR(c, s); + return; + } + if (r == 15) { + switch (t) { + case 0: /* RET.N */ + c->npc = AR(c, 0); + c->jumped = 1; + c->cost += 2; + return; + case 1: retw(c); return; + case 2: debug_exception(c, DBG_BREAKN); return; + case 3: return; /* NOP.N */ + } + } + esk_lx6_illegal(c); + return; + } + ES_UNUSED(len); + esk_lx6_illegal(c); +} + +#ifdef LX6_DEBUG_TRACE +#define RING 65536 +static char ring[RING][96]; +static unsigned ring_n; +static FILE *ring_f; +static void ring_dump(void) +{ + unsigned i, n = ring_n < RING ? ring_n : RING; + for (i = 0; i < n; i++) + fputs(ring[(ring_n - n + i) % RING], ring_f); + fclose(ring_f); +} +static void lx6_debug_trace(struct lx6 *c, u32 w) +{ + static int opened; + if (!opened) { + const char *e = getenv("LX6_TRACE"); + opened = 1; + ring_f = e ? fopen(e, "w") : 0; + if (ring_f) + atexit(ring_dump); + } + { + static u32 stop_pc; + static int got; + if (!got) { + const char *e = getenv("LX6_STOP_PC"); + got = 1; + stop_pc = e ? (u32)strtoul(e, 0, 16) : 0; + } + { + static u32 logs[32]; + static int nlogs = -1; + int q; + if (nlogs < 0) { + const char *e = getenv("LX6_LOG_PCS"); + nlogs = 0; + while (e && *e && nlogs < 32) { + char *end; + logs[nlogs++] = (u32)strtoul(e, &end, 16); + e = *end ? end + 1 : end; + } + } + for (q = 0; q < nlogs; q++) + if (c->pc == logs[q]) { + char str[40]; + int z; + for (z = 0; z < 39; z++) { + u32 ch = 0; + if (esk_bus_debug_read(&c->m->bus, AR(c, 3) + (u32)z, 1, &ch) || ch < 32 || ch > 126) + break; + str[z] = (char)ch; + } + str[z] = 0; + fprintf(stderr, "PCLOG core %d at %08x cycles %llu a0=%08x a2=%08x a3=%08x a4=%08x s3=%s\n", c->id, + (unsigned)c->pc, (unsigned long long)c->m->cycles, (unsigned)AR(c, 0), (unsigned)AR(c, 2), + (unsigned)AR(c, 3), (unsigned)AR(c, 4), str); + } + } + if (stop_pc && c->pc == stop_pc) { + fprintf(stderr, "LX6_STOP_PC hit on core %d\n", c->id); + exit(0); + } + } + if (ring_f) + snprintf(ring[ring_n++ % RING], 96, "%d %08x %06x a0=%08x a1=%08x a2=%08x a3=%08x\n", c->id, + (unsigned)c->pc, (unsigned)w, (unsigned)AR(c, 0), (unsigned)AR(c, 1), (unsigned)AR(c, 2), + (unsigned)AR(c, 3)); +} +#endif + +/* ---- interrupts and a step -------------------------------------------- */ + +/* the level of the interrupt the core would take now, or 0 */ +static u32 irq_level(const struct lx6 *c) +{ + u32 pend = interrupt_reg(c) & c->intenable, th = c->ps & PS_INTLEVEL, l; + if (!pend) + return 0; + if ((c->ps & PS_EXCM) && th < EXCM_LEVEL) + th = EXCM_LEVEL; + if (pend & level_mask[7]) + return 7; + for (l = 5; l > th; l--) + if (pend & level_mask[l]) + return l; + return 0; +} + +static int take_irq(struct lx6 *c) +{ + u32 l = irq_level(c); + if (!l) + return 0; + if (l == 1) + exception(c, EXC_LEVEL1); + else + level_entry(c, l, c->pc); + if (l == 7) + c->latched &= ~INT_NMI; + if (l != 1) + esk_mach_exc(c->m, c->id, 64 + (int)l, c->pc); + c->waiti = 0; + return 1; +} + +static void core_step(struct lx6 *c) +{ + struct esk_mach *m = c->m; + u32 w = 0, len = 3, before = ccount(c); + c->exc = 0; + c->cost = 1; + if (take_irq(c)) + goto done; + if (c->waiti) { + m->asleep = 1; + return; + } + if (c->ibreakenable && (c->ps & PS_INTLEVEL) < DEBUG_LEVEL && + (((c->ibreakenable & 1u) && c->pc == c->ibreaka[0]) || + ((c->ibreakenable & 2u) && c->pc == c->ibreaka[1]))) { + c->debugcause = DBG_IBREAK; + level_entry(c, DEBUG_LEVEL, c->pc); + goto done; + } + if (prohibited(c->itlb[c->pc >> 29])) { + c->excvaddr = c->pc; + exception(c, EXC_IFETCH_PROHIBITED); + goto done; + } + if (fetch(c, c->pc, &w)) { + if (c->pc == c->vecbase + VEC_KERNEL || c->pc == c->vecbase + VEC_DOUBLE) { + esk_mach_end(m, ESK_MACH_LOCKUP, "core %d: the exception vector 0x%08x cannot be fetched", + c->id, (unsigned)c->pc); + return; + } + esk_mach_bus_error(m, c->pc, 3, 0); + c->excvaddr = c->pc; + exception(c, EXC_IFETCH_ADDR); + goto done; + } + if ((w & 15u) >= 8u) { + len = 2; + w &= 0xffffu; + } + c->npc = c->pc + len; + c->jumped = 0; + m->insns++; +#ifdef LX6_DEBUG_TRACE + lx6_debug_trace(c, w); +#endif + if ((w & 15u) >= 14u) + esk_lx6_illegal(c); + else + exec(c, w, len); + if (c->exc == 3) { /* the core was reset by its own store */ + c->exc = 0; + m->cycles += c->cost; + return; + } + if (c->exc == 2) { /* a watchpoint: the debugger stops before it */ + m->insns--; + c->exc = 0; + return; + } + if (!c->exc) { + if (!c->jumped && c->npc == c->pc + len && c->npc == c->lend && c->lcount && !(c->ps & PS_EXCM)) { + c->lcount--; + c->npc = c->lbeg; + } + if (c->icountlevel > (c->ps & PS_INTLEVEL) && ++c->icount == 0) { + c->pc = c->npc; + c->debugcause = DBG_ICOUNT; + level_entry(c, DEBUG_LEVEL, c->pc); + } + } +done: + c->pc = c->npc; + m->cycles += c->cost; + timer_check(c, before, c->cost); +} + +static int core_wake_pending(const struct lx6 *c) +{ + return irq_level(c) != 0; +} + +static void core_reset(struct lx6 *c) +{ + int i; + u32 prid = c->prid, rv = c->reset_vector; + memset(c->ar, 0, sizeof c->ar); + c->pc = c->npc = rv ? 0x40000400u : 0x50000000u; + c->wb = 0; + c->ws = 1; + c->ps = 0x1fu; /* INTLEVEL 15, EXCM */ + c->sar = c->lbeg = c->lend = c->lcount = c->br = c->scompare1 = 0; + c->acclo = c->acchi = 0; + memset(c->mr, 0, sizeof c->mr); + memset(c->epc, 0, sizeof c->epc); + memset(c->eps, 0, sizeof c->eps); + memset(c->excsave, 0, sizeof c->excsave); + c->depc = c->exccause = c->excvaddr = c->debugcause = 0; + c->intenable = c->latched = 0; + c->vecbase = 0x40000000u; + memset(c->ccompare, 0, sizeof c->ccompare); + c->ccount_base = 0; + c->ccount_at = c->m->cycles; + c->cpenable = c->threadptr = c->fcr = c->fsr = 0; + c->expstate = c->f64r_lo = c->f64r_hi = c->f64s = 0; + memset(c->f, 0, sizeof c->f); + memset(c->misc, 0, sizeof c->misc); + c->prid = prid; + c->atomctl = 0x28u; + c->memctl = 1u; + c->ibreakenable = c->icount = c->icountlevel = c->ddr = 0; + memset(c->ibreaka, 0, sizeof c->ibreaka); + memset(c->dbreaka, 0, sizeof c->dbreaka); + memset(c->dbreakc, 0, sizeof c->dbreakc); + for (i = 0; i < 8; i++) + c->itlb[i] = c->dtlb[i] = 2u; + c->waiti = 0; + c->exc = 0; +} + +/* ---- two cores, one interface ----------------------------------------- */ + +static void smp_step(struct esk_cpu *cpu); + +static struct smp *smp_of(struct esk_mach *m) +{ + return m->cpu && m->cpu->ops->step == smp_step ? (struct smp *)m->cpu : 0; +} + +static int next_core(const struct smp *x) +{ + int i, best = -1; + for (i = 0; i < x->n; i++) + if (x->state[i] == CORE_RUN && (best < 0 || x->lt[i] < x->lt[best])) + best = i; + return best < 0 ? 0 : best; +} + +static int current(const struct smp *x) +{ + return x->stepping ? x->cur : next_core(x); +} + +static int any_running(const struct smp *x) +{ + int i; + for (i = 0; i < x->n; i++) + if (x->state[i] == CORE_RUN) + return 1; + return 0; +} + +static void settle(struct smp *x, int i) +{ + int st = x->held[i] ? CORE_HELD : x->stalled[i] ? CORE_STALLED + : x->c[i]->waiti && !core_wake_pending(x->c[i]) ? CORE_SLEEP : CORE_RUN; + if (st == CORE_RUN && x->state[i] != CORE_RUN) { + if (x->lt[i] < x->m->cycles) + x->lt[i] = x->m->cycles; + x->m->asleep = 0; + } + x->state[i] = st; +} + +static void smp_reset(struct esk_cpu *cpu) +{ + struct smp *x = (struct smp *)cpu; + int i; + for (i = 0; i < x->n; i++) { + core_reset(x->c[i]); + x->held[i] = i != 0; /* APP_CPU: DPORT holds it until released */ + x->stalled[i] = 0; + x->lt[i] = x->m->cycles; + x->state[i] = i == 0 ? CORE_RUN : CORE_HELD; + } + x->stepping = 0; + x->cur = 0; +} + +static void smp_step(struct esk_cpu *cpu) +{ + struct smp *x = (struct smp *)cpu; + struct esk_mach *m = x->m; + u64 g0 = m->cycles, g = ~(u64)0; + int i = next_core(x), counting = m->counting, j; + if (x->state[i] != CORE_RUN) { + m->asleep = 1; + return; + } + m->cycles = x->lt[i]; + m->counting = 0; + m->asleep = 0; + x->cur = i; + x->stepping = 1; + esk_mach_step_core(m, i, &x->c[i]->cpu); + x->stepping = 0; + x->lt[i] = m->cycles; + m->counting += counting; + if (x->c[i]->waiti && x->state[i] == CORE_RUN && !core_wake_pending(x->c[i])) + x->state[i] = CORE_SLEEP; + for (j = 0; j < x->n; j++) + if (x->state[j] == CORE_RUN && x->lt[j] < g) + g = x->lt[j]; + if (g == ~(u64)0) + g = x->lt[i] > g0 ? x->lt[i] : g0; + m->cycles = g0; + if (g > g0) { + m->cycles = g; + if (m->counting) + esk_mach_advance(m, (u32)(g - g0)); + } + m->asleep = !any_running(x); +} + +/* the core interface on one core: the analyses step it */ +static void one_step(struct esk_cpu *cpu) +{ + core_step((struct lx6 *)cpu); +} + +/* the CPU timers of the cores that wait: they wake at CCOMPARE */ +static void tm_tick(void *ctx, u32 cycles) +{ + struct smp *x = (struct smp *)ctx; + int i; + for (i = 0; i < x->n; i++) { + struct lx6 *c = x->c[i]; + if (x->state[i] != CORE_SLEEP) + continue; + timer_check(c, ccount(c) - cycles, cycles); + if (core_wake_pending(c)) + settle(x, i); + } +} + +static int tm_next(void *ctx, u32 *cycles) +{ + struct smp *x = (struct smp *)ctx; + int i, k, any = 0; + for (i = 0; i < x->n; i++) { + struct lx6 *c = x->c[i]; + if (x->state[i] != CORE_SLEEP) + continue; + for (k = 0; k < 3; k++) { + u32 d = c->ccompare[k] - ccount(c); + if (!(c->intenable & (1u << timer_int[k])) || (c->latched & (1u << timer_int[k]))) + continue; + if (!d) + d = 0xffffffffu; + if (!any || d < *cycles) + *cycles = d; + any = 1; + } + } + return any; +} + +static void tm_reset(void *ctx) +{ + ES_UNUSED(ctx); +} + +static const struct esk_dev_ops timer_ops = { + "lx6-timers", 0, 0, tm_reset, tm_tick, tm_next, +}; + +/* ---- registers, as GDB numbers them ----------------------------------- + * + * Espressif's xtensa-esp32-elf-gdb: pc 0, the 64 physical ARs 1-64, lbeg, + * lend, lcount, sar, windowbase, windowstart, configid0, configid1, ps, + * threadptr, br, scompare1, acclo, acchi, m0-m3, expstate, f64r_lo, + * f64r_hi, f64s, f0-f15, fcr, fsr (65-104). The window's a0-a15 follow + * here at 105-120 for a register view. */ + +enum { GR_PC = 0, GR_AR = 1, GR_LBEG = 65, GR_F = 87, GR_FCR = 103, GR_FSR = 104, GR_A = 105, GR_N = 121 }; + +static int put(u8 *b, u32 v) +{ + b[0] = (u8)v; + b[1] = (u8)(v >> 8); + b[2] = (u8)(v >> 16); + b[3] = (u8)(v >> 24); + return 4; +} + +static u32 get(const u8 *b) +{ + return (u32)b[0] | (u32)b[1] << 8 | (u32)b[2] << 16 | (u32)b[3] << 24; +} + +static u32 *reg_ptr(struct lx6 *c, int n) +{ + static u32 zero; + if (n == GR_PC) + return &c->pc; + if (n >= GR_AR && n < GR_AR + 64) + return &c->ar[n - GR_AR]; + if (n >= GR_A && n < GR_A + 16) + return &AR(c, n - GR_A); + if (n >= GR_F && n < GR_F + 16) + return &c->f[n - GR_F]; + switch (n) { + case 65: return &c->lbeg; + case 66: return &c->lend; + case 67: return &c->lcount; + case 68: return &c->sar; + case 69: return &c->wb; + case 70: return &c->ws; + case 73: return &c->ps; + case 74: return &c->threadptr; + case 75: return &c->br; + case 76: return &c->scompare1; + case 77: return &c->acclo; + case 78: return &c->acchi; + case 79: case 80: case 81: case 82: return &c->mr[n - 79]; + case GR_FCR: return &c->fcr; + case GR_FSR: return &c->fsr; + } + zero = 0; + return n == 71 || n == 72 || (n >= 83 && n <= 86) ? &zero : 0; +} + +static int core_reg_read(struct lx6 *c, int n, u8 *buf) +{ + u32 *p; + if (n == 71) + return put(buf, CONFIGID0); + if (n == 72) + return put(buf, CONFIGID1); + p = reg_ptr(c, n); + return p ? put(buf, *p) : 0; +} + +static int core_reg_write(struct lx6 *c, int n, const u8 *buf) +{ + u32 *p = n == 71 || n == 72 ? 0 : reg_ptr(c, n); + if (!p) + return 0; + *p = get(buf); + c->wb &= 15u; + c->ws &= 0xffffu; + c->ps &= PS_MASK; + if (n == GR_PC) + c->npc = c->pc; + return 4; +} + +static const char *core_reg_name(int n) +{ + static const char *const a[16] = { "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", + "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15" }; + static const char *const sr[] = { "lbeg", "lend", "lcount", "sar", "windowbase", "windowstart", + "configid0", "configid1", "ps", "threadptr", "br", "scompare1", + "acclo", "acchi", "m0", "m1", "m2", "m3", "expstate", + "f64r_lo", "f64r_hi", "f64s" }; + static const char *const f[16] = { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15" }; + static const char *const ar[64] = { + "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", "ar8", "ar9", "ar10", "ar11", + "ar12", "ar13", "ar14", "ar15", "ar16", "ar17", "ar18", "ar19", "ar20", "ar21", "ar22", + "ar23", "ar24", "ar25", "ar26", "ar27", "ar28", "ar29", "ar30", "ar31", "ar32", "ar33", + "ar34", "ar35", "ar36", "ar37", "ar38", "ar39", "ar40", "ar41", "ar42", "ar43", "ar44", + "ar45", "ar46", "ar47", "ar48", "ar49", "ar50", "ar51", "ar52", "ar53", "ar54", "ar55", + "ar56", "ar57", "ar58", "ar59", "ar60", "ar61", "ar62", "ar63" }; + if (n == GR_PC) + return "pc"; + if (n >= GR_AR && n < GR_AR + 64) + return ar[n - GR_AR]; + if (n >= GR_LBEG && n < GR_F) + return sr[n - GR_LBEG]; + if (n >= GR_F && n < GR_F + 16) + return f[n - GR_F]; + if (n == GR_FCR) + return "fcr"; + if (n == GR_FSR) + return "fsr"; + if (n >= GR_A && n < GR_A + 16) + return a[n - GR_A]; + return 0; +} + +static const int g_regs[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, + 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, + 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, + 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, + 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, -1 }; + +/* the disassembly: the instruction's bytes and size (the debugger and + * the trace show the mnemonic from the ELF's own tools) */ +static int core_disasm(struct lx6 *c, u32 addr, char *text, size_t cap) +{ + u32 lo, hi = 0, w; + int len; + if (esk_bus_debug_read(&c->m->bus, addr, 2, &lo) != 0) + return 0; + len = (lo & 15u) >= 8u ? 2 : 3; + if (len == 3 && esk_bus_debug_read(&c->m->bus, addr + 2u, 1, &hi) != 0) + return 0; + w = (lo & 0xffffu) | (hi & 0xffu) << 16; + snprintf(text, cap, len == 3 ? ".byte 0x%02x, 0x%02x, 0x%02x" : ".byte 0x%02x, 0x%02x", + (unsigned)(w & 0xffu), (unsigned)((w >> 8) & 0xffu), (unsigned)((w >> 16) & 0xffu)); + return len; +} + +/* the interface's hooks: the core that runs next */ +static struct lx6 *cur(struct esk_cpu *cpu) +{ + struct smp *x = (struct smp *)cpu; + return x->c[current(x)]; +} + +static u32 smp_pc(struct esk_cpu *cpu) { return cur(cpu)->pc; } +static int smp_reg_read(struct esk_cpu *cpu, int n, u8 *buf) { return core_reg_read(cur(cpu), n, buf); } +static int smp_reg_write(struct esk_cpu *cpu, int n, const u8 *buf) { return core_reg_write(cur(cpu), n, buf); } +static const int *smp_g_regs(struct esk_cpu *cpu) { ES_UNUSED(cpu); return g_regs; } +static const char *smp_xml(struct esk_cpu *cpu, const char *annex) +{ + ES_UNUSED(cpu); + ES_UNUSED(annex); + return 0; +} +static void smp_interrupt(struct esk_cpu *cpu, int n) +{ + struct smp *x = (struct smp *)cpu; + struct lx6 *c = x->c[current(x)]; + if (n >= 16) + n -= 16; + if (n >= 0 && n < 32 && ((1u << n) & INT_SOFTWARE)) { + c->latched |= 1u << n; + settle(x, current(x)); + } +} +static const char *smp_reg_name(struct esk_cpu *cpu, int n) { ES_UNUSED(cpu); return core_reg_name(n); } +static int smp_wake_pending(struct esk_cpu *cpu) +{ + struct smp *x = (struct smp *)cpu; + int i; + for (i = 0; i < x->n; i++) + if (!x->held[i] && !x->stalled[i] && core_wake_pending(x->c[i])) + return 1; + return 0; +} +static int smp_disasm(struct esk_cpu *cpu, u32 addr, char *text, size_t cap) +{ + return core_disasm(cur(cpu), addr, text, cap); +} + +static const struct esk_cpu_ops smp_ops = { + "xtensa", 94, "an Xtensa image", + smp_reset, smp_step, smp_pc, smp_reg_read, smp_reg_write, + smp_g_regs, smp_xml, 3, smp_interrupt, GR_PC, 1, 0, smp_reg_name, smp_wake_pending, + smp_disasm, 0, 0, +}; + +/* each core's own interface, for the analyses' step (esk_mach_step_core) */ +static u32 one_pc(struct esk_cpu *cpu) { return ((struct lx6 *)cpu)->pc; } +static int one_reg_read(struct esk_cpu *cpu, int n, u8 *buf) { return core_reg_read((struct lx6 *)cpu, n, buf); } +static int one_reg_write(struct esk_cpu *cpu, int n, const u8 *buf) { return core_reg_write((struct lx6 *)cpu, n, buf); } +static void one_reset(struct esk_cpu *cpu) { core_reset((struct lx6 *)cpu); } +static int one_wake_pending(struct esk_cpu *cpu) { return core_wake_pending((struct lx6 *)cpu); } +static int one_disasm(struct esk_cpu *cpu, u32 addr, char *text, size_t cap) +{ + return core_disasm((struct lx6 *)cpu, addr, text, cap); +} + +static const struct esk_cpu_ops one_ops = { + "xtensa", 94, "an Xtensa image", + one_reset, one_step, one_pc, one_reg_read, one_reg_write, + smp_g_regs, smp_xml, 3, 0, GR_PC, 1, 0, smp_reg_name, one_wake_pending, + one_disasm, 0, 0, +}; + +int esk_lx6_is(const struct esk_cpu *c) +{ + return c && c->ops == &smp_ops; +} + +es_status esk_lx6_create(struct esk_mach *m, const char *model, int cores, struct esk_cpu **out) +{ + struct smp *x; + int i; + es_status st; + if (strcmp(model, "esp32-lx6") || cores < 1 || cores > NCORES) + return ES_ENOTFOUND; + x = (struct smp *)esk_mach_alloc(m, sizeof *x); + if (!x) + return ES_ENOMEM; + x->cpu.ops = &smp_ops; + x->m = m; + x->n = cores; + for (i = 0; i < cores; i++) { + struct lx6 *c = (struct lx6 *)esk_mach_alloc(m, sizeof *c); + if (!c) + return ES_ENOMEM; + c->cpu.ops = &one_ops; + c->m = m; + c->x = x; + c->id = i; + c->prid = i == 0 ? 0xCDCDu : 0xABABu; + c->reset_vector = 1; + x->c[i] = c; + } + st = esk_mach_add_dev(m, 0, 0, &timer_ops, x); + if (st != ES_OK) + return st; + esk_mach_clock(m, &x->running, 1); /* the CPU timers' clock never stops */ + m->steps_cores = 1; + m->cpu = &x->cpu; + smp_reset(&x->cpu); + *out = &x->cpu; + return ES_OK; +} + +/* ---- the part's controls ---------------------------------------------- */ + +int esk_lx6_cores(struct esk_mach *m) +{ + struct smp *x = smp_of(m); + return x ? x->n : 0; +} + +int esk_lx6_core(struct esk_mach *m) +{ + struct smp *x = smp_of(m); + return x ? current(x) : 0; +} + +void esk_lx6_irq(struct esk_mach *m, int core, int line, int level) +{ + struct smp *x = smp_of(m); + struct lx6 *c; + u32 bit; + if (!x || core < 0 || core >= x->n || line < 0 || line > 31) + return; + c = x->c[core]; + bit = 1u << line; + if (level) { + if (!(c->lines & bit) && (bit & (INT_EDGE | INT_NMI))) + c->latched |= bit; + c->lines |= bit; + } else { + c->lines &= ~bit; + } + if (x->state[core] == CORE_SLEEP && core_wake_pending(c)) + settle(x, core); +} + +void esk_lx6_core_reset(struct esk_mach *m, int core, int held) +{ + struct smp *x = smp_of(m); + if (!x || core < 0 || core >= x->n || x->held[core] == (held != 0)) + return; + x->held[core] = held != 0; + if (!held) { + core_reset(x->c[core]); + x->lt[core] = m->cycles; + } + settle(x, core); +} + +void esk_lx6_core_stall(struct esk_mach *m, int core, int why, int stalled) +{ + struct smp *x = smp_of(m); + if (!x || core < 0 || core >= x->n || why < 0 || why > 7) + return; + if (stalled) + x->stalled[core] |= 1 << why; + else + x->stalled[core] &= ~(1 << why); + settle(x, core); +} + +void esk_lx6_core_restart(struct esk_mach *m, int core) +{ + struct smp *x = smp_of(m); + if (!x || core < 0 || core >= x->n) + return; + core_reset(x->c[core]); + x->lt[core] = m->cycles; + if (x->stepping && x->cur == core) + x->c[core]->exc = 3; /* the instruction in progress is gone with it */ + settle(x, core); +} + +int esk_lx6_view(struct esk_mach *m, int core, u32 base, u32 size, const u8 *mem) +{ + struct smp *x = smp_of(m); + struct lx6 *c; + if (!x || core < 0 || core >= x->n) + return -1; + c = x->c[core]; + if (c->nview >= 2) + return -1; + c->view[c->nview].base = base; + c->view[c->nview].size = size; + c->view[c->nview].mem = mem; + c->nview++; + return 0; +} + +void esk_lx6_reset_vector(struct esk_mach *m, int core, int sel) +{ + struct smp *x = smp_of(m); + if (x && core >= 0 && core < x->n) + x->c[core]->reset_vector = sel != 0; +} + +u32 esk_lx6_pc(struct esk_mach *m, int core) +{ + struct smp *x = smp_of(m); + return x && core >= 0 && core < x->n ? x->c[core]->pc : 0; +} + +u32 esk_lx6_sp(struct esk_mach *m, int core) +{ + struct smp *x = smp_of(m); + return x && core >= 0 && core < x->n ? AR(x->c[core], 1) : 0; +} + +/* ---- for lx6fp.c ------------------------------------------------------ */ + +u32 *esk_lx6_fregs(struct lx6 *c) { return c->f; } +u32 *esk_lx6_fcr(struct lx6 *c) { return &c->fcr; } +u32 *esk_lx6_fsr(struct lx6 *c) { return &c->fsr; } +u32 esk_lx6_fp_rd(struct lx6 *c, int n) { return c->f[n & 15]; } +void esk_lx6_fp_wr(struct lx6 *c, int n, u32 v) { c->f[n & 15] = v; } +u32 esk_lx6_ar(struct lx6 *c, int n) { return AR(c, (u32)n); } +void esk_lx6_set_ar(struct lx6 *c, int n, u32 v) { AR(c, (u32)n) = v; } +u32 esk_lx6_br(struct lx6 *c) { return c->br; } +void esk_lx6_set_br(struct lx6 *c, u32 v) { c->br = v & 0xffffu; } +int esk_lx6_win(struct lx6 *c, u32 hi) { return win(c, hi); } diff --git a/core/mcu/xtensa/lx6.h b/core/mcu/xtensa/lx6.h new file mode 100644 index 000000000..623d1ec89 --- /dev/null +++ b/core/mcu/xtensa/lx6.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* lx6.h -- the Xtensa LX6 cores of the ESP32 (lx6.c, lx6fp.c), behind + * the machine's one core interface: the configuration Espressif's + * core-isa.h gives (esp32_v3_49_prod, LX6.0.3), two of them as the chip's + * PRO_CPU and APP_CPU. */ +#ifndef ESK_MCU_XTENSA_LX6_H +#define ESK_MCU_XTENSA_LX6_H + +#include "mcu/mach.h" + +/* the cores of model "esp32-lx6" (`cores` 1 or 2): core 0 runs from + * reset, core 1 is held in reset until the part releases it */ +es_status esk_lx6_create(struct esk_mach *m, const char *model, int cores, struct esk_cpu **out); +int esk_lx6_is(const struct esk_cpu *c); +/* the number of cores, and the one whose instruction is in progress (a + * debugger's: the one that runs next) */ +int esk_lx6_cores(struct esk_mach *m); +int esk_lx6_core(struct esk_mach *m); +/* interrupt input `line` (0-31) of core `core` is at `level`: a level + * input is pending while it is high, an edge input latches a rise + * (core-isa.h's XCHAL_INTTYPE_MASK_EXTERN_EDGE) */ +void esk_lx6_irq(struct esk_mach *m, int core, int line, int level); +/* the core is held in reset (1) or released (0): released, it starts + * at its reset vector */ +void esk_lx6_core_reset(struct esk_mach *m, int core, int held); +/* the core's clock is gated or stalled (1: it stops where it is) for + * reason `why` (0-7: the part's sources, any of which stops it), or runs */ +void esk_lx6_core_stall(struct esk_mach *m, int core, int why, int stalled); +/* the core alone is reset (a software or watchdog CPU reset): it starts + * again at its reset vector, the devices as they are */ +void esk_lx6_core_restart(struct esk_mach *m, int core); +/* the core sees `size` bytes of read-only memory at `base` from `mem` + * rather than the bus (its own ROM): 0, or -1 (two views at most) */ +int esk_lx6_view(struct esk_mach *m, int core, u32 base, u32 size, const u8 *mem); +/* the core's reset vector: 0x40000400 (1) or 0x50000000 (0) */ +void esk_lx6_reset_vector(struct esk_mach *m, int core, int sel); +/* the core's program counter, and its stack pointer (a1) */ +u32 esk_lx6_pc(struct esk_mach *m, int core); +u32 esk_lx6_sp(struct esk_mach *m, int core); + +/* ---- inside: the core's state, for lx6fp.c ------------------------------ */ + +struct lx6; +/* FP instruction `w` (op0 0 with op1 8, 10 or 11; op0 3): 0 when done, + * or -1 when not an FP instruction */ +int esk_lx6_fp(struct lx6 *c, u32 w); +u32 esk_lx6_fp_rd(struct lx6 *c, int n); +void esk_lx6_fp_wr(struct lx6 *c, int n, u32 v); +u32 *esk_lx6_fregs(struct lx6 *c); +u32 *esk_lx6_fcr(struct lx6 *c); +u32 *esk_lx6_fsr(struct lx6 *c); +u32 esk_lx6_ar(struct lx6 *c, int n); +void esk_lx6_set_ar(struct lx6 *c, int n, u32 v); +u32 esk_lx6_br(struct lx6 *c); +void esk_lx6_set_br(struct lx6 *c, u32 v); +/* a load or store of the core's: 0, or -1 when it took an exception */ +int esk_lx6_load(struct lx6 *c, u32 a, int n, u32 *v); +/* the window overflow check of registers up to `hi`: 1 when it was taken */ +int esk_lx6_win(struct lx6 *c, u32 hi); +int esk_lx6_store(struct lx6 *c, u32 a, int n, u32 v); +void esk_lx6_illegal(struct lx6 *c); +#endif diff --git a/core/mcu/xtensa/lx6fp.c b/core/mcu/xtensa/lx6fp.c new file mode 100644 index 000000000..411a11b62 --- /dev/null +++ b/core/mcu/xtensa/lx6fp.c @@ -0,0 +1,418 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* lx6fp.c -- the ESP32's floating-point coprocessor (CP0): the Xtensa + * Floating-Point Coprocessor Option, single precision, with the + * division, reciprocal and square root instructions of core-isa.h + * (XCHAL_HAVE_FP_DIV, _RECIP, _SQRT, _RSQRT). + * + * Sixteen 32-bit registers f0-f15; FCR's rounding mode (bits 1:0: + * nearest even, toward zero, up, down) and FSR's sticky flags (bits 11:7: + * inexact, underflow, overflow, divide by zero, invalid). Arithmetic is + * IEEE 754: ADD.S, SUB.S, MUL.S, MADD.S and MSUB.S (fused, one rounding) + * are rounded as FCR says, with their flags; FLOAT.S and UFLOAT.S scale + * by 2^-imm, ROUND.S, TRUNC.S, FLOOR.S, CEIL.S and UTRUNC.S by 2^imm, out + * of range or NaN giving the limits (0x7fffffff, 0x80000000, or for + * UTRUNC.S 0xffffffff); the comparisons set a boolean register; the + * moves (MOV.S, ABS.S, NEG.S, the conditional ones, RFR, WFR, CONST.S's + * 0, 1, 2 and 0.5) change no flag. A NaN result is the first NaN operand + * made quiet, or 0x7fc00000. + * + * Where it differs inside: the division and square root sequences + * libgcc runs (DIV0.S, NEXP01.S, MADDN.S, MKDADJ.S, ADDEXP.S, ADDEXPM.S, + * DIVN.S; SQRT0.S, MKSADJ.S, ...) give the quotient or root correctly + * rounded, as the hardware's do, but the registers in between hold other + * values: MKDADJ.S fr, fs computes fs / fr, MKSADJ.S the root, ADDEXPM.S + * moves it to its destination, the others change nothing (Espressif's + * QEMU does the same). RECIP0.S and RSQRT0.S give the exact reciprocal + * and reciprocal root rounded, where the hardware gives a seed of fewer + * bits. The arithmetic is the host's double precision with fma(), which + * holds every single-precision result exactly or with its residual. */ +#include +#include +#include + +#include "mcu/xtensa/lx6.h" + +#define F_I 0x1u /* the flags, as FSR holds them from bit 7 */ +#define F_U 0x2u +#define F_O 0x4u +#define F_Z 0x8u +#define F_V 0x10u +#define QNAN 0x7fc00000u + +static float f_of(u32 v) +{ + float f; + memcpy(&f, &v, 4); + return f; +} + +static u32 bits_of(float f) +{ + u32 v; + memcpy(&v, &f, 4); + return v; +} + +static int is_nan(u32 v) +{ + return (v & 0x7f800000u) == 0x7f800000u && (v & 0x7fffffu); +} + +static int is_snan(u32 v) +{ + return is_nan(v) && !(v & 0x400000u); +} + +static void flag(struct lx6 *c, u32 f) +{ + *esk_lx6_fsr(c) |= f << 7; +} + +static u32 rmode(struct lx6 *c) +{ + return *esk_lx6_fcr(c) & 3u; +} + +/* a NaN result of operands a and b (and c): the first NaN quieted */ +static u32 nan_of(struct lx6 *c, u32 a, u32 b, u32 x, int n) +{ + if (is_snan(a) || is_snan(b) || (n > 2 && is_snan(x))) + flag(c, F_V); + if (is_nan(a)) + return a | 0x400000u; + if (is_nan(b)) + return b | 0x400000u; + if (n > 2 && is_nan(x)) + return x | 0x400000u; + return QNAN; +} + +/* the value hi + lo (lo below hi's last bit, only its sign and whether + * it is 0 matter) rounded to single precision in mode `m` */ +static u32 round_f(struct lx6 *c, double hi, double lo, u32 m) +{ + float f; + double diff, res; + int inexact; + if (hi != hi) + return QNAN; + if (isinf(hi)) + return bits_of((float)hi); + f = (float)hi; + if (isinf(f)) { /* overflow */ + flag(c, F_O | F_I); + if ((m == 1) || (m == 2 && hi < 0) || (m == 3 && hi > 0)) + return bits_of(hi < 0 ? -FLT_MAX : FLT_MAX); + return bits_of(f); + } + diff = hi - (double)f; + res = diff != 0 ? diff : lo; + inexact = diff != 0 || lo != 0; + if (m == 0) { + /* a tie broken the wrong way by the host, lo deciding */ + if (diff != 0 && lo != 0 && (lo > 0) == (diff > 0)) { + float g = nextafterf(f, diff > 0 ? INFINITY : -INFINITY); + if (fabs((double)g - (double)f) == 2 * fabs(diff)) + f = g; + } + } else if (res != 0) { + if (m == 1) { /* toward zero */ + if ((f > 0 && res < 0) || (f < 0 && res > 0)) + f = nextafterf(f, 0.0f); + } else if (m == 2) { /* up */ + if (res > 0) + f = nextafterf(f, INFINITY); + } else if (res < 0) { /* down */ + f = nextafterf(f, -INFINITY); + } + if (f == 0 && hi != 0) + f = hi < 0 ? -0.0f : 0.0f; + } + if (isinf(f)) { + flag(c, F_O | F_I); + return bits_of(f); + } + if (inexact) { + flag(c, F_I); + if (fabs((double)f) < FLT_MIN || (f == 0 && hi != 0)) + flag(c, F_U); + } + return bits_of(f); +} + +static int is_inf(u32 v) +{ + return (v & 0x7fffffffu) == 0x7f800000u; +} + +static int is_zero(u32 v) +{ + return !(v & 0x7fffffffu); +} + +/* a + b * x fused (sub: a - b * x), or b + x (mul 0) / b * x (add 0) */ +static u32 add_s(struct lx6 *c, u32 a, u32 b) +{ + double x = f_of(a), y = f_of(b), s, bb, lo; + if (is_nan(a) || is_nan(b)) + return nan_of(c, a, b, 0, 2); + if (is_inf(a) && is_inf(b) && ((a ^ b) & 0x80000000u)) { + flag(c, F_V); + return QNAN; + } + s = x + y; + if (is_inf(a) || is_inf(b)) + return bits_of((float)s); + if (s == 0 && x == -y && x != 0) + return rmode(c) == 3 ? 0x80000000u : 0; /* an exact zero sum: +0 but rounding down */ + if (s == 0) + return (a & b & 0x80000000u) | (rmode(c) == 3 ? (a | b) & 0x80000000u : 0u); + bb = s - x; + lo = (x - (s - bb)) + (y - bb); /* TwoSum: s + lo is x + y exactly */ + return round_f(c, s, lo, rmode(c)); +} + +static u32 mul_s(struct lx6 *c, u32 a, u32 b) +{ + if (is_nan(a) || is_nan(b)) + return nan_of(c, a, b, 0, 2); + if ((is_inf(a) && is_zero(b)) || (is_zero(a) && is_inf(b))) { + flag(c, F_V); + return QNAN; + } + return round_f(c, (double)f_of(a) * (double)f_of(b), 0, rmode(c)); /* exact in double */ +} + +static u32 madd_s(struct lx6 *c, u32 acc, u32 a, u32 b, int sub) +{ + double p, x, s, bb, lo; + u32 pb; + if (is_nan(acc) || is_nan(a) || is_nan(b)) { + if ((is_inf(a) && is_zero(b)) || (is_zero(a) && is_inf(b))) + flag(c, F_V); + return nan_of(c, a, b, acc, 3); + } + if ((is_inf(a) && is_zero(b)) || (is_zero(a) && is_inf(b))) { + flag(c, F_V); + return QNAN; + } + p = (double)f_of(a) * (double)f_of(b); + if (sub) + p = -p; + x = f_of(acc); + pb = (u32)(p < 0 || (p == 0 && signbit(p))) << 31; + if ((is_inf(a) || is_inf(b)) && is_inf(acc) && ((pb ^ acc) & 0x80000000u)) { + flag(c, F_V); + return QNAN; + } + s = x + p; + if (isinf(s) || is_inf(acc)) + return bits_of((float)s); + if (s == 0) { + if (x == 0 && p == 0) + return (acc & pb) | (rmode(c) == 3 ? (acc | pb) & 0x80000000u : 0u); + return rmode(c) == 3 ? 0x80000000u : 0; + } + bb = s - x; + lo = (x - (s - bb)) + (p - bb); + return round_f(c, s, lo, rmode(c)); +} + +static u32 div_s(struct lx6 *c, u32 a, u32 b) +{ + double q, r; + if (is_nan(a) || is_nan(b)) + return nan_of(c, a, b, 0, 2); + if ((is_zero(a) && is_zero(b)) || (is_inf(a) && is_inf(b))) { + flag(c, F_V); + return QNAN; + } + if (is_zero(b)) { + if (!is_inf(a)) + flag(c, F_Z); + return ((a ^ b) & 0x80000000u) | 0x7f800000u; + } + if (is_inf(a) || is_zero(a) || is_inf(b)) + return bits_of(f_of(a) / f_of(b)); + q = (double)f_of(a) / (double)f_of(b); + r = fma(-q, (double)f_of(b), (double)f_of(a)); /* the exact remainder */ + return round_f(c, q, (f_of(b) < 0 ? -r : r), rmode(c)); +} + +static u32 sqrt_s(struct lx6 *c, u32 a) +{ + double x = f_of(a), r, e; + if (is_nan(a)) + return nan_of(c, a, 0, 0, 1); + if (is_zero(a)) + return a; + if (a & 0x80000000u) { + flag(c, F_V); + return QNAN; + } + if (is_inf(a)) + return a; + r = sqrt(x); + e = fma(-r, r, x); + return round_f(c, r, e, rmode(c)); +} + +/* to an integer: v * 2^scale rounded in mode m, signed or not */ +static u32 to_int(struct lx6 *c, u32 v, u32 scale, u32 m, int uns) +{ + double x = ldexp((double)f_of(v), (int)scale), y; + if (is_nan(v)) { + flag(c, F_V); + return uns ? 0xffffffffu : 0x7fffffffu; + } + y = m == 0 ? nearbyint(x) : m == 1 ? trunc(x) : m == 2 ? ceil(x) : floor(x); + if (m == 0 && fabs(x - trunc(x)) == 0.5) + y = 2.0 * nearbyint(x / 2.0); /* ties to even, whatever the host's mode */ + if (uns && !(v & 0x80000000u)) { + if (y > 4294967295.0) { + flag(c, F_V); + return 0xffffffffu; + } + if (y != x) + flag(c, F_I); + return (u32)y; + } + if (y > 2147483647.0) { + flag(c, F_V); + return 0x7fffffffu; + } + if (y < -2147483648.0) { + flag(c, F_V); + return 0x80000000u; + } + if (uns && y != 0) + flag(c, F_V); /* UTRUNC.S of a negative value */ + else if (y != x) + flag(c, F_I); + return (u32)(s32)y; +} + +static u32 from_int(struct lx6 *c, u32 v, u32 scale, int uns) +{ + double x = uns ? (double)v : (double)(s32)v; + return round_f(c, ldexp(x, -(int)scale), 0, rmode(c)); /* exact in double */ +} + +/* the comparisons: 1 UN, 2 OEQ, 3 UEQ, 4 OLT, 5 ULT, 6 OLE, 7 ULE */ +static int compare(struct lx6 *c, u32 op, u32 a, u32 b) +{ + int un = is_nan(a) || is_nan(b); + float x = f_of(a), y = f_of(b); + if (is_snan(a) || is_snan(b) || (un && op >= 4 && (op & 1u) == 0)) + flag(c, F_V); + switch (op) { + case 1: return un; + case 2: return !un && x == y; + case 3: return un || x == y; + case 4: return !un && x < y; + case 5: return un || x < y; + case 6: return !un && x <= y; + case 7: return un || x <= y; + } + return 0; +} + +int esk_lx6_fp(struct lx6 *c, u32 w) +{ + u32 op1 = (w >> 16) & 15u, op2 = (w >> 20) & 15u, r = (w >> 12) & 15u, s = (w >> 8) & 15u, + t = (w >> 4) & 15u, *f = esk_lx6_fregs(c), a, v; + if (op1 == 8) { /* LSX, SSX (LSXU, SSXU: not in this configuration) */ + if (op2 != 0 && op2 != 4) + return -1; + if (esk_lx6_win(c, s > t ? s : t)) + return 0; + a = esk_lx6_ar(c, (int)s) + esk_lx6_ar(c, (int)t); + if (op2 == 0) { + if (esk_lx6_load(c, a, 4, &v) == 0) + f[r] = v; + } else { + (void)esk_lx6_store(c, a, 4, f[r]); + } + return 0; + } + if (op1 == 10) { /* FP0 */ + switch (op2) { + case 0: f[r] = add_s(c, f[s], f[t]); return 0; + case 1: f[r] = add_s(c, f[s], f[t] ^ (is_nan(f[t]) ? 0u : 0x80000000u)); return 0; + case 2: f[r] = mul_s(c, f[s], f[t]); return 0; + case 4: f[r] = madd_s(c, f[r], f[s], f[t], 0); return 0; + case 5: f[r] = madd_s(c, f[r], f[s], f[t], 1); return 0; + case 6: case 7: return 0; /* MADDN.S DIVN.S: in MKDADJ.S's result */ + case 8: case 9: case 10: case 11: case 14: { /* ROUND TRUNC FLOOR CEIL UTRUNC */ + static const u32 mode[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 3, 2, 0, 0, 1, 0 }; + if (esk_lx6_win(c, r)) + return 0; + esk_lx6_set_ar(c, (int)r, to_int(c, f[s], t, mode[op2], op2 == 14)); + return 0; + } + case 12: case 13: /* FLOAT.S UFLOAT.S */ + if (esk_lx6_win(c, s)) + return 0; + f[r] = from_int(c, esk_lx6_ar(c, (int)s), t, op2 == 13); + return 0; + case 15: /* FP1OP */ + switch (t) { + case 0: f[r] = f[s]; return 0; /* MOV.S */ + case 1: f[r] = f[s] & 0x7fffffffu; return 0; /* ABS.S */ + case 3: { /* CONST.S */ + static const u32 k[4] = { 0x00000000u, 0x3f800000u, 0x40000000u, 0x3f000000u }; + f[r] = k[s & 3u]; + return 0; + } + case 4: /* RFR */ + if (esk_lx6_win(c, r)) + return 0; + esk_lx6_set_ar(c, (int)r, f[s]); + return 0; + case 5: /* WFR */ + if (esk_lx6_win(c, s)) + return 0; + f[r] = esk_lx6_ar(c, (int)s); + return 0; + case 6: f[r] = f[s] ^ 0x80000000u; return 0; /* NEG.S */ + case 7: case 9: case 11: return 0; /* DIV0.S SQRT0.S NEXP01.S */ + case 8: f[r] = div_s(c, 0x3f800000u, f[s]); return 0; /* RECIP0.S */ + case 10: /* RSQRT0.S */ + f[r] = div_s(c, 0x3f800000u, sqrt_s(c, f[s])); + return 0; + case 12: f[r] = sqrt_s(c, f[s]); return 0; /* MKSADJ.S */ + case 13: f[r] = div_s(c, f[s], f[r]); return 0; /* MKDADJ.S */ + case 14: return 0; /* ADDEXP.S */ + case 15: f[r] = f[s]; return 0; /* ADDEXPM.S */ + } + return -1; + } + return -1; + } + if (op1 == 11) { /* FP1 */ + if (op2 >= 1 && op2 <= 7) { + u32 br = esk_lx6_br(c); + int b = compare(c, op2, f[s], f[t]); + esk_lx6_set_br(c, (br & ~(1u << r)) | (u32)b << r); + return 0; + } + if (op2 >= 8 && op2 <= 11) { /* MOVEQZ.S MOVNEZ.S MOVLTZ.S MOVGEZ.S */ + int mv; + if (esk_lx6_win(c, t)) + return 0; + v = esk_lx6_ar(c, (int)t); + mv = op2 == 8 ? v == 0 : op2 == 9 ? v != 0 : op2 == 10 ? (s32)v < 0 : (s32)v >= 0; + if (mv) + f[r] = f[s]; + return 0; + } + if (op2 == 12 || op2 == 13) { /* MOVF.S MOVT.S */ + if (((esk_lx6_br(c) >> t) & 1u) == (op2 == 13)) + f[r] = f[s]; + return 0; + } + return -1; + } + return -1; +} diff --git a/tools/importers/esprom.py b/tools/importers/esprom.py index 74716ce75..dd95dacf8 100644 --- a/tools/importers/esprom.py +++ b/tools/importers/esprom.py @@ -98,7 +98,9 @@ def build(elf: bytes, base: int, size: int, tables=(), words=(), aliases=()) -> entries = [struct.unpack_from("<3I", img, o - base) for o in range(start, end, 16)] for addr, data in sections(elf): for dst, dst_end, src in entries: - if dst <= addr and addr + len(data) <= dst_end and dst < dst_end: + if dst <= addr < dst_end: + # a section may outrun its entry by its alignment padding + # (the ESP32's .data_xtos_pro, 0x420 bytes for 0x418) o = src + (addr - dst) - base if 0 <= o and o + len(data) <= size: img[o:o + len(data)] = data From aa738f8c09bd867ebdc882c01f0fca60ca04475f Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 03:35:14 +0000 Subject: [PATCH 02/16] ESP32: DevKitC V4 board, LX6 unit test, ESP-IDF vendor scenario, docs - emblink/esp32_devkitc: the DevKitC V4's power path (BAT760, AMS1117-3.3), power LED, Boot and EN buttons with EN's RC, both 19-pin headers, from Espressif's schematic; three fixtures - test_lx6: programs assembled by Espressif's assembler (gen_lx6_programs.py -> lx6_programs.h) check the core's instructions, windowed recursion through the ROM's window vectors, exceptions, the timer interrupt, FPU, MAC16, and the APP_CPU's ROM data - tests/vendor/esp-idf: esp32_hello_world built for the esp32 target - the description's fidelity and provenance, CHANGELOG, STATUS, coverage - a zero-overhead loop is not taken back when its last instruction branches to LEND (the ROM's strcmp); the DFP accelerator's user registers; no debug hooks in the core --- CHANGELOG.md | 22 + catalog/boards/esp32_devkitc/board.json | 553 +++++++++++++++++- .../esp32_devkitc/tests/boot-button.json | 69 +++ .../esp32_devkitc/tests/reset-button.json | 78 +++ .../esp32_devkitc/tests/usb-powered.json | 82 +++ catalog/mcus/espressif/esp32/mcu.json | 56 +- core/mcu/mcu.c | 4 +- core/mcu/xtensa/lx6.c | 89 +-- docs/STATUS.md | 15 + docs/coverage.md | 56 ++ tests/unit/gen_lx6_programs.py | 294 ++++++++++ tests/unit/lx6_programs.h | 312 ++++++++++ tests/unit/test_lx6.c | 351 +++++++++++ .../examples/esp32_hello_world/project.json | 61 ++ .../examples/esp32_hello_world/scenario.json | 82 +++ tests/vendor/esp-idf/run.py | 23 +- 16 files changed, 2027 insertions(+), 120 deletions(-) create mode 100644 catalog/boards/esp32_devkitc/tests/boot-button.json create mode 100644 catalog/boards/esp32_devkitc/tests/reset-button.json create mode 100644 catalog/boards/esp32_devkitc/tests/usb-powered.json create mode 100644 tests/unit/gen_lx6_programs.py create mode 100644 tests/unit/lx6_programs.h create mode 100644 tests/unit/test_lx6.c create mode 100644 tests/vendor/esp-idf/examples/esp32_hello_world/project.json create mode 100644 tests/vendor/esp-idf/examples/esp32_hello_world/scenario.json diff --git a/CHANGELOG.md b/CHANGELOG.md index 1094af9ac..f7b911d9e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -5,6 +5,28 @@ versions follow semantic versioning. There is no release yet. ## Unreleased +### ESP32 in the machine framework: ESP-IDF boots on the ESP32-DevKitC V4 + +- Added the ESP32's two Xtensa LX6 cores as a framework core + (`core/mcu/xtensa/lx6.c`, `lx6fp.c`, backend `xtensa`): the configuration + Espressif's core-isa.h gives, windowed registers with their overflow and + underflow, loops, XEA2 exceptions, 32 interrupts at their levels, the + CCOMPARE timers, MAC16, booleans, the FPU, region protection and the debug + option; the APP_CPU held until DPORT releases it, with its own view of the + ROM's data pointers. +- Added `espressif/esp32`: the memory map, the ROM image made from + Espressif's ROM ELF (`esprom.py` now places sections that outrun their + copy-table entry; the image equals QEMU's esp32-v3-rom.bin), the register + file from esp32.svd, and models for DPORT (APP_CPU, caches and flash MMU, + interrupt matrix), RTC_CNTL, eFuse, APB_CTRL clocks, GPIO/IO_MUX with + strapping, UART0-2, TIMG0/1, SPI0/1 with the GT25Q32A flash, SHA, the + internal analog I2C, RNG and the AHB view. +- Added the `emblink/esp32_devkitc` board (ESP32-DevKitC V4, WROOM-32E) with + its power path, LED, Boot and EN buttons, headers and fixtures. +- Espressif's ROM, ESP-IDF v5.4's bootloader and hello_world run unmodified + through `esp_restart` (`tests/vendor/esp-idf`, example `esp32_hello_world`, + 9/9); `test_lx6` checks the core with programs from Espressif's assembler. + ### Original ESP32 digital per-pin hold - Added the SDK-mapped digital hold register and per-pad capture masks. diff --git a/catalog/boards/esp32_devkitc/board.json b/catalog/boards/esp32_devkitc/board.json index 2068109da..d98c1ccf4 100644 --- a/catalog/boards/esp32_devkitc/board.json +++ b/catalog/boards/esp32_devkitc/board.json @@ -2,24 +2,541 @@ "schema_version": 1, "kind": "board", "id": "emblink/esp32_devkitc", - "version": "0.1.0", + "version": "1.0.0", "name": "ESP32-DevKitC V4", - "description": "Espressif's ESP32-DevKitC V4 with an ESP32-WROOM-32E module.", - "keywords": ["esp32", "devkitc", "esp32-wroom-32e", "xtensa", "espressif"], + "description": "Espressif's ESP32-DevKitC V4 with an ESP32-WROOM-32E module (the ESP32-D0WD-V3 with its 40 MHz crystal and 4 MB of flash), the AMS1117-3.3 regulator making 3.3 V from the micro-USB's 5 V through a BAT760 Schottky, the red power LED, the Boot button on GPIO0, the EN button on CHIP_PU with its RC, and two 19-pin headers. The CP2102N's USB-to-UART bridge on UART0 (GPIO1/GPIO3) is the session's serial console, and a serial port on the host (embsim serve --serial). The firmware is a flash image (bin), as idf.py and esptool write it.", + "keywords": [ + "esp32", + "devkitc", + "esp32-devkitc-v4", + "esp32-wroom-32e", + "xtensa", + "espressif", + "cp2102n" + ], "revision": "V4", - "mcu": {"ref": "espressif/esp32", "package": "wroom32e", "instance": "U1"}, - "oscillators": {"hse": {"hz": 40000000, "source": "external_crystal"}}, - "components": [], + "mcu": { + "ref": "espressif/esp32", + "package": "wroom32e", + "instance": "U1" + }, + "oscillators": { + "hse": { + "hz": 40000000, + "source": "external_crystal" + } + }, + "components": [ + { + "id": "D2", + "component": "emblink/diode_schottky", + "params": { + "part": "generic" + }, + "doc": "BAT760-7: the USB's VBUS to the board's 5 V (EXT_5V), so 5 V fed at the header does not reach the host (the generic Schottky's model)" + }, + { + "id": "U2", + "component": "emblink/regulator", + "params": { + "part": "AMS1117-3.3" + }, + "doc": "AMS1117-3.3: 3.3 V from 5 V for the module and the bridge" + }, + { + "id": "C21", + "component": "emblink/capacitor", + "params": { + "capacitance": "22u" + }, + "doc": "U2's input capacitor, 22 uF/10 V" + }, + { + "id": "C22", + "component": "emblink/capacitor", + "params": { + "capacitance": "100n" + }, + "doc": "U2's input decoupling, 0.1 uF/50 V" + }, + { + "id": "C1", + "component": "emblink/capacitor", + "params": { + "capacitance": "22u" + }, + "doc": "U2's output capacitor, 22 uF/10 V" + }, + { + "id": "C3", + "component": "emblink/capacitor", + "params": { + "capacitance": "22u" + }, + "doc": "The 3.3 V rail's bulk capacitor at the module, 22 uF/10 V" + }, + { + "id": "R2", + "component": "emblink/resistor", + "params": { + "resistance": "2k" + }, + "doc": "D1's resistor" + }, + { + "id": "D1", + "component": "emblink/led", + "params": { + "color": "red" + }, + "doc": "The power-on LED" + }, + { + "id": "R11", + "component": "emblink/resistor", + "params": { + "resistance": "10k" + }, + "doc": "EN's pull-up to 3.3 V" + }, + { + "id": "C9", + "component": "emblink/capacitor", + "params": { + "capacitance": "100n" + }, + "doc": "EN's 0.1 uF: with R11 it delays the chip's start after power-up (the RC the datasheet asks for)" + }, + { + "id": "SW2", + "component": "emblink/push_button", + "doc": "EN: joins EN to ground (reset)" + }, + { + "id": "SW1", + "component": "emblink/push_button", + "doc": "Boot: joins GPIO0 to ground; held through a reset, the ROM waits for a download" + }, + { + "id": "J2", + "component": "emblink/header", + "params": { + "pins": 19 + }, + "doc": "The left header (CON19X1_2P54)" + }, + { + "id": "J3", + "component": "emblink/header", + "params": { + "pins": 19 + }, + "doc": "The right header (CON19X1_2P54)" + } + ], "nets": { - "3V3": ["U1.VDD3P3"], - "GND": ["U1.GND"], - "EN": ["U1.CHIP_EN"], - "GPIO0": ["U1.GPIO0"], - "GPIO1": ["U1.GPIO1"], - "GPIO3": ["U1.GPIO3"] - }, - "ports": {}, - "console": {"peripheral": "UART0", "tx": "GPIO1", "rx": "GPIO3", "baud": 115200}, - "fidelity": {"functional": {"claims": "Work in progress.", "omissions": [], "validation": []}}, - "provenance": {"author": "EmbSIM", "license": "Apache-2.0", "sources": []} -} + "VBUS": [ + "D2.A" + ], + "5V": [ + "D2.K", + "U2.IN", + "C21.1", + "C22.1", + "J2.19" + ], + "3V3": [ + "U2.OUT", + "C1.1", + "C3.1", + "U1.VDD3P3", + "R2.1", + "R11.1", + "J2.1" + ], + "GND": [ + "U2.GND", + "C21.2", + "C22.2", + "C1.2", + "C3.2", + "D1.K", + "C9.2", + "SW2.2", + "SW1.2", + "U1.GND", + "J2.14", + "J3.1", + "J3.7" + ], + "D1_A": [ + "R2.2", + "D1.A" + ], + "EN": [ + "U1.CHIP_EN", + "R11.2", + "C9.1", + "SW2.1", + "J2.2" + ], + "GPIO36": [ + "U1.GPIO36", + "J2.3" + ], + "GPIO39": [ + "U1.GPIO39", + "J2.4" + ], + "GPIO34": [ + "U1.GPIO34", + "J2.5" + ], + "GPIO35": [ + "U1.GPIO35", + "J2.6" + ], + "GPIO32": [ + "U1.GPIO32", + "J2.7" + ], + "GPIO33": [ + "U1.GPIO33", + "J2.8" + ], + "GPIO25": [ + "U1.GPIO25", + "J2.9" + ], + "GPIO26": [ + "U1.GPIO26", + "J2.10" + ], + "GPIO27": [ + "U1.GPIO27", + "J2.11" + ], + "GPIO14": [ + "U1.GPIO14", + "J2.12" + ], + "GPIO12": [ + "U1.GPIO12", + "J2.13" + ], + "GPIO13": [ + "U1.GPIO13", + "J2.15" + ], + "GPIO23": [ + "U1.GPIO23", + "J3.2" + ], + "GPIO22": [ + "U1.GPIO22", + "J3.3" + ], + "GPIO1": [ + "U1.GPIO1", + "J3.4" + ], + "GPIO3": [ + "U1.GPIO3", + "J3.5" + ], + "GPIO21": [ + "U1.GPIO21", + "J3.6" + ], + "GPIO19": [ + "U1.GPIO19", + "J3.8" + ], + "GPIO18": [ + "U1.GPIO18", + "J3.9" + ], + "GPIO5": [ + "U1.GPIO5", + "J3.10" + ], + "GPIO17": [ + "U1.GPIO17", + "J3.11" + ], + "GPIO16": [ + "U1.GPIO16", + "J3.12" + ], + "GPIO4": [ + "U1.GPIO4", + "J3.13" + ], + "GPIO0": [ + "U1.GPIO0", + "J3.14", + "SW1.1" + ], + "GPIO2": [ + "U1.GPIO2", + "J3.15" + ], + "GPIO15": [ + "U1.GPIO15", + "J3.16" + ] + }, + "ports": { + "VBUS": { + "net": "VBUS", + "doc": "The micro-USB connector's VBUS: where a USB host's 5 V comes in" + }, + "3V3": { + "net": "3V3", + "connector": "J2", + "pin": 1 + }, + "EN": { + "net": "EN", + "connector": "J2", + "pin": 2, + "doc": "CHIP_PU: low holds the chip off and in reset" + }, + "VP": { + "net": "GPIO36", + "connector": "J2", + "pin": 3 + }, + "VN": { + "net": "GPIO39", + "connector": "J2", + "pin": 4 + }, + "IO34": { + "net": "GPIO34", + "connector": "J2", + "pin": 5 + }, + "IO35": { + "net": "GPIO35", + "connector": "J2", + "pin": 6 + }, + "IO32": { + "net": "GPIO32", + "connector": "J2", + "pin": 7 + }, + "IO33": { + "net": "GPIO33", + "connector": "J2", + "pin": 8 + }, + "IO25": { + "net": "GPIO25", + "connector": "J2", + "pin": 9 + }, + "IO26": { + "net": "GPIO26", + "connector": "J2", + "pin": 10 + }, + "IO27": { + "net": "GPIO27", + "connector": "J2", + "pin": 11 + }, + "IO14": { + "net": "GPIO14", + "connector": "J2", + "pin": 12 + }, + "IO12": { + "net": "GPIO12", + "connector": "J2", + "pin": 13 + }, + "GND": { + "net": "GND", + "connector": "J2", + "pin": 14 + }, + "IO13": { + "net": "GPIO13", + "connector": "J2", + "pin": 15 + }, + "5V": { + "net": "5V", + "connector": "J2", + "pin": 19 + }, + "GND1": { + "net": "GND", + "connector": "J3", + "pin": 1 + }, + "IO23": { + "net": "GPIO23", + "connector": "J3", + "pin": 2 + }, + "IO22": { + "net": "GPIO22", + "connector": "J3", + "pin": 3 + }, + "TX": { + "net": "GPIO1", + "connector": "J3", + "pin": 4, + "doc": "GPIO1, U0TXD: also the bridge's RXD" + }, + "RX": { + "net": "GPIO3", + "connector": "J3", + "pin": 5, + "doc": "GPIO3, U0RXD: also the bridge's TXD" + }, + "IO21": { + "net": "GPIO21", + "connector": "J3", + "pin": 6 + }, + "GND2": { + "net": "GND", + "connector": "J3", + "pin": 7 + }, + "IO19": { + "net": "GPIO19", + "connector": "J3", + "pin": 8 + }, + "IO18": { + "net": "GPIO18", + "connector": "J3", + "pin": 9 + }, + "IO5": { + "net": "GPIO5", + "connector": "J3", + "pin": 10 + }, + "IO17": { + "net": "GPIO17", + "connector": "J3", + "pin": 11 + }, + "IO16": { + "net": "GPIO16", + "connector": "J3", + "pin": 12 + }, + "IO4": { + "net": "GPIO4", + "connector": "J3", + "pin": 13 + }, + "IO0": { + "net": "GPIO0", + "connector": "J3", + "pin": 14, + "doc": "GPIO0, a strapping pin: the Boot button" + }, + "IO2": { + "net": "GPIO2", + "connector": "J3", + "pin": 15 + }, + "IO15": { + "net": "GPIO15", + "connector": "J3", + "pin": 16 + } + }, + "leds": [ + { + "name": "power", + "component": "D1", + "color": "red" + } + ], + "buttons": [ + { + "name": "boot", + "component": "SW1", + "gpio": "GPIO0", + "active": "low" + }, + { + "name": "reset", + "component": "SW2", + "signal": "CHIP_EN", + "active": "low" + } + ], + "console": { + "peripheral": "UART0", + "tx": "GPIO1", + "rx": "GPIO3", + "baud": 115200, + "bridge": { + "part": "CP2102N-A02-GQFN28", + "usb": { + "vid": "0x10C4", + "pid": "0xEA60", + "product": "CP2102N USB to UART Bridge Controller" + } + } + }, + "toolchains": { + "gcc-xtensa": { + "cpu": "esp32", + "flags": [ + "-mlongcalls" + ] + } + }, + "fidelity": { + "functional": { + "claims": "Nets, ports, the power LED and the two buttons as parts; the ESP32 runs its firmware from the flash image (see its description): Espressif's own ROM, the second-stage bootloader and the app, as on the board. EN pulls CHIP_PU low and the chip starts again with rst:0x1 (POWERON_RESET); Boot held through it makes the ROM wait for a download. The CP2102N's port is the session's console on UART0 (GPIO1/GPIO3) and a serial port on the host.", + "omissions": [ + "the CP2102N itself: its USB enumeration, its modem lines and so the auto-program circuit (Q1, Q2 and R21, R22 that let esptool's DTR and RTS drive EN and GPIO0): pressing Boot and EN does what they do", + "the ESD diodes on the USB lines (LESD5D5.0CT1G) and the USB connector", + "the flash pins GPIO6-11 on the headers (D0-D3, CMD, CLK): the module keeps them for its flash and the ports leave them out", + "the artwork and the bench model" + ], + "validation": [] + }, + "electrical": { + "claims": "The power path from the schematic: VBUS through the Schottky to 5 V, the AMS1117-3.3 to 3.3 V, the LED, the EN RC.", + "omissions": [], + "validation": [] + } + }, + "provenance": { + "author": "EmbSIM", + "license": "Apache-2.0", + "sources": [ + { + "title": "ESP32-DevKitC V4 schematic (Espressif)", + "rev": "V4, 2020-02-25", + "url": "https://dl.espressif.com/dl/schematics/esp32_devkitc_v4_sch.pdf" + }, + { + "title": "ESP32-DevKitC V4 user guide (Espressif esp-dev-kits)", + "url": "https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32/esp32-devkitc/user_guide.html" + }, + { + "title": "ESP32-WROOM-32E & ESP32-WROOM-32UE datasheet (Espressif)", + "rev": "v1.7" + } + ], + "notes": "Nets and parts read from the schematic's text and the user guide's header table." + }, + "tests": [ + "tests/*.json" + ] +} \ No newline at end of file diff --git a/catalog/boards/esp32_devkitc/tests/boot-button.json b/catalog/boards/esp32_devkitc/tests/boot-button.json new file mode 100644 index 000000000..d65737702 --- /dev/null +++ b/catalog/boards/esp32_devkitc/tests/boot-button.json @@ -0,0 +1,69 @@ +{ + "schema_version": 1, + "kind": "component_test", + "name": "boot-button", + "description": "Boot (SW1) joins GPIO0 to ground while held.", + "policy": "electrical", + "until": "60ms", + "circuit": { + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc" + } + ], + "components": [ + { + "id": "HOST", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5.0 + } + }, + { + "id": "CABLE", + "component": "emblink/resistor", + "params": { + "resistance": 0.25 + } + }, + { + "id": "G", + "component": "emblink/gnd" + } + ], + "nets": { + "HOSTV": [ + "HOST.+", + "CABLE.1" + ], + "VBUS": [ + "CABLE.2", + "B1.VBUS" + ], + "GND": [ + "HOST.-", + "G.GND", + "B1.GND1" + ], + "IO0": [ + "B1.IO0" + ] + } + }, + "inputs": [ + { + "at": "40ms", + "target": "B1.SW1", + "input": "pressed", + "value": true + } + ], + "expect": { + "net:IO0": { + "at": "55ms", + "max_v": 0.05 + } + } +} \ No newline at end of file diff --git a/catalog/boards/esp32_devkitc/tests/reset-button.json b/catalog/boards/esp32_devkitc/tests/reset-button.json new file mode 100644 index 000000000..c24f45f48 --- /dev/null +++ b/catalog/boards/esp32_devkitc/tests/reset-button.json @@ -0,0 +1,78 @@ +{ + "schema_version": 1, + "kind": "component_test", + "name": "reset-button", + "description": "EN (SW2) holds CHIP_PU low while pressed; C9 brings it back up through R11 once released.", + "policy": "electrical", + "until": "90ms", + "circuit": { + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc" + } + ], + "components": [ + { + "id": "HOST", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5.0 + } + }, + { + "id": "CABLE", + "component": "emblink/resistor", + "params": { + "resistance": 0.25 + } + }, + { + "id": "G", + "component": "emblink/gnd" + } + ], + "nets": { + "HOSTV": [ + "HOST.+", + "CABLE.1" + ], + "VBUS": [ + "CABLE.2", + "B1.VBUS" + ], + "GND": [ + "HOST.-", + "G.GND", + "B1.GND1" + ], + "EN": [ + "B1.EN" + ] + } + }, + "inputs": [ + { + "at": "60ms", + "target": "B1.SW2", + "input": "pressed", + "value": true + }, + { + "at": "70ms", + "target": "B1.SW2", + "input": "pressed", + "value": false + } + ], + "expect": { + "net:EN": { + "between": [ + "62ms", + "70ms" + ], + "max_v": 0.05 + } + } +} \ No newline at end of file diff --git a/catalog/boards/esp32_devkitc/tests/usb-powered.json b/catalog/boards/esp32_devkitc/tests/usb-powered.json new file mode 100644 index 000000000..f7aab7201 --- /dev/null +++ b/catalog/boards/esp32_devkitc/tests/usb-powered.json @@ -0,0 +1,82 @@ +{ + "schema_version": 1, + "kind": "component_test", + "name": "usb-powered", + "description": "Plugged into a computer's USB port through a 0.25 ohm cable: D2 passes VBUS to 5V less its Schottky drop, U2 (AMS1117-3.3) makes 3V3, D1 glows (about 0.6 mA through R2's 2 k) and R11 holds EN high.", + "policy": "electrical", + "until": "60ms", + "circuit": { + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc" + } + ], + "components": [ + { + "id": "HOST", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5.0 + } + }, + { + "id": "CABLE", + "component": "emblink/resistor", + "params": { + "resistance": 0.25 + } + }, + { + "id": "G", + "component": "emblink/gnd" + } + ], + "nets": { + "HOSTV": [ + "HOST.+", + "CABLE.1" + ], + "VBUS": [ + "CABLE.2", + "B1.VBUS" + ], + "GND": [ + "HOST.-", + "G.GND", + "B1.GND1" + ], + "V5": [ + "B1.5V" + ], + "V33": [ + "B1.3V3" + ], + "EN": [ + "B1.EN" + ] + } + }, + "expect": { + "net:V5": { + "at": "50ms", + "min_v": 4.5, + "max_v": 4.95 + }, + "net:V33": { + "at": "50ms", + "min_v": 3.25, + "max_v": 3.35 + }, + "net:EN": { + "at": "50ms", + "min_v": 3.2, + "max_v": 3.35 + }, + "output:B1.D1.luminance": { + "at": "50ms", + "min": 0.01 + } + } +} \ No newline at end of file diff --git a/catalog/mcus/espressif/esp32/mcu.json b/catalog/mcus/espressif/esp32/mcu.json index 62e1209d2..6bedac0a6 100644 --- a/catalog/mcus/espressif/esp32/mcu.json +++ b/catalog/mcus/espressif/esp32/mcu.json @@ -4,7 +4,7 @@ "id": "espressif/esp32", "version": "0.1.0", "name": "ESP32", - "description": "Espressif ESP32 (ESP32-D0WD-V3, chip revision v3.1): two Xtensa LX6 cores at up to 240 MHz, 520 KiB of SRAM, 448 KiB of ROM, 16 KiB of RTC memory, external SPI flash behind the cores' caches, Wi-Fi and Bluetooth.", + "description": "Espressif ESP32 (ESP32-D0WD-V3, chip revision v3.1): two Xtensa LX6 cores at up to 240 MHz, 520 KiB of SRAM, 448 KiB of ROM, 16 KiB of RTC memory, external SPI flash behind the cores' caches, Wi-Fi and Bluetooth; the ESP32-DevKitC's MCU. Espressif's ROM, ESP-IDF's second-stage bootloader and ESP-IDF applications run on both cores; the radios are not yet modelled.", "keywords": [ "xtensa", "lx6", @@ -32,7 +32,8 @@ "size": "448K", "kind": "rom", "file": "rom.bin", - "doc": "Internal ROM0 (384 KiB) and ROM1 (64 KiB) on the instruction bus (TRM v5 table 3.3-1, ESP-IDF's SOC_IROM_MASK_HIGH 0x40070000): the boot ROM of chip revision v3, its image made by tools/importers/esprom.py (--base 0x40000000 --size 0x70000 --data-table 0x4000D4EC:0x4000D4F8, the Bluetooth controller's entry; --data-table 0x4000D4F8:0x4000D5C8, the ROM's copy table of its RAM variables' initial values) from Espressif's esp32_rev300_rom.elf (espressif/esp-rom-elfs 20241011, Apache-2.0: LICENSES/Apache-2.0.txt; the ROM's code is Copyright (c) 2015-2022 Espressif Systems (Shanghai) Co. Ltd.). It equals byte for byte the image Espressif's QEMU loads (esp32-v3-rom.bin, sha256 9115bbcd...258b) over its 455,722 bytes; the rest reads zeros" + "doc": "Internal ROM0 (384 KiB) and ROM1 (64 KiB) on the instruction bus (TRM v5 table 3.3-1, ESP-IDF's SOC_IROM_MASK_HIGH 0x40070000): the boot ROM of chip revision v3, its image made by tools/importers/esprom.py (--base 0x40000000 --size 0x70000 --data-table 0x4000D4EC:0x4000D4F8, the Bluetooth controller's entry; --data-table 0x4000D4F8:0x4000D5C8, the ROM's copy table of its RAM variables' initial values) from Espressif's esp32_rev300_rom.elf (espressif/esp-rom-elfs 20241011, Apache-2.0: LICENSES/Apache-2.0.txt; the ROM's code is Copyright (c) 2015-2022 Espressif Systems (Shanghai) Co. Ltd.). It equals byte for byte the image Espressif's QEMU loads (esp32-v3-rom.bin, sha256 9115bbcd...258b) over its 455,722 bytes; the rest reads zeros", + "sha256": "ee235a76e8e5afd5bed9d674587e001d8cde459a659edef9072cbc867fd31313" }, { "name": "rom1_data", @@ -220,18 +221,36 @@ }, "fidelity": { "functional": { - "claims": "Work in progress.", - "omissions": [], - "validation": [] + "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), the internal analog I2C master, the random number generator and the peripherals' AHB view.", + "omissions": [ + "Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written)", + "the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept", + "PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts", + "the peripherals without a model yet: I2C0/1, I2S0/1, SPI2/3 (HSPI, VSPI), RMT, LEDC, MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption", + "sleep modes (light and deep sleep, the power domains), brown-out", + "the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection" + ], + "validation": [ + "tests/unit/test_lx6.c: programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16), and the APP_CPU's ROM data kept apart", + "tests/vendor/esp-idf: ESP-IDF v5.4's hello_world built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart", + "the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin" + ] }, "timed": { - "claims": "Instruction timing estimated.", - "omissions": [], + "claims": "Instruction timing estimated: one cycle, a taken branch, jump, call or return three, MULL two, a division twelve, an exception's entry three; CCOUNT counts those cycles. The clocks follow the registers: CPU_CLK from XTAL (40 MHz out of reset), the PLL's 80, 160 or 240 MHz, or RC_FAST; APB_CLK; RTC_SLOW_CLK at the RC oscillator's nominal 150 kHz.", + "omissions": [ + "the LX6 pipeline's interlocks and the loop buffer's timing", + "cache misses and flash latency (the SPI transfers' bus time is counted on SPI1, the flash's own program and erase times too)", + "the RC oscillators' error and drift" + ], "validation": [] }, "electrical": { - "claims": "GPIO pin-model defaults at 3.3 V.", - "omissions": [], + "claims": "GPIO pin-model defaults at 3.3 V from the datasheet's DC characteristics: VIH 0.75 VDD, VIL 0.25 VDD, VOH 0.8 VDD, VOL 0.1 VDD, 45 kOhm pulls; GPIO34-39 inputs only.", + "omissions": [ + "the supply current (the datasheet's power modes are not yet in the description)", + "the pads' drive strengths' effect" + ], "validation": [] } }, @@ -241,22 +260,33 @@ "sources": [ { "title": "ESP32 Technical Reference Manual", - "rev": "v5.2" + "rev": "v5" }, { "title": "ESP32 Series Datasheet", - "rev": "v4.8" + "rev": "v4" }, { "title": "Espressif esp32.svd (espressif/svd)", "rev": "be20aa1" }, { - "title": "Espressif esp-rom-elfs, esp32_rev300_rom.elf", + "title": "Espressif esp-rom-elfs, esp32_rev300_rom.elf (sha256 920b70635440517866aab2230964a570d2cf2b676658d93c52fbac108c1cca31)", "rev": "20241011" + }, + { + "title": "Espressif ESP-IDF, components/xtensa/esp32/include/xtensa/config/core-isa.h and esp32.rom.ld", + "rev": "v5.4" + }, + { + "title": "Cadence Xtensa Instruction Set Architecture Reference Manual" + }, + { + "title": "Giantec GT25Q32A-U datasheet (the module's flash)", + "rev": "V2.5" } ], - "notes": "The register description is converted from Espressif's Apache-2.0 SVD; the boot ROM's image from Espressif's Apache-2.0 ROM ELF." + "notes": "The register description is converted from Espressif's Apache-2.0 SVD; the boot ROM's image from Espressif's Apache-2.0 ROM ELF; the instruction encodings checked against Espressif's assembler." }, "signals": [ "GPIO0", diff --git a/core/mcu/mcu.c b/core/mcu/mcu.c index dc2222bab..08a3404d5 100644 --- a/core/mcu/mcu.c +++ b/core/mcu/mcu.c @@ -1167,8 +1167,8 @@ static int irq_entry(const mcu_state *st, int n) return -1; if (!strcmp(arch, "cortex-m") || !strcmp(arch, "mips")) want = n - 16; /* 16 + the vector */ - else if (!strcmp(arch, "riscv")) - return -1; + else if (!strcmp(arch, "riscv") || !strcmp(arch, "xtensa")) + return -1; /* causes and CPU interrupt numbers, not the matrix's sources */ else want = n; /* the vector itself (an AVR's, a PIC24's) */ for (i = 0; want >= 0 && i < rf->nirq; i++) diff --git a/core/mcu/xtensa/lx6.c b/core/mcu/xtensa/lx6.c index f6df523be..e08dc1f8a 100644 --- a/core/mcu/xtensa/lx6.c +++ b/core/mcu/xtensa/lx6.c @@ -57,7 +57,6 @@ * notes on the ESP32's interrupt levels and types it agrees with. */ #include #include -#include #include #include "mcu/xtensa/lx6.h" @@ -155,7 +154,6 @@ struct lx6 { int jumped; /* it branched, jumped, called or returned: no loop-back */ int waiti; /* waiting in WAITI */ u32 cost; - char xml[1]; /* no target description */ }; enum { CORE_RUN, CORE_SLEEP, CORE_HELD, CORE_STALLED }; @@ -379,10 +377,6 @@ int esk_lx6_store(struct lx6 *c, u32 a, int n, u32 v) struct esk_bus *b = &c->m->bus; struct esk_region *r; int i; -#ifdef LX6_DEBUG_TRACE - if (getenv("LX6_WATCH") && a == (u32)strtoul(getenv("LX6_WATCH"), 0, 16)) - fprintf(stderr, "WATCH core %d pc %08x writes %08x a0=%08x\n", c->id, (unsigned)c->pc, (unsigned)v, (unsigned)AR(c, 0)); -#endif if (prohibited(c->dtlb[a >> 29])) { mem_exception(c, EXC_STORE_PROHIBITED, a); return -1; @@ -1505,76 +1499,6 @@ static void exec(struct lx6 *c, u32 w, u32 len) esk_lx6_illegal(c); } -#ifdef LX6_DEBUG_TRACE -#define RING 65536 -static char ring[RING][96]; -static unsigned ring_n; -static FILE *ring_f; -static void ring_dump(void) -{ - unsigned i, n = ring_n < RING ? ring_n : RING; - for (i = 0; i < n; i++) - fputs(ring[(ring_n - n + i) % RING], ring_f); - fclose(ring_f); -} -static void lx6_debug_trace(struct lx6 *c, u32 w) -{ - static int opened; - if (!opened) { - const char *e = getenv("LX6_TRACE"); - opened = 1; - ring_f = e ? fopen(e, "w") : 0; - if (ring_f) - atexit(ring_dump); - } - { - static u32 stop_pc; - static int got; - if (!got) { - const char *e = getenv("LX6_STOP_PC"); - got = 1; - stop_pc = e ? (u32)strtoul(e, 0, 16) : 0; - } - { - static u32 logs[32]; - static int nlogs = -1; - int q; - if (nlogs < 0) { - const char *e = getenv("LX6_LOG_PCS"); - nlogs = 0; - while (e && *e && nlogs < 32) { - char *end; - logs[nlogs++] = (u32)strtoul(e, &end, 16); - e = *end ? end + 1 : end; - } - } - for (q = 0; q < nlogs; q++) - if (c->pc == logs[q]) { - char str[40]; - int z; - for (z = 0; z < 39; z++) { - u32 ch = 0; - if (esk_bus_debug_read(&c->m->bus, AR(c, 3) + (u32)z, 1, &ch) || ch < 32 || ch > 126) - break; - str[z] = (char)ch; - } - str[z] = 0; - fprintf(stderr, "PCLOG core %d at %08x cycles %llu a0=%08x a2=%08x a3=%08x a4=%08x s3=%s\n", c->id, - (unsigned)c->pc, (unsigned long long)c->m->cycles, (unsigned)AR(c, 0), (unsigned)AR(c, 2), - (unsigned)AR(c, 3), (unsigned)AR(c, 4), str); - } - } - if (stop_pc && c->pc == stop_pc) { - fprintf(stderr, "LX6_STOP_PC hit on core %d\n", c->id); - exit(0); - } - } - if (ring_f) - snprintf(ring[ring_n++ % RING], 96, "%d %08x %06x a0=%08x a1=%08x a2=%08x a3=%08x\n", c->id, - (unsigned)c->pc, (unsigned)w, (unsigned)AR(c, 0), (unsigned)AR(c, 1), (unsigned)AR(c, 2), - (unsigned)AR(c, 3)); -} -#endif /* ---- interrupts and a step -------------------------------------------- */ @@ -1653,9 +1577,6 @@ static void core_step(struct lx6 *c) c->npc = c->pc + len; c->jumped = 0; m->insns++; -#ifdef LX6_DEBUG_TRACE - lx6_debug_trace(c, w); -#endif if ((w & 15u) >= 14u) esk_lx6_illegal(c); else @@ -1902,7 +1823,6 @@ static u32 get(const u8 *b) static u32 *reg_ptr(struct lx6 *c, int n) { - static u32 zero; if (n == GR_PC) return &c->pc; if (n >= GR_AR && n < GR_AR + 64) @@ -1928,8 +1848,13 @@ static u32 *reg_ptr(struct lx6 *c, int n) case GR_FCR: return &c->fcr; case GR_FSR: return &c->fsr; } - zero = 0; - return n == 71 || n == 72 || (n >= 83 && n <= 86) ? &zero : 0; + switch (n) { + case 83: return &c->expstate; + case 84: return &c->f64r_lo; + case 85: return &c->f64r_hi; + case 86: return &c->f64s; + } + return 0; } static int core_reg_read(struct lx6 *c, int n, u8 *buf) diff --git a/docs/STATUS.md b/docs/STATUS.md index a8394f400..d43415860 100644 --- a/docs/STATUS.md +++ b/docs/STATUS.md @@ -5,6 +5,21 @@ maintained by hand until evidence tooling exists. It is not a generated support matrix. Specifications define target contracts; their acceptance does not mean the described behaviour exists. +## ESP32 on the machine framework (2026-11-08) + +The ESP32 now runs as a catalog MCU (`espressif/esp32`) on the +`emblink/esp32_devkitc` board: two Xtensa LX6 cores in the framework +(`core/mcu/xtensa/lx6.c`), the SoC models in `core/mcu/esp32/soc/`, and +Espressif's ROM (ECO3), ESP-IDF v5.4's second-stage bootloader and its +hello_world running unmodified on both cores at 160 MHz to `Hello world!` +and through `esp_restart` (rst:0xc SW_CPU_RESET). Evidence: `test_lx6` +(4,332 checks), the board's three fixtures, and the ESP-IDF vendor +scenario `esp32_hello_world` (9/9). Not yet: Wi-Fi and Bluetooth, the +double-precision accelerator's instructions, the peripherals the +description's fidelity lists (I2C, I2S, SPI2/3, RMT, LEDC, ADC, ...), +sleep. The standalone harness below remains as its own qualification +fixtures. + ## Original ESP32 dual-core target investigation (2026-11-04) **Latest digital pad-hold update:** [Per-pin digital hold](engineering/esp32-digital-pad-hold.md) diff --git a/docs/coverage.md b/docs/coverage.md index b112be32e..3c4dc6e27 100644 --- a/docs/coverage.md +++ b/docs/coverage.md @@ -8,6 +8,7 @@ evidence for each model is in [STATUS.md](STATUS.md). | MCU | Modelled | Registers only | Missing | Peripherals | |---|---|---|---|---| +| ESP32 | 14 | 0 | 31 | 45 | | ESP32-C3 | 35 | 0 | 0 | 35 | | ATmega328P | 15 | 0 | 0 | 15 | | PIC24FJ1024GB610 | 11 | 4 | 17 | 32 | @@ -19,6 +20,61 @@ evidence for each model is in [STATUS.md](STATUS.md). | STM32F446RE | 53 | 0 | 15 | 68 | | STM32F446ZE | 53 | 0 | 15 | 68 | +## ESP32 (`espressif/esp32`) + +Boards: ESP32-DevKitC V4. +14 of 45 peripherals modelled, 0 registers only, 31 missing. + +| Peripheral | Model | State | +|---|---|---| +| DPORT | `esp32-dport` | modelled | +| AES | — | **missing** | +| RSA | — | **missing** | +| SHA | `esp32-sha` | modelled | +| UART0 | `esp32-uart` | modelled | +| SPI1 | `esp32-spi` | modelled | +| SPI0 | `esp32-spi` | modelled | +| GPIO | `esp32-gpio` | modelled | +| GPIO_SD | — | **missing** | +| FLASH_ENCRYPTION | — | **missing** | +| FRC_TIMER | — | **missing** | +| RTC_CNTL | `esp32-rtc` | modelled | +| RTC_IO | — | **missing** | +| SENS | — | **missing** | +| RTC_I2C | — | **missing** | +| IO_MUX | `esp32-iomux` | modelled | +| HINF | — | **missing** | +| UHCI1 | — | **missing** | +| I2S0 | — | **missing** | +| UART1 | `esp32-uart` | modelled | +| I2C0 | — | **missing** | +| UHCI0 | — | **missing** | +| SLCHOST | — | **missing** | +| RMT | — | **missing** | +| PCNT | — | **missing** | +| SLC | — | **missing** | +| LEDC | — | **missing** | +| EFUSE | `esp32-efuse` | modelled | +| NRX | — | **missing** | +| BB | — | **missing** | +| MCPWM0 | — | **missing** | +| TIMG0 | `esp32-timg` | modelled | +| TIMG1 | `esp32-timg` | modelled | +| SPI2 | — | **missing** | +| SPI3 | — | **missing** | +| APB_CTRL | `esp32-apbctrl` | modelled | +| I2C1 | — | **missing** | +| SDHOST | — | **missing** | +| EMAC_DMA | — | **missing** | +| EMAC_EXT | — | **missing** | +| EMAC_MAC | — | **missing** | +| TWAI0 | — | **missing** | +| MCPWM1 | — | **missing** | +| I2S1 | — | **missing** | +| UART2 | `esp32-uart` | modelled | + +Declared omissions: Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written); the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept; PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts; the peripherals without a model yet: I2C0/1, I2S0/1, SPI2/3 (HSPI, VSPI), RMT, LEDC, MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption; sleep modes (light and deep sleep, the power domains), brown-out; the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection. + ## ESP32-C3 (`espressif/esp32c3`) Boards: ESP32-C3-DevKitM-1. diff --git a/tests/unit/gen_lx6_programs.py b/tests/unit/gen_lx6_programs.py new file mode 100644 index 000000000..7e2bbb162 --- /dev/null +++ b/tests/unit/gen_lx6_programs.py @@ -0,0 +1,294 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: Apache-2.0 +# Copyright 2026 Junior Deogracias +"""Assemble test_lx6.c's programs with Espressif's Xtensa assembler and +write lx6_programs.h, so the test needs no toolchain. + + gen_lx6_programs.py --as xtensa-esp32-elf-as --objcopy xtensa-esp32-elf-objcopy + +Each program is linked at 0x40080000 (IRAM), its data at 0x3FFB0000. +The sources are the PROGRAMS below; their expected results are in +test_lx6.c, computed by hand from the Xtensa ISA reference.""" +import argparse +import subprocess +import sys +import tempfile +from pathlib import Path + +HERE = Path(__file__).resolve().parent + +PROGRAMS = { + # integer arithmetic and logic: results left in a2-a15 + "alu": """ + movi a2, 7 + movi a3, -3 + add a4, a2, a3 # 4 + addx4 a5, a2, a3 # 25 + subx8 a6, a2, a3 # 59 + neg a7, a3 # 3 + abs a8, a3 # 3 + min a9, a2, a3 # -3 + maxu a10, a2, a3 # 0xfffffffd + sext a11, a3, 7 # -3 + movi a12, 300 + clamps a12, a12, 7 # 127 + nsau a13, a2 # 29 + nsa a14, a3 # 29 + extui a15, a3, 4, 8 # 0xff + j . +""", + "shifts": """ + movi a2, 0x123 + slli a3, a2, 20 # 0x12300000 + srli a4, a3, 8 # 0x00123000 + movi a5, -256 + srai a6, a5, 4 # -16 + ssl a2 # shift left by a2 & 31 = 3 + sll a7, a2 # 0x918 + movi a8, 12 + ssr a8 + srl a9, a3 # 0x00012300 + sra a10, a5 # -1 + movi a11, 0x87654321 + ssai 8 + src a12, a11, a2 # (0x87654321:0x123) >> 8 = 0x21000001 + ssa8l a8 # sar = (12 & 3) * 8 = 0 + rsr.sar a13 # 0 + ssa8b a2 # sar = 32 - (0x123 & 3) * 8 = 8 + rsr.sar a14 # 8 + j . +""", + "muldiv": """ + movi a2, -7 + movi a3, 3 + mull a4, a2, a3 # -21 + muluh a5, a2, a3 # 2 + mulsh a6, a2, a3 # -1 + quos a7, a2, a3 # -2 + rems a8, a2, a3 # -1 + quou a9, a2, a3 # 0x55555553 + remu a10, a2, a3 # 0 + mul16u a11, a2, a3 # 0xfff9 * 3 = 0x2ffeb + mul16s a12, a2, a3 # -21 + movi a13, 0 + j . +""", + # a loop exited by a branch taken to LEND (the ROM's strcmp does it) + "loops": """ + movi a2, 0 + movi a3, 5 + loop a3, 1f + addi a2, a2, 1 +1: + movi a4, 0 + movi a5, 0 + loopnez a5, 2f + addi a4, a4, 1 +2: + movi a6, 0 + movi a7, 10 + movi a8, 0 + loop a8, 3f # LCOUNT 0xffffffff: only the branch leaves + addi a6, a6, 1 + addi a7, a7, -1 + beqz a7, 3f +3: + movi a9, 0 + movi a10, -2 + loopgtz a10, 4f + addi a9, a9, 1 +4: + j . +""", + "branches": """ + movi a2, 0 + movi a3, 0x80 + bbci a3, 7, 1f + addi a2, a2, 1 # taken path skips nothing: bit 7 is set +1: bbsi a3, 7, 2f + addi a2, a2, 16 # not reached +2: movi a4, 65536 + bltui a4, 32768, 3f + addi a2, a2, 2 # reached: 65536 >= 32768 +3: bgeui a4, 65536, 4f + addi a2, a2, 32 # not reached +4: movi a5, -1 + beqi a5, -1, 5f + addi a2, a2, 64 # not reached +5: movi a6, 0xf0 + movi a7, 0x30 + ball a6, a7, 6f + addi a2, a2, 128 # not reached +6: bnone a6, a7, 7f + addi a2, a2, 4 # reached +7: movi a8, 5 + bbs a3, a8, 8f # bit 5 of 0x80: clear + addi a2, a2, 8 # reached +8: j . +""", + "memory": """ + j 1f + .align 4 +lit: .word 0xcafef00d +1: + movi a2, 0x3ffb0000 + movi a3, 0x8081 + s16i a3, a2, 0 + l16si a4, a2, 0 # 0xffff8081 + l16ui a5, a2, 0 # 0x8081 + l8ui a6, a2, 1 # 0x80 + movi a7, 0x11223344 + s32i a7, a2, 4 + addi a15, a2, 3 + l32i a8, a15, 0 # unaligned: bytes 3..6, 0x22334400 + movi a9, 0x55 + wsr.scompare1 a9 + movi a10, 0x55 + s32i a10, a2, 8 + movi a11, 0x66 + s32c1i a11, a2, 8 # memory 0x55 == SCOMPARE1: stored; a11 = 0x55 + l32i a12, a2, 8 # 0x66 + movi a13, 0x77 + s32c1i a13, a2, 8 # 0x66 != 0x55: not stored; a13 = 0x66 + l32r a14, lit + j . +""", + # windowed calls deep enough to spill and fill through the ROM's vectors + "windows": """ + movi a1, 0x3ffb8000 + movi a3, 0x3ffb8100 # the outermost frame's caller's stack pointer + addi a4, a1, -16 + s32i a3, a4, 4 # at sp - 12, for WindowOverflow8 to find its save area + movi a10, 12 + call8 fib + mov a15, a10 + j . + .align 4 +fib: + entry a1, 32 + bltui a2, 2, 1f + addi a10, a2, -1 + call8 fib + mov a3, a10 + addi a10, a2, -2 + call8 fib + add a2, a3, a10 +1: retw +""", + # an exception and its return, through a vector table of the test's + "syscall": """ + movi a2, vectors + wsr.vecbase a2 + movi a3, 0 + syscall + addi a3, a3, 1 + j . + .align 1024 +vectors: + .org vectors + 0x300 +kernel: + rsr.exccause a4 + rsr.epc1 a5 + addi a5, a5, 3 + wsr.epc1 a5 + rfe +""", + # CCOMPARE0 against CCOUNT: the timer interrupt (6) at level 1 + "timer": """ + movi a2, vectors + wsr.vecbase a2 + movi a6, 0 + rsr.ccount a3 + addi a3, a3, 200 + wsr.ccompare0 a3 + movi a4, 1 << 6 + wsr.intenable a4 + rsil a5, 0 +1: beqz a6, 1b + j . + .align 1024 +vectors: + .org vectors + 0x300 +kernel: + rsr.exccause a7 + rsr.interrupt a8 + movi a6, 1 + movi a9, 0 + wsr.intenable a9 + rfe +""", + "float": """ + movi a2, 1 + wsr.cpenable a2 + rsync + movi a3, 3 + float.s f0, a3, 0 # 3.0 + movi a4, 5 + float.s f1, a4, 1 # 2.5 + add.s f2, f0, f1 # 5.5 + mul.s f3, f0, f1 # 7.5 + madd.s f2, f0, f1 # 5.5 + 7.5 = 13.0 + trunc.s a5, f2, 0 # 13 + round.s a6, f1, 0 # 2 (ties to even) + olt.s b0, f1, f0 + movi a7, 0 + movt a7, a4, b0 # 5: 2.5 < 3.0 + rfr a8, f3 # 0x40f00000 + j . +""", + "mac16": """ + movi a2, 0x00030004 + movi a3, 0xfffe0005 + mul.aa.ll a2, a3 # 4 * 5 = 20 + mula.aa.hh a2, a3 # + 3 * -2 = 14 + rsr.acclo a4 + rsr.acchi a5 + umul.aa.hl a2, a3 # 3 * 5 = 15 + rsr.acclo a6 + j . +""", +} + + +def main(argv=None) -> int: + ap = argparse.ArgumentParser(description=__doc__, formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("--as", dest="asm", default="xtensa-esp32-elf-as") + ap.add_argument("--ld", default="xtensa-esp32-elf-ld") + ap.add_argument("--objcopy", default="xtensa-esp32-elf-objcopy") + ap.add_argument("--nm", default="xtensa-esp32-elf-nm") + ap.add_argument("-o", "--output", type=Path, default=HERE / "lx6_programs.h") + args = ap.parse_args(argv) + out = ["/* SPDX-License-Identifier: Apache-2.0 */", + "/* Copyright 2026 Junior Deogracias */", + "/* lx6_programs.h -- test_lx6.c's programs, assembled by Espressif's", + " * xtensa-esp32-elf-as and linked at 0x40080000 by gen_lx6_programs.py", + " * (generated: do not edit; the sources are in the script). */", + "#ifndef LX6_PROGRAMS_H", "#define LX6_PROGRAMS_H", ""] + with tempfile.TemporaryDirectory() as tmp: + t = Path(tmp) + for name, src in PROGRAMS.items(): + s = t / f"{name}.S" + s.write_text(".text\n.literal_position\n.global _start\n_start:\n" + src, encoding="utf-8") + subprocess.run([args.asm, "--text-section-literals", "-o", str(t / f"{name}.o"), str(s)], check=True) + subprocess.run([args.ld, "-Ttext=0x40080000", "-o", str(t / f"{name}.elf"), str(t / f"{name}.o")], + check=True) + subprocess.run([args.objcopy, "-O", "binary", "-j", ".text", str(t / f"{name}.elf"), + str(t / f"{name}.bin")], check=True) + data = (t / f"{name}.bin").read_bytes() + syms = subprocess.run([args.nm, str(t / f"{name}.elf")], check=True, capture_output=True, + text=True).stdout.split("\n") + entry = next(int(x.split()[0], 16) for x in syms if x.endswith(" _start")) + out.append(f"#define PROG_{name.upper()}_ENTRY 0x{entry:08X}u") + out.append(f"static const unsigned char prog_{name}[{len(data)}] = {{") + for i in range(0, len(data), 16): + out.append(" " + " ".join(f"0x{b:02x}," for b in data[i:i + 16])) + out.append("};") + out.append("") + out += ["#endif", ""] + args.output.write_text("\n".join(out), encoding="utf-8") + print(f"{args.output}: {len(PROGRAMS)} programs") + return 0 + + +if __name__ == "__main__": + sys.exit(main()) diff --git a/tests/unit/lx6_programs.h b/tests/unit/lx6_programs.h new file mode 100644 index 000000000..8326b4dc3 --- /dev/null +++ b/tests/unit/lx6_programs.h @@ -0,0 +1,312 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* lx6_programs.h -- test_lx6.c's programs, assembled by Espressif's + * xtensa-esp32-elf-as and linked at 0x40080000 by gen_lx6_programs.py + * (generated: do not edit; the sources are in the script). */ +#ifndef LX6_PROGRAMS_H +#define LX6_PROGRAMS_H + +#define PROG_ALU_ENTRY 0x40080000u +static const unsigned char prog_alu[45] = { + 0x0c, 0x72, 0x7c, 0xd3, 0x3a, 0x42, 0x30, 0x52, 0xa0, 0x30, 0x62, 0xf0, 0x30, 0x70, 0x60, 0x30, + 0x81, 0x60, 0x30, 0x92, 0x43, 0x30, 0xa2, 0x73, 0x00, 0xb3, 0x23, 0xc2, 0xa1, 0x2c, 0x00, 0xcc, + 0x33, 0xd0, 0xf2, 0x40, 0xe0, 0xe3, 0x40, 0x30, 0xf4, 0x74, 0x06, 0xff, 0xff, +}; + +#define PROG_SHIFTS_ENTRY 0x40080004u +static const unsigned char prog_shifts[60] = { + 0x21, 0x43, 0x65, 0x87, 0x22, 0xa1, 0x23, 0xc0, 0x32, 0x01, 0x30, 0x48, 0x41, 0x52, 0xaf, 0x00, + 0x50, 0x64, 0x21, 0x00, 0x12, 0x40, 0x00, 0x72, 0xa1, 0x0c, 0xc8, 0x00, 0x08, 0x40, 0x30, 0x90, + 0x91, 0x50, 0xa0, 0xb1, 0xb1, 0xf7, 0xff, 0x00, 0x48, 0x40, 0x20, 0xcb, 0x81, 0x00, 0x28, 0x40, + 0xd0, 0x03, 0x03, 0x00, 0x32, 0x40, 0xe0, 0x03, 0x03, 0x06, 0xff, 0xff, +}; + +#define PROG_MULDIV_ENTRY 0x40080000u +static const unsigned char prog_muldiv[36] = { + 0x7c, 0x92, 0x0c, 0x33, 0x30, 0x42, 0x82, 0x30, 0x52, 0xa2, 0x30, 0x62, 0xb2, 0x30, 0x72, 0xd2, + 0x30, 0x82, 0xf2, 0x30, 0x92, 0xc2, 0x30, 0xa2, 0xe2, 0x30, 0xb2, 0xc1, 0x30, 0xc2, 0xd1, 0x0c, + 0x0d, 0x06, 0xff, 0xff, +}; + +#define PROG_LOOPS_ENTRY 0x40080000u +static const unsigned char prog_loops[47] = { + 0x0c, 0x02, 0x32, 0xa0, 0x05, 0x76, 0x83, 0x01, 0x1b, 0x22, 0x0c, 0x04, 0x0c, 0x05, 0x76, 0x95, + 0x01, 0x1b, 0x44, 0x0c, 0x06, 0x0c, 0xa7, 0x0c, 0x08, 0x76, 0x88, 0x06, 0x1b, 0x66, 0x0b, 0x77, + 0x16, 0xf7, 0xff, 0x0c, 0x09, 0x7c, 0xea, 0x76, 0xaa, 0x01, 0x1b, 0x99, 0x06, 0xff, 0xff, +}; + +#define PROG_BRANCHES_ENTRY 0x40080004u +static const unsigned char prog_branches[76] = { + 0x00, 0x00, 0x01, 0x00, 0x22, 0xa0, 0x00, 0x32, 0xa0, 0x80, 0x77, 0x63, 0x02, 0x22, 0xc2, 0x01, + 0x77, 0xe3, 0x02, 0x22, 0xc2, 0x10, 0x41, 0xfa, 0xff, 0xb6, 0x04, 0x01, 0x2b, 0x22, 0xf6, 0x14, + 0x02, 0x22, 0xc2, 0x20, 0x7c, 0xf5, 0x26, 0x05, 0x02, 0x22, 0xc2, 0x40, 0x62, 0xa0, 0xf0, 0x3c, + 0x07, 0x77, 0x46, 0x05, 0x22, 0xd2, 0x01, 0x22, 0xc2, 0x80, 0x77, 0x06, 0x02, 0x22, 0xc2, 0x04, + 0x0c, 0x58, 0x87, 0xd3, 0x02, 0x22, 0xc2, 0x08, 0x06, 0xff, 0xff, 0x00, +}; + +#define PROG_MEMORY_ENTRY 0x4008000Cu +static const unsigned char prog_memory[76] = { + 0x00, 0x00, 0xfb, 0x3f, 0x81, 0x80, 0x00, 0x00, 0x44, 0x33, 0x22, 0x11, 0x06, 0x01, 0x00, 0x00, + 0x0d, 0xf0, 0xfe, 0xca, 0x21, 0xfb, 0xff, 0x31, 0xfb, 0xff, 0x32, 0x52, 0x00, 0x42, 0x92, 0x00, + 0x52, 0x12, 0x00, 0x62, 0x02, 0x01, 0x71, 0xf8, 0xff, 0x79, 0x12, 0x3b, 0xf2, 0x88, 0x0f, 0x5c, + 0x59, 0x90, 0x0c, 0x13, 0x5c, 0x5a, 0xa9, 0x22, 0xb2, 0xa0, 0x66, 0xb2, 0xe2, 0x02, 0xc8, 0x22, + 0xd2, 0xa0, 0x77, 0xd2, 0xe2, 0x02, 0xe1, 0xf2, 0xff, 0x06, 0xff, 0xff, +}; + +#define PROG_WINDOWS_ENTRY 0x40080008u +static const unsigned char prog_windows[56] = { + 0x00, 0x80, 0xfb, 0x3f, 0x00, 0x81, 0xfb, 0x3f, 0x11, 0xfe, 0xff, 0x31, 0xfe, 0xff, 0x42, 0xc1, + 0xf0, 0x39, 0x14, 0x0c, 0xca, 0xa5, 0x00, 0x00, 0xfd, 0x0a, 0x06, 0xff, 0xff, 0x00, 0x00, 0x00, + 0x36, 0x41, 0x00, 0xb6, 0x22, 0x0f, 0xa2, 0xc2, 0xff, 0x65, 0xff, 0xff, 0x3d, 0x0a, 0xa2, 0xc2, + 0xfe, 0xe5, 0xfe, 0xff, 0xaa, 0x23, 0x1d, 0xf0, +}; + +#define PROG_SYSCALL_ENTRY 0x40080004u +static const unsigned char prog_syscall[1808] = { + 0x00, 0x04, 0x08, 0x40, 0x21, 0xff, 0xff, 0x20, 0xe7, 0x13, 0x0c, 0x03, 0x00, 0x50, 0x00, 0x1b, + 0x33, 0x06, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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PROG_FLOAT_ENTRY 0x40080000u +static const unsigned char prog_float[47] = { + 0x0c, 0x12, 0x20, 0xe0, 0x13, 0x10, 0x20, 0x00, 0x0c, 0x33, 0x00, 0x03, 0xca, 0x0c, 0x54, 0x10, + 0x14, 0xca, 0x10, 0x20, 0x0a, 0x10, 0x30, 0x2a, 0x10, 0x20, 0x4a, 0x00, 0x52, 0x9a, 0x00, 0x61, + 0x8a, 0x00, 0x01, 0x4b, 0x0c, 0x07, 0x00, 0x74, 0xd3, 0x40, 0x83, 0xfa, 0x06, 0xff, 0xff, +}; + +#define PROG_MAC16_ENTRY 0x40080008u +static const unsigned char prog_mac16[36] = { + 0x04, 0x00, 0x03, 0x00, 0x05, 0x00, 0xfe, 0xff, 0x21, 0xfe, 0xff, 0x31, 0xfe, 0xff, 0x34, 0x02, + 0x74, 0x34, 0x02, 0x7b, 0x40, 0x10, 0x03, 0x50, 0x11, 0x03, 0x34, 0x02, 0x71, 0x60, 0x10, 0x03, + 0x06, 0xff, 0xff, 0x00, +}; + +#endif diff --git a/tests/unit/test_lx6.c b/tests/unit/test_lx6.c new file mode 100644 index 000000000..79436eb8a --- /dev/null +++ b/tests/unit/test_lx6.c @@ -0,0 +1,351 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* test_lx6.c -- the ESP32's Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) + * on the machine the catalog's ESP32 description builds: programs + * assembled by Espressif's assembler (lx6_programs.h, gen_lx6_programs.py) + * run from IRAM, their results checked against the Xtensa ISA reference + * worked by hand. The window spills and fills of the recursive program go + * through the ESP32 ROM's own window vectors. */ +#include "harness.h" +#include "lx6_programs.h" +#include "mcu/build.h" +#include "mcu/xtensa/lx6.h" +#include "util/json.h" + +#define IRAM 0x40080000u +#define GR_PC 0 +#define GR_WB 69 +#define GR_WS 70 +#define GR_PS 73 +#define GR_A 105 +#define J_SELF 0xffff06u + +typedef struct t32 { + esk_alloc a; + esk_json *mcu, *regs; + struct esk_mach m; +} t32; + +static unsigned char *slurp(const char *rel, size_t *len) +{ + char path[1024]; + FILE *f; + unsigned char *buf; + long n; + snprintf(path, sizeof path, "%s/%s", EMBSIM_SOURCE_DIR, rel); + f = fopen(path, "rb"); + if (!f) + return NULL; + fseek(f, 0, SEEK_END); + n = ftell(f); + fseek(f, 0, SEEK_SET); + buf = (unsigned char *)malloc(n > 0 ? (size_t)n : 1); + if (buf && fread(buf, 1, (size_t)n, f) != (size_t)n) { + free(buf); + buf = NULL; + } + fclose(f); + *len = (size_t)n; + return buf; +} + +static esk_json *load_json(esk_alloc *a, const char *rel) +{ + size_t len = 0; + unsigned char *text = slurp(rel, &len); + esk_json *j; + int line = 0; + const char *err = NULL; + if (!text) + return NULL; + j = esk_json_parse(a, (const char *)text, len, &line, &err); + free(text); + return j; +} + +static void put32(u8 *b, u32 v) +{ + b[0] = (u8)v; + b[1] = (u8)(v >> 8); + b[2] = (u8)(v >> 16); + b[3] = (u8)(v >> 24); +} + +static u32 reg(t32 *t, int n) +{ + u8 b[8] = { 0 }; + t->m.cpu->ops->reg_read(t->m.cpu, n, b); + return (u32)b[0] | (u32)b[1] << 8 | (u32)b[2] << 16 | (u32)b[3] << 24; +} + +static void set_reg(t32 *t, int n, u32 v) +{ + u8 b[4]; + put32(b, v); + CHECK_EQ(t->m.cpu->ops->reg_write(t->m.cpu, n, b), 4); +} + +static u32 a(t32 *t, int n) { return reg(t, GR_A + n); } + +/* the ESP32 out of reset, `prog` in IRAM, the PRO_CPU at `entry` with + * windowed calls on (PS.WOE), interrupts open, a stack in DRAM */ +static int open32(t32 *t, const unsigned char *prog, size_t n, u32 entry) +{ + char why[200]; + es_status st; + size_t i; + memset(t, 0, sizeof *t); + esk_alloc_init(&t->a, NULL); + t->mcu = load_json(&t->a, "catalog/mcus/espressif/esp32/mcu.json"); + t->regs = load_json(&t->a, "catalog/mcus/espressif/esp32/registers.json"); + CHECK(t->mcu != NULL && t->regs != NULL); + if (!t->mcu || !t->regs) + return 0; + esk_mach_init(&t->m, &t->a); + st = esk_mach_build(&t->m, t->mcu, t->regs, 40000000u, why, sizeof why); + if (st != ES_OK) { + FAIL(why); + return 0; + } + { + size_t rlen = 0; + unsigned char *rom = slurp("catalog/mcus/espressif/esp32/rom.bin", &rlen); + CHECK(rom != NULL); + if (!rom) + return 0; + CHECK_EQ(esk_mach_factory(&t->m, 0x40000000u, rom, rlen), ES_OK); + free(rom); + } + esk_mach_reset(&t->m); + CHECK(esk_lx6_is(t->m.cpu)); + CHECK_STR(t->m.cpu->ops->name, "xtensa"); + CHECK_EQ(esk_lx6_cores(&t->m), 2); + CHECK_EQ(reg(t, GR_PC), 0x40000400u); /* the reset vector */ + for (i = 0; i < n; i++) + CHECK_EQ(esk_bus_debug_write(&t->m.bus, IRAM + (u32)i, 1, prog[i]), 0); + set_reg(t, GR_PC, entry); + set_reg(t, GR_PS, 0x00040000u); /* WOE, INTLEVEL 0 */ + set_reg(t, GR_WB, 0); + set_reg(t, GR_WS, 1); + set_reg(t, GR_A + 1, 0x3FFB8000u); + return 1; +} + +static void close32(t32 *t) +{ + esk_mach_free(&t->m); + esk_json_free(&t->a, t->mcu); + esk_json_free(&t->a, t->regs); + CHECK_EQ(t->a.live_bytes, 0); +} + +/* runs until the program's final `j .`: 1 when it got there */ +static int run_to_end(t32 *t, u64 max_insns) +{ + u32 w = 0; + esk_mach_run(&t->m, 0xffffffffu, max_insns); + if (esk_bus_debug_read(&t->m.bus, reg(t, GR_PC), 4, &w)) + return 0; + return (w & 0xffffffu) == J_SELF; +} + +#define OPEN(t, name, NAME) open32(&(t), prog_##name, sizeof prog_##name, PROG_##NAME##_ENTRY) + +static void test_alu(void) +{ + t32 t; + if (!OPEN(t, alu, ALU)) + return; + CHECK(run_to_end(&t, 100)); + CHECK_EQ(a(&t, 4), 4u); + CHECK_EQ(a(&t, 5), 25u); + CHECK_EQ(a(&t, 6), 59u); + CHECK_EQ(a(&t, 7), 3u); + CHECK_EQ(a(&t, 8), 3u); + CHECK_EQ(a(&t, 9), (u32)-3); + CHECK_EQ(a(&t, 10), 0xfffffffdu); + CHECK_EQ(a(&t, 11), (u32)-3); + CHECK_EQ(a(&t, 12), 127u); + CHECK_EQ(a(&t, 13), 29u); + CHECK_EQ(a(&t, 14), 29u); + CHECK_EQ(a(&t, 15), 0xffu); + close32(&t); +} + +static void test_shifts(void) +{ + t32 t; + if (!OPEN(t, shifts, SHIFTS)) + return; + CHECK(run_to_end(&t, 100)); + CHECK_EQ(a(&t, 3), 0x12300000u); + CHECK_EQ(a(&t, 4), 0x00123000u); + CHECK_EQ(a(&t, 6), (u32)-16); + CHECK_EQ(a(&t, 7), 0x918u); + CHECK_EQ(a(&t, 9), 0x12300u); + CHECK_EQ(a(&t, 10), 0xffffffffu); + CHECK_EQ(a(&t, 12), 0x21000001u); + CHECK_EQ(a(&t, 13), 0u); + CHECK_EQ(a(&t, 14), 8u); + close32(&t); +} + +static void test_muldiv(void) +{ + t32 t; + if (!OPEN(t, muldiv, MULDIV)) + return; + CHECK(run_to_end(&t, 100)); + CHECK_EQ(a(&t, 4), (u32)-21); + CHECK_EQ(a(&t, 5), 2u); + CHECK_EQ(a(&t, 6), 0xffffffffu); + CHECK_EQ(a(&t, 7), (u32)-2); + CHECK_EQ(a(&t, 8), (u32)-1); + CHECK_EQ(a(&t, 9), 0x55555553u); + CHECK_EQ(a(&t, 10), 0u); + CHECK_EQ(a(&t, 11), 0x2ffebu); + CHECK_EQ(a(&t, 12), (u32)-21); + close32(&t); +} + +/* the zero-overhead loops, one left by a branch taken to its end */ +static void test_loops(void) +{ + t32 t; + if (!OPEN(t, loops, LOOPS)) + return; + CHECK(run_to_end(&t, 200)); + CHECK_EQ(a(&t, 2), 5u); + CHECK_EQ(a(&t, 4), 0u); /* LOOPNEZ of 0: skipped */ + CHECK_EQ(a(&t, 6), 10u); /* left by BEQZ to LEND, not looped again */ + CHECK_EQ(a(&t, 7), 0u); + CHECK_EQ(a(&t, 9), 0u); /* LOOPGTZ of -2: skipped */ + close32(&t); +} + +static void test_branches(void) +{ + t32 t; + if (!OPEN(t, branches, BRANCHES)) + return; + CHECK(run_to_end(&t, 100)); + CHECK_EQ(a(&t, 2), 15u); + close32(&t); +} + +static void test_memory(void) +{ + t32 t; + if (!OPEN(t, memory, MEMORY)) + return; + CHECK(run_to_end(&t, 100)); + CHECK_EQ(a(&t, 4), 0xffff8081u); + CHECK_EQ(a(&t, 5), 0x8081u); + CHECK_EQ(a(&t, 6), 0x80u); + CHECK_EQ(a(&t, 8), 0x22334400u); + CHECK_EQ(a(&t, 11), 0x55u); /* S32C1I stored, and returned the old word */ + CHECK_EQ(a(&t, 12), 0x66u); + CHECK_EQ(a(&t, 13), 0x66u); /* compare failed: nothing stored */ + CHECK_EQ(a(&t, 14), 0xcafef00du); + close32(&t); +} + +/* fib(12) by CALL8/ENTRY/RETW: twelve frames deep, spilled and filled by + * the ROM's WindowOverflow8 and WindowUnderflow8 */ +static void test_windows(void) +{ + t32 t; + if (!OPEN(t, windows, WINDOWS)) + return; + CHECK(run_to_end(&t, 200000)); + CHECK_EQ(a(&t, 15), 144u); + CHECK_EQ(reg(&t, GR_WB), 0u); + close32(&t); +} + +static void test_syscall(void) +{ + t32 t; + if (!OPEN(t, syscall, SYSCALL)) + return; + CHECK(run_to_end(&t, 100)); + CHECK_EQ(a(&t, 4), 1u); /* EXCCAUSE: SyscallCause */ + CHECK_EQ(a(&t, 3), 1u); /* back after it */ + CHECK_EQ(reg(&t, GR_PS) & 0x10u, 0u); /* RFE cleared EXCM */ + close32(&t); +} + +static void test_timer(void) +{ + t32 t; + if (!OPEN(t, timer, TIMER)) + return; + CHECK(run_to_end(&t, 2000)); + CHECK_EQ(a(&t, 6), 1u); + CHECK_EQ(a(&t, 7), 4u); /* Level1InterruptCause */ + CHECK_EQ(a(&t, 8) & 0x40u, 0x40u); /* INTERRUPT: timer 0 */ + close32(&t); +} + +static void test_float(void) +{ + t32 t; + if (!OPEN(t, float, FLOAT)) + return; + CHECK(run_to_end(&t, 100)); + CHECK_EQ(a(&t, 5), 13u); + CHECK_EQ(a(&t, 6), 2u); + CHECK_EQ(a(&t, 7), 5u); + CHECK_EQ(a(&t, 8), 0x40f00000u); + close32(&t); +} + +static void test_mac16(void) +{ + t32 t; + if (!OPEN(t, mac16, MAC16)) + return; + CHECK(run_to_end(&t, 100)); + CHECK_EQ(a(&t, 4), 14u); + CHECK_EQ(a(&t, 5), 0u); + CHECK_EQ(a(&t, 6), 15u); + close32(&t); +} + +/* the APP_CPU's ROM keeps its own data: released, it runs the ROM's start, + * which sets g_ticks_per_us_app (0x3FFE40F0) and leaves the PRO_CPU's + * g_ticks_per_us_pro (0x3FFE01E0) as the PRO_CPU set it */ +static void test_app_cpu_rom_data(void) +{ + static const unsigned char spin[3] = { 0x06, 0xff, 0xff }; /* j . */ + t32 t; + u32 pro = 0, app = 0; + if (!open32(&t, spin, sizeof spin, IRAM)) + return; + CHECK_EQ(esk_bus_debug_write(&t.m.bus, 0x3FFE01E0u, 4, 80u), 0); + CHECK_EQ(esk_bus_debug_write(&t.m.bus, 0x3FFE40F0u, 4, 0xdeadbeefu), 0); + /* DPORT: the APP_CPU's clock on, out of reset (APPCPU_CTRL_B, _A) */ + CHECK_EQ(esk_bus_write(&t.m.bus, 0x3FF00030u, 4, 1u), 0); + CHECK_EQ(esk_bus_write(&t.m.bus, 0x3FF0002Cu, 4, 0u), 0); + esk_mach_run(&t.m, 0xffffffffu, 20000); + CHECK_EQ(esk_bus_debug_read(&t.m.bus, 0x3FFE01E0u, 4, &pro), 0); + CHECK_EQ(esk_bus_debug_read(&t.m.bus, 0x3FFE40F0u, 4, &app), 0); + CHECK_EQ(pro, 80u); + CHECK_EQ(app, 13u); /* the ROM's initial value, unpacked by the APP_CPU */ + close32(&t); +} + +TEST_MAIN_BEGIN +RUN(test_alu); +RUN(test_shifts); +RUN(test_muldiv); +RUN(test_loops); +RUN(test_branches); +RUN(test_memory); +RUN(test_windows); +RUN(test_syscall); +RUN(test_timer); +RUN(test_float); +RUN(test_mac16); +RUN(test_app_cpu_rom_data); +TEST_MAIN_END diff --git a/tests/vendor/esp-idf/examples/esp32_hello_world/project.json b/tests/vendor/esp-idf/examples/esp32_hello_world/project.json new file mode 100644 index 000000000..b223b1942 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_hello_world/project.json @@ -0,0 +1,61 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "esp-idf-esp32_hello_world", + "description": "An ESP32-DevKitC V4 running ESP-IDF's hello_world, built unmodified by ESP-IDF's tools for the esp32 target (tests/vendor/esp-idf/run.py puts its 4 MB flash image beside this file as flash.bin), plugged into USB. The console is UART0 through the CP2102N.", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + } + ], + "nets": { + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1" + ], + "USB5V": [ + "USB.+", + "B1.VBUS" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_hello_world/scenario.json b/tests/vendor/esp-idf/examples/esp32_hello_world/scenario.json new file mode 100644 index 000000000..4ae1bd0b2 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_hello_world/scenario.json @@ -0,0 +1,82 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "esp32_hello_world", + "until": "11600ms", + "description": "hello_world on the ESP32: Espressif's ROM (ECO3, its banner and boot mode), ESP-IDF's second-stage bootloader (chip revision v3.1 from the eFuses, the image's SHA-256 on the SHA accelerator), the application on both cores at 160 MHz, its chip report, a countdown of eleven one-second FreeRTOS delays, and esp_restart back to the ROM with a software CPU reset of the PRO_CPU.", + "inputs": [], + "assertions": [ + { + "id": "rom", + "at": "100ms", + "probe": "console", + "expect": { + "contains": "rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)" + } + }, + { + "id": "banner", + "at": "100ms", + "probe": "console", + "expect": { + "contains": "ets Jul 29 2019 12:21:46" + } + }, + { + "id": "revision", + "at": "300ms", + "probe": "console", + "expect": { + "contains": "boot: chip revision: v3.1" + } + }, + { + "id": "app", + "at": "500ms", + "probe": "console", + "expect": { + "contains": "cpu_start: Multicore app" + } + }, + { + "id": "freq", + "at": "500ms", + "probe": "console", + "expect": { + "contains": "cpu freq: 160000000 Hz" + } + }, + { + "id": "hello", + "at": "1s", + "probe": "console", + "expect": { + "contains": "Hello world!" + } + }, + { + "id": "chip", + "at": "1s", + "probe": "console", + "expect": { + "contains": "This is esp32 chip with 2 CPU core(s), WiFi/BTBLE, silicon revision v3.1" + } + }, + { + "id": "not-yet", + "at": "11200ms", + "probe": "console", + "expect": { + "not_contains": "Restarting now." + } + }, + { + "id": "restart", + "at": "11600ms", + "probe": "console", + "expect": { + "contains": "rst:0xc (SW_CPU_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)" + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/run.py b/tests/vendor/esp-idf/run.py index 46f36f9a9..843c2291f 100644 --- a/tests/vendor/esp-idf/run.py +++ b/tests/vendor/esp-idf/run.py @@ -3,11 +3,12 @@ # Copyright 2026 Junior Deogracias """ESP-IDF's own examples for the ESP32-C3, built unmodified by ESP-IDF's build system and run on EmbSIM's ESP32-C3-DevKitM-1 (the RTOS boards plan, -part 2, step 7; 01 §8.2). +part 2, step 7; 01 §8.2), and for the ESP32 on the ESP32-DevKitC V4 (the +examples TARGETS names, built for that target). ESP-IDF is not vendored. --idf names an ESP-IDF checkout (v5.4) whose tools are installed, or IDF_PATH does; the riscv32-esp-elf toolchain must be on -PATH and ESP-IDF's Python environment the one running `idf.py` (its +PATH (xtensa-esp32-elf for the ESP32's) and ESP-IDF's Python environment the one running `idf.py` (its export.sh sets both up). An example's managed components (blink's led_strip) come from Espressif's component registry, as `idf.py` fetches them. @@ -70,7 +71,14 @@ "wifi_softap": "examples/wifi/getting_started/softAP", "wifi_station": "examples/wifi/getting_started/station", "wifi_station_open": "examples/wifi/getting_started/station", + "esp32_hello_world": "examples/get-started/hello_world", } +# the target an example is built for, when not the ESP32-C3 (its board in +# examples//project.json), and the toolchain that target needs +TARGETS = { + "esp32_hello_world": "esp32", +} +TOOLCHAINS = {"esp32c3": "riscv32-esp-elf-gcc", "esp32": "xtensa-esp32-elf-gcc"} # examples built only for another's project (with examples//'s # sdkconfig.defaults), not run on their own VARIANTS = { @@ -100,7 +108,7 @@ def build(idf: Path, name: str, out: Path) -> Path: cmd = [sys.executable, idf / "tools" / "idf.py", "-C", proj, "-B", proj / "build"] if defaults: cmd += ["-D", "SDKCONFIG_DEFAULTS=" + ";".join(str(d) for d in defaults)] - sh(cmd + ["set-target", "esp32c3"], env=env) + sh(cmd + ["set-target", TARGETS.get(name, "esp32c3")], env=env) sh(cmd + ["build"], env=env) args = json.loads((proj / "build" / "flasher_args.json").read_text(encoding="utf-8")) image = bytearray(b"\xff" * FLASH_SIZE) @@ -120,11 +128,16 @@ def main() -> int: ap.add_argument("--keep", help="build here, and keep it, instead of a temporary directory") ap.add_argument("examples", nargs="*") args = ap.parse_args() - if not args.idf or not shutil.which("riscv32-esp-elf-gcc"): - print("skip: ESP-IDF (--idf or IDF_PATH) and its riscv32-esp-elf toolchain are needed") + if not args.idf: + print("skip: ESP-IDF (--idf or IDF_PATH) and its toolchains are needed") return 0 idf = Path(args.idf).resolve() names = args.examples or sorted(EXAMPLES) + missing = sorted({TOOLCHAINS[TARGETS.get(n, "esp32c3")] for n in names} - {t for t in TOOLCHAINS.values() + if shutil.which(t)}) + if missing: + print(f"skip: the toolchain(s) {', '.join(missing)} are needed") + return 0 unknown = [n for n in names if n not in EXAMPLES] if unknown: raise SystemExit(f"unknown example(s): {', '.join(unknown)}") From 32d72597ad8cab2cbed668f55f6518decac72846 Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 03:39:27 +0000 Subject: [PATCH 03/16] ESP-IDF vendor suite: blink on the ESP32-DevKitC V4 The GPIO LED on GPIO2 (sdkconfig.defaults), an LED and 330 ohm on IO2: gpio_set_level through the matrix every second, 6/6. --- .../esp-idf/examples/esp32_blink/project.json | 102 ++++++++++++++++++ .../examples/esp32_blink/scenario.json | 58 ++++++++++ .../examples/esp32_blink/sdkconfig.defaults | 2 + tests/vendor/esp-idf/run.py | 2 + 4 files changed, 164 insertions(+) create mode 100644 tests/vendor/esp-idf/examples/esp32_blink/project.json create mode 100644 tests/vendor/esp-idf/examples/esp32_blink/scenario.json create mode 100644 tests/vendor/esp-idf/examples/esp32_blink/sdkconfig.defaults diff --git a/tests/vendor/esp-idf/examples/esp32_blink/project.json b/tests/vendor/esp-idf/examples/esp32_blink/project.json new file mode 100644 index 000000000..0ba8734e5 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_blink/project.json @@ -0,0 +1,102 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "esp-idf-esp32_blink", + "description": "ESP-IDF's blink on the ESP32-DevKitC V4 with an LED on IO2 through 330 ohm (the DevKitC has no LED of its own; sdkconfig.defaults chooses the GPIO LED on GPIO2).", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + }, + { + "id": "R1", + "component": "emblink/resistor", + "params": { + "resistance": "330" + }, + "layout": { + "x": 600, + "y": 160 + } + }, + { + "id": "LED1", + "component": "emblink/led", + "params": { + "color": "red" + }, + "layout": { + "x": 680, + "y": 160 + } + } + ], + "nets": { + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1", + "LED1.K" + ], + "USB5V": [ + "USB.+", + "B1.VBUS" + ], + "IO2": [ + "B1.IO2", + "R1.1" + ], + "LA": [ + "R1.2", + "LED1.A" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + }, + { + "id": "io2", + "target": "net:IO2", + "kind": "digital" + }, + { + "id": "led", + "target": "output:LED1.luminance", + "kind": "value" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_blink/scenario.json b/tests/vendor/esp-idf/examples/esp32_blink/scenario.json new file mode 100644 index 000000000..636b319a9 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_blink/scenario.json @@ -0,0 +1,58 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "esp32_blink", + "until": "3900ms", + "description": "blink on the ESP32, the GPIO LED on GPIO2 (sdkconfig.defaults): gpio_set_level through the GPIO matrix every second, the console saying each; the LED off first, then on, off, on.", + "inputs": [], + "assertions": [ + { + "id": "gpio", + "at": "1s", + "probe": "console", + "expect": { + "contains": "Example configured to blink GPIO LED!" + } + }, + { + "id": "on", + "at": "1800ms", + "probe": "io2", + "expect": { + "equals": 1 + } + }, + { + "id": "lit", + "at": "1800ms", + "probe": "led", + "expect": { + "min": 0.1 + } + }, + { + "id": "off", + "at": "2800ms", + "probe": "io2", + "expect": { + "equals": 0 + } + }, + { + "id": "on-again", + "at": "3800ms", + "probe": "io2", + "expect": { + "equals": 1 + } + }, + { + "id": "said", + "at": "3800ms", + "probe": "console", + "expect": { + "contains": "Turning the LED ON!" + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_blink/sdkconfig.defaults b/tests/vendor/esp-idf/examples/esp32_blink/sdkconfig.defaults new file mode 100644 index 000000000..fdea10c5d --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_blink/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_BLINK_LED_GPIO=y +CONFIG_BLINK_GPIO=2 diff --git a/tests/vendor/esp-idf/run.py b/tests/vendor/esp-idf/run.py index 843c2291f..fe8b0bb8f 100644 --- a/tests/vendor/esp-idf/run.py +++ b/tests/vendor/esp-idf/run.py @@ -72,11 +72,13 @@ "wifi_station": "examples/wifi/getting_started/station", "wifi_station_open": "examples/wifi/getting_started/station", "esp32_hello_world": "examples/get-started/hello_world", + "esp32_blink": "examples/get-started/blink", } # the target an example is built for, when not the ESP32-C3 (its board in # examples//project.json), and the toolchain that target needs TARGETS = { "esp32_hello_world": "esp32", + "esp32_blink": "esp32", } TOOLCHAINS = {"esp32c3": "riscv32-esp-elf-gcc", "esp32": "xtensa-esp32-elf-gcc"} # examples built only for another's project (with examples//'s From 055a9f01ea26fbbacada242392267dbe24e07555 Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 03:40:01 +0000 Subject: [PATCH 04/16] CI: the ESP-IDF job installs the ESP32's toolchain too run.py skips an example whose toolchain is missing rather than every example, and CI installs xtensa-esp32-elf with riscv32-esp-elf so the esp32_* examples run on the ESP32-DevKitC. --- .github/workflows/ci.yml | 9 +++++---- tests/vendor/esp-idf/run.py | 7 +++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 060c4e594..673a04a5b 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -160,8 +160,9 @@ jobs: python3 tests/vendor/freedom-metal/run.py --sdk "$RUNNER_TEMP/freedom-e-sdk" --metal "$RUNNER_TEMP/freedom-metal" --embsim build/${{ matrix.preset }}/bin/embsim esp-idf: - # its own job: ESP-IDF and its RISC-V toolchain take a while to fetch, - # and each example is built with idf.py as a user builds it + # its own job: ESP-IDF and its RISC-V and Xtensa toolchains take a while + # to fetch, and each example is built with idf.py as a user builds it + # (the ESP32-C3-DevKitM-1's, and the ESP32-DevKitC's esp32_* ones) name: ESP-IDF's examples on the ESP32-C3-DevKitM-1 runs-on: ubuntu-24.04 steps: @@ -174,7 +175,7 @@ jobs: run: | cmake --preset ci-gcc cmake --build --preset ci-gcc - - name: ESP-IDF v5.4 and its tools for the ESP32-C3 + - name: ESP-IDF v5.4 and its tools for the ESP32-C3 and the ESP32 run: | # an origin remote: ESP-IDF's submodules are relative to it (../../espressif/...) git init -q "$RUNNER_TEMP/esp-idf" @@ -182,7 +183,7 @@ jobs: git -C "$RUNNER_TEMP/esp-idf" fetch -q --depth 1 origin 67c1de1eebe095d554d281952fde63c16ee2dca0 # v5.4 git -C "$RUNNER_TEMP/esp-idf" checkout -q FETCH_HEAD git -C "$RUNNER_TEMP/esp-idf" submodule update -q --init --depth 1 --recursive - "$RUNNER_TEMP/esp-idf/install.sh" esp32c3 + "$RUNNER_TEMP/esp-idf/install.sh" esp32c3,esp32 - name: Run the examples run: | . "$RUNNER_TEMP/esp-idf/export.sh" >/dev/null diff --git a/tests/vendor/esp-idf/run.py b/tests/vendor/esp-idf/run.py index fe8b0bb8f..5e552a009 100644 --- a/tests/vendor/esp-idf/run.py +++ b/tests/vendor/esp-idf/run.py @@ -135,10 +135,9 @@ def main() -> int: return 0 idf = Path(args.idf).resolve() names = args.examples or sorted(EXAMPLES) - missing = sorted({TOOLCHAINS[TARGETS.get(n, "esp32c3")] for n in names} - {t for t in TOOLCHAINS.values() - if shutil.which(t)}) - if missing: - print(f"skip: the toolchain(s) {', '.join(missing)} are needed") + names = [n for n in names if n not in EXAMPLES or shutil.which(TOOLCHAINS[TARGETS.get(n, "esp32c3")]) + or print(f"skip: {n} needs {TOOLCHAINS[TARGETS.get(n, 'esp32c3')]}")] + if not names: return 0 unknown = [n for n in names if n not in EXAMPLES] if unknown: From 3749b91925c2f2298c8fd452e54e90b9ca44296f Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 03:43:12 +0000 Subject: [PATCH 05/16] ESP32: LEDC, with ESP-IDF's ledc_basic Eight high-speed and eight low-speed channels on four timers each (core/mcu/esp32/soc/ledc.c, the ESP32-C3's model on the ESP32's registers): REF_TICK, APB_CLK or SLOW_CLK over the 10.8 divider, up to 20 bits of duty, high-speed settings at the next overflow and low-speed ones after PARA_UP, fading, the overflow and fade interrupts, the matrix's ledc_hs/ls_sig_out. ledc_basic's 4 kHz on GPIO5: 2/2. --- CHANGELOG.md | 6 +- catalog/mcus/espressif/esp32/mcu.json | 10 +- core/mcu/esp32/soc/esp32.h | 3 + core/mcu/esp32/soc/ledc.c | 500 ++++++++++++++++++ core/mcu/models.c | 1 + docs/STATUS.md | 5 +- docs/coverage.md | 8 +- .../examples/esp32_ledc_basic/project.json | 66 +++ .../examples/esp32_ledc_basic/scenario.json | 33 ++ tests/vendor/esp-idf/run.py | 2 + 10 files changed, 622 insertions(+), 12 deletions(-) create mode 100644 core/mcu/esp32/soc/ledc.c create mode 100644 tests/vendor/esp-idf/examples/esp32_ledc_basic/project.json create mode 100644 tests/vendor/esp-idf/examples/esp32_ledc_basic/scenario.json diff --git a/CHANGELOG.md b/CHANGELOG.md index f7b911d9e..bd9526d0a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -19,13 +19,13 @@ versions follow semantic versioning. There is no release yet. copy-table entry; the image equals QEMU's esp32-v3-rom.bin), the register file from esp32.svd, and models for DPORT (APP_CPU, caches and flash MMU, interrupt matrix), RTC_CNTL, eFuse, APB_CTRL clocks, GPIO/IO_MUX with - strapping, UART0-2, TIMG0/1, SPI0/1 with the GT25Q32A flash, SHA, the + strapping, UART0-2, TIMG0/1, SPI0/1 with the GT25Q32A flash, SHA, LEDC, the internal analog I2C, RNG and the AHB view. - Added the `emblink/esp32_devkitc` board (ESP32-DevKitC V4, WROOM-32E) with its power path, LED, Boot and EN buttons, headers and fixtures. - Espressif's ROM, ESP-IDF v5.4's bootloader and hello_world run unmodified - through `esp_restart` (`tests/vendor/esp-idf`, example `esp32_hello_world`, - 9/9); `test_lx6` checks the core with programs from Espressif's assembler. + through `esp_restart` (`tests/vendor/esp-idf`: `esp32_hello_world` 9/9, + `esp32_blink` 6/6, `esp32_ledc_basic` 2/2); `test_lx6` checks the core with programs from Espressif's assembler. ### Original ESP32 digital per-pin hold diff --git a/catalog/mcus/espressif/esp32/mcu.json b/catalog/mcus/espressif/esp32/mcu.json index 6bedac0a6..abcc6854c 100644 --- a/catalog/mcus/espressif/esp32/mcu.json +++ b/catalog/mcus/espressif/esp32/mcu.json @@ -191,6 +191,10 @@ { "match": "SHA", "model": "esp32-sha" + }, + { + "match": "LEDC", + "model": "esp32-ledc" } ], "io": { @@ -221,18 +225,18 @@ }, "fidelity": { "functional": { - "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), the internal analog I2C master, the random number generator and the peripherals' AHB view.", + "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), the internal analog I2C master, the random number generator and the peripherals' AHB view.", "omissions": [ "Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written)", "the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept", "PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts", - "the peripherals without a model yet: I2C0/1, I2S0/1, SPI2/3 (HSPI, VSPI), RMT, LEDC, MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption", + "the peripherals without a model yet: I2C0/1, I2S0/1, SPI2/3 (HSPI, VSPI), RMT, MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption", "sleep modes (light and deep sleep, the power domains), brown-out", "the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection" ], "validation": [ "tests/unit/test_lx6.c: programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16), and the APP_CPU's ROM data kept apart", - "tests/vendor/esp-idf: ESP-IDF v5.4's hello_world built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart", + "tests/vendor/esp-idf: ESP-IDF v5.4's hello_world, blink and ledc_basic built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart", "the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin" ] }, diff --git a/core/mcu/esp32/soc/esp32.h b/core/mcu/esp32/soc/esp32.h index 65cb9db5e..16b4c970c 100644 --- a/core/mcu/esp32/soc/esp32.h +++ b/core/mcu/esp32/soc/esp32.h @@ -16,6 +16,7 @@ * spi.c SPI0 and SPI1 in front of the flash, and the flash itself * apbctrl.c APB_CTRL: the CPU's and APB's clock dividers * sha.c the SHA accelerator + * ledc.c the LED PWM controller * misc.c the random number generator, the AHB view of the * peripherals */ #ifndef ESK_MCU_ESP32_SOC_H @@ -49,6 +50,8 @@ extern const struct esk_dev_ops esk_esp32_spi_ops; void *esk_esp32_spi_create(struct esk_mach *s, struct esk_rf_periph *p); extern const struct esk_dev_ops esk_esp32_apbctrl_ops; void *esk_esp32_apbctrl_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_ledc_ops; +void *esk_esp32_ledc_create(struct esk_mach *s, struct esk_rf_periph *p); extern const struct esk_dev_ops esk_esp32_sha_ops; void *esk_esp32_sha_create(struct esk_mach *s, struct esk_rf_periph *p); /* the RNG and the AHB view of the peripherals (misc.c): 0, or -1 */ diff --git a/core/mcu/esp32/soc/ledc.c b/core/mcu/esp32/soc/ledc.c new file mode 100644 index 000000000..576e4c938 --- /dev/null +++ b/core/mcu/esp32/soc/ledc.c @@ -0,0 +1,500 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* ledc.c -- the ESP32's LED PWM controller (LEDC, TRM v5 chapter 14): + * eight high-speed and eight low-speed channels on four timers each, + * ledc_hs_sig_out0-7 and ledc_ls_sig_out0-7 (signals 71-86 of the GPIO + * matrix). The ESP32-C3's model (mcu/esp32c3/ledc.c) on the ESP32's + * registers. + * + * - A timer counts its clock -- REF_TICK (1 MHz) with TICK_SEL 0; with + * TICK_SEL 1 APB_CLK for the high-speed timers, SLOW_CLK (APB_CLK with + * CONF's APB_CLK_SEL, else the 8 MHz RC_FAST_CLK) for the low-speed ones + * -- divided by DIV_NUM / 256 (10 integer and 8 fractional bits), from + * 0 to 2^DUTY_RES - 1 (up to 20 bits), then overflows; RST holds it at + * 0, PAUSE stops it. A high-speed timer's new DIV_NUM and DUTY_RES + * take effect at its next overflow, a low-speed one's at the overflow + * after PARA_UP. + * - A channel (TIMER_SEL's timer of its group) goes high at its HPOINT + * count and low at HPOINT + DUTY[24:4]; DUTY[3:0] of every 16 periods + * last one count longer; with SIG_OUT_EN 0 it outputs IDLE_LV. Its + * settings take effect at the timer's overflow after DUTY_START (a + * high-speed channel) or the PARA_UP that follows it (a low-speed one). + * - Fading: from DUTY, every DUTY_CYCLE overflows the duty steps + * DUTY_SCALE up (DUTY_INC) or down, DUTY_NUM times, then + * DUTY_CHNG_END. DUTY_R is the duty in use. + * - INT_ST is INT_RAW and INT_ENA (the timers' overflows, bits 0-7; the + * channels' fade ends, 8-23), raising matrix source 43; INT_CLR clears. + * Where it differs inside: a fractional divider's counts are all of the + * average length; the dithered periods are spread by an accumulator. + * Not yet: light sleep, the clock gate's effect on a running timer. */ +#include +#include + +#include "mcu/esp32/soc/esp32.h" + +#define NCH 16 /* HSCH0-7, LSCH0-7 */ +#define NTM 8 /* HSTIMER0-3, LSTIMER0-3 */ +#define SIG_OUT0 71 /* ledc_hs_sig_out0; ledc_ls_sig_out0 is 79 */ +#define RC_FAST_HZ 8000000u +#define REF_TICK_HZ 1000000u +#define FS_PER_S 1000000000000000ull + +#define T_PAUSE (1u << 23) +#define T_RST (1u << 24) +#define T_TICK_SEL (1u << 25) +#define T_PARA_UP (1u << 26) +#define C_SIG_OUT_EN (1u << 2) +#define C_IDLE_LV (1u << 3) +#define C_PARA_UP (1u << 4) +#define F_INC (1u << 30) +#define F_START (1u << 31) + +struct tmr { + struct esk_rf_reg *conf, *value; + u32 res, div; /* in use: DUTY_RES, CLK_DIV */ + int update; /* PARA_UP: the new ones at the next overflow */ + u32 cnt; /* the count */ + u64 pos; /* fs into the period */ +}; + +struct chan { + struct esk_rf_reg *conf0, *hpoint, *duty, *conf1, *duty_r; + int update; /* PARA_UP: the new settings at the next overflow */ + u32 sel, hp, en, idle; /* in use */ + u32 duty_cur; /* the duty (19 bits, 4 of them fractions) */ + u32 lp; /* this period's low point */ + u32 dither; /* the fractions' accumulator */ + int fading; + u32 cyc, steps, ovf; + int out; +}; + +struct e32_ledc { + struct esk_mach *s; + struct esk_rf_periph *p; + struct esk_rf_reg *conf, *raw, *st, *ena; + struct tmr t[NTM]; + struct chan c[NCH]; + int clocked, level, source; +}; + +static u32 reg(const struct esk_rf_reg *r) { return (u32)r->value; } + +static void update(struct e32_ledc *k) +{ + u32 st = reg(k->raw) & reg(k->ena) & 0xffffffu; + int level = st != 0; + esk_rf_hw(k->st, st); + if (level != k->level) { + k->level = level; + esk_esp32_source(k->s, k->source, level); + } +} + +static void raise(struct e32_ledc *k, u32 bits) +{ + esk_rf_hw(k->raw, reg(k->raw) | bits); + update(k); +} + +/* a count's length in fs, or 0 while the timer does not count */ +static double tick_fs(const struct e32_ledc *k, const struct tmr *t) +{ + u32 hz, c = reg(t->conf), x = (u32)(t - k->t); + if ((c & (T_RST | T_PAUSE)) || t->div < 256u) + return 0; + if (!(c & T_TICK_SEL)) + hz = REF_TICK_HZ; + else if (x < 4u || (reg(k->conf) & 1u)) + hz = esk_esp32_apb_hz(k->s); /* high speed: APB_CLK; low speed: SLOW_CLK */ + else + hz = RC_FAST_HZ; + if (!hz) + return 0; + return (double)t->div / 256.0 * (double)FS_PER_S / (double)hz; +} + +static u32 top(const struct tmr *t) { return (1u << (t->res > 20u ? 20u : t->res)) - 1u; } + +static u64 fs_per_cycle(const struct e32_ledc *k) +{ + u32 hz = esk_mach_core_hz(k->s); + return hz ? FS_PER_S / hz : 0; +} + +static void drive(struct e32_ledc *k, int n, int out) +{ + struct chan *c = &k->c[n]; + if (out != c->out) { + c->out = out; + esk_esp32_signal(k->s, SIG_OUT0 + n, out, 1); + } +} + +/* the channel's settings as written, in use from now */ +static void chan_apply(struct e32_ledc *k, int n) +{ + struct chan *c = &k->c[n]; + u32 c0 = reg(c->conf0); + c->sel = (c0 & 3u) + (n >= 8 ? 4u : 0u); /* its group's timer */ + c->hp = reg(c->hpoint) & 0xfffffu; + c->en = (c0 & C_SIG_OUT_EN) != 0; + c->idle = (c0 & C_IDLE_LV) != 0; + c->update = 0; + if (!c->en) + drive(k, n, (int)c->idle); +} + +/* the low point of the period starting: HPOINT + the duty, a count longer + * in DUTY[3:0] periods of 16 */ +static void period_start(struct e32_ledc *k, int n) +{ + struct chan *c = &k->c[n]; + u32 frac = c->duty_cur & 0xfu, d = c->duty_cur >> 4; + c->dither += frac; + if (c->dither >= 16u) { + c->dither -= 16u; + d++; + } + c->lp = c->hp + d; + esk_rf_hw(c->duty_r, c->duty_cur); +} + +/* the timer overflowed: what waits for it */ +static void overflow(struct e32_ledc *k, int x) +{ + struct tmr *t = &k->t[x]; + int n; + if (t->update) { + t->res = reg(t->conf) & 0x1fu; + t->div = (reg(t->conf) >> 5) & 0x3ffffu; + t->update = 0; + } + raise(k, 1u << x); + for (n = 0; n < NCH; n++) { + struct chan *c = &k->c[n]; + u32 c1; + if (c->sel != (u32)x) + continue; + if (c->update) + chan_apply(k, n); + c1 = reg(c->conf1); + if (c->fading) { + u32 every = (c1 >> 10) & 0x3ffu; + if (++c->cyc >= (every ? every : 1u)) { + u32 num = (c1 >> 20) & 0x3ffu, scale = (c1 & 0x3ffu) << 4; + c->cyc = 0; + if (c->steps < num) { + if (c1 & F_INC) + c->duty_cur = c->duty_cur + scale > 0x1ffffffu ? 0x1ffffffu : c->duty_cur + scale; + else + c->duty_cur = c->duty_cur > scale ? c->duty_cur - scale : 0; + c->steps++; + } + if (c->steps >= num) { + c->fading = 0; + raise(k, 1u << (8 + n)); + } + } + } + if (c->sel == (u32)x) + period_start(k, n); + } +} + +/* the timer entered count `cnt`: the outputs that switch there */ +static void at_count(struct e32_ledc *k, int x) +{ + struct tmr *t = &k->t[x]; + int n; + for (n = 0; n < NCH; n++) { + struct chan *c = &k->c[n]; + if (c->sel != (u32)x || !c->en) + continue; + if (t->cnt == c->hp && c->lp != c->hp) + drive(k, n, 1); + if (t->cnt == c->lp) + drive(k, n, 0); + } +} + +/* the next count after the present one where something happens: an output + * switching or the overflow (top + 1) */ +static u32 next_count(const struct e32_ledc *k, int x) +{ + const struct tmr *t = &k->t[x]; + u32 best = top(t) + 1u; + int n; + for (n = 0; n < NCH; n++) { + const struct chan *c = &k->c[n]; + if (c->sel != (u32)x || !c->en) + continue; + if (c->hp > t->cnt && c->hp < best) + best = c->hp; + if (c->lp > t->cnt && c->lp < best) + best = c->lp; + } + return best; +} + +/* fs from the present to the timer's next event, or 0 when it stands */ +static u64 due(const struct e32_ledc *k, int x) +{ + const struct tmr *t = &k->t[x]; + double tf = tick_fs(k, t); + u64 at; + if (tf <= 0) + return 0; + at = (u64)((double)next_count(k, x) * tf + 0.5); + return at > t->pos ? at - t->pos : 1u; +} + +static void clocking(struct e32_ledc *k) +{ + int x, on = 0; + for (x = 0; x < NTM; x++) + if (tick_fs(k, &k->t[x]) > 0) + on = 1; + esk_rf_clock(k->p, &k->clocked, on); +} + +static void advance(struct e32_ledc *k, u64 budget) +{ + struct esk_mach *s = k->s; + u64 fpc = fs_per_cycle(k); + int x; + if (!fpc) + return; + for (;;) { + u64 d = 0; + int which = -1; + for (x = 0; x < NTM; x++) { + u64 dx = due(k, x); + if (dx && (which < 0 || dx < d)) { + d = dx; + which = x; + } + } + if (which < 0 || d > budget) { + for (x = 0; x < NTM; x++) { + struct tmr *t = &k->t[x]; + double tf = tick_fs(k, t); + if (tf <= 0) + continue; + t->pos += budget; + t->cnt = (u32)((double)t->pos / tf); + if (t->cnt > top(t)) + t->cnt = top(t); + } + break; + } + budget -= d; + s->output_lag = (u32)(budget / fpc); + for (x = 0; x < NTM; x++) { + struct tmr *t = &k->t[x]; + double tf = tick_fs(k, t); + if (tf <= 0) + continue; + if (x == which) { + u32 c = next_count(k, x); + t->pos += d; + if (c > top(t)) { + t->pos = 0; + t->cnt = 0; + overflow(k, x); + } else { + t->cnt = c; + } + at_count(k, x); + } else { + t->pos += d; + t->cnt = (u32)((double)t->pos / tf); + } + } + s->output_lag = 0; + } + for (x = 0; x < NTM; x++) + esk_rf_hw(k->t[x].value, k->t[x].cnt & 0xfffffu); +} + +static void ledc_tick(void *ctx, u32 cycles) +{ + struct e32_ledc *k = (struct e32_ledc *)ctx; + advance(k, (u64)cycles * fs_per_cycle(k)); +} + +static int ledc_next(void *ctx, u32 *cycles) +{ + struct e32_ledc *k = (struct e32_ledc *)ctx; + u64 fpc = fs_per_cycle(k), best = 0; + int x, any = 0; + if (!fpc) + return 0; + for (x = 0; x < NTM; x++) { + u64 d = due(k, x), c; + if (!d) + continue; + c = (d + fpc - 1u) / fpc; + if (!any || c < best) + best = c; + any = 1; + } + if (!any) + return 0; + *cycles = best == 0 ? 1u : best > 0xffffffffu ? 0xffffffffu : (u32)best; + return 1; +} + +static u32 ledc_read(void *ctx, u32 off, int n) +{ + struct e32_ledc *k = (struct e32_ledc *)ctx; + return esk_rf_read(k->p, off, n); +} + +/* the timer starts counting (out of RST): its generators' first period */ +static void timer_starts(struct e32_ledc *k, int x) +{ + int n; + for (n = 0; n < NCH; n++) + if (k->c[n].sel == (u32)x) + period_start(k, n); + at_count(k, x); +} + +static void ledc_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_ledc *k = (struct e32_ledc *)ctx; + u32 w = off & ~3u, held[NTM]; + int i; + for (i = 0; i < NTM; i++) + held[i] = reg(k->t[i].conf) & T_RST; + if (w == 0x18Cu) { /* INT_CLR */ + esk_rf_hw(k->raw, reg(k->raw) & ~v); + update(k); + return; + } + if (w == 0x184u) + return; /* INT_ST */ + esk_rf_write(k->p, off, n, v); + if (w == 0x180u || w == 0x188u) + update(k); + for (i = 0; i < NTM; i++) { + struct tmr *t = &k->t[i]; + if (w != esk_rf_off(t->conf)) + continue; + if (reg(t->conf) & T_RST) { + t->cnt = 0; + t->pos = 0; + } + if (i < 4 || (v & T_PARA_UP)) + t->update = 1; /* a high-speed timer's settings: at its next overflow */ + if (!t->div && !t->res) /* never set: the first settings at once */ + t->update = 1; + if (t->update && (reg(t->conf) & T_RST)) { /* held: nothing to wait for */ + t->res = reg(t->conf) & 0x1fu; + t->div = (reg(t->conf) >> 5) & 0x3ffffu; + t->update = 0; + } + if (held[i] && !(reg(t->conf) & T_RST)) + timer_starts(k, i); + } + for (i = 0; i < NCH; i++) { + struct chan *c = &k->c[i]; + /* a high-speed channel takes DUTY_START (CONF1), a low-speed one + * its PARA_UP (CONF0) after it */ + if (!(i < 8 ? w == esk_rf_off(c->conf1) && (v & F_START) : w == esk_rf_off(c->conf0) && (v & C_PARA_UP))) + continue; + { + u32 c1 = reg(c->conf1); + c->update = 1; + c->duty_cur = reg(c->duty) & 0x1ffffffu; /* the fade's start, at once */ + c->fading = (c1 & F_START) != 0; + c->cyc = 0; + c->steps = 0; + esk_rf_hw(c->duty_r, c->duty_cur); + if (tick_fs(k, &k->t[c->sel]) <= 0) { /* no overflow coming: now */ + chan_apply(k, i); + period_start(k, i); + } + } + } + clocking(k); +} + +static void ledc_reset(void *ctx) +{ + struct e32_ledc *k = (struct e32_ledc *)ctx; + int i; + for (i = 0; i < NTM; i++) { + struct tmr *t = &k->t[i]; + t->res = reg(t->conf) & 0x1fu; + t->div = (reg(t->conf) >> 5) & 0x3ffffu; + t->update = 0; + t->cnt = 0; + t->pos = 0; + } + for (i = 0; i < NCH; i++) { + struct chan *c = &k->c[i]; + c->update = 0; + c->duty_cur = 0; + c->lp = 0; + c->dither = 0; + c->fading = 0; + c->cyc = c->steps = c->ovf = 0; + c->out = -1; + chan_apply(k, i); + drive(k, i, (int)c->idle); + } + k->level = 0; + esk_esp32_source(k->s, k->source, 0); + k->clocked = 0; + update(k); + clocking(k); +} + +const struct esk_dev_ops esk_esp32_ledc_ops = { + "esp32-ledc", ledc_read, ledc_write, ledc_reset, ledc_tick, ledc_next, +}; + +void *esk_esp32_ledc_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_ledc *k = (struct e32_ledc *)esk_mach_alloc(s, sizeof *k); + char name[24]; + int i; + if (!k) + return 0; + memset(k, 0, sizeof *k); + k->s = s; + k->p = p; + k->conf = esk_rf_reg(p, "CONF"); + k->raw = esk_rf_reg(p, "INT_RAW"); + k->st = esk_rf_reg(p, "INT_ST"); + k->ena = esk_rf_reg(p, "INT_ENA"); + if (!k->conf || !k->raw || !k->st || !k->ena) + return 0; + k->source = esk_rf_irq(p, "LEDC"); + for (i = 0; i < NTM; i++) { + snprintf(name, sizeof name, "%sTIMER%d_CONF", i < 4 ? "HS" : "LS", i % 4); + k->t[i].conf = esk_rf_reg(p, name); + snprintf(name, sizeof name, "%sTIMER%d_VALUE", i < 4 ? "HS" : "LS", i % 4); + k->t[i].value = esk_rf_reg(p, name); + if (!k->t[i].conf || !k->t[i].value) + return 0; + } + for (i = 0; i < NCH; i++) { + struct chan *c = &k->c[i]; + snprintf(name, sizeof name, "%sCH%d_CONF0", i < 8 ? "HS" : "LS", i % 8); + c->conf0 = esk_rf_reg(p, name); + snprintf(name, sizeof name, "%sCH%d_HPOINT", i < 8 ? "HS" : "LS", i % 8); + c->hpoint = esk_rf_reg(p, name); + snprintf(name, sizeof name, "%sCH%d_DUTY", i < 8 ? "HS" : "LS", i % 8); + c->duty = esk_rf_reg(p, name); + snprintf(name, sizeof name, "%sCH%d_CONF1", i < 8 ? "HS" : "LS", i % 8); + c->conf1 = esk_rf_reg(p, name); + snprintf(name, sizeof name, "%sCH%d_DUTY_R", i < 8 ? "HS" : "LS", i % 8); + c->duty_r = esk_rf_reg(p, name); + if (!c->conf0 || !c->hpoint || !c->duty || !c->conf1 || !c->duty_r) + return 0; + } + return k; +} diff --git a/core/mcu/models.c b/core/mcu/models.c index 954533580..314801791 100644 --- a/core/mcu/models.c +++ b/core/mcu/models.c @@ -71,6 +71,7 @@ static const struct esk_rf_model_type model_types[] = { { "esp32-spi", &esk_esp32_spi_ops, esk_esp32_spi_create }, { "esp32-timg", &esk_esp32_timg_ops, esk_esp32_timg_create }, { "esp32-sha", &esk_esp32_sha_ops, esk_esp32_sha_create }, + { "esp32-ledc", &esk_esp32_ledc_ops, esk_esp32_ledc_create }, { "esp32-iomux", &esk_esp32_iomux_ops, esk_esp32_iomux_create }, { "esp32c3-intmtx", &esk_esp32c3_intmtx_ops, esk_esp32c3_intmtx_create }, { "esp32c3-uart", &esk_esp32c3_uart_ops, esk_esp32c3_uart_create }, diff --git a/docs/STATUS.md b/docs/STATUS.md index d43415860..c563bbea0 100644 --- a/docs/STATUS.md +++ b/docs/STATUS.md @@ -14,9 +14,10 @@ Espressif's ROM (ECO3), ESP-IDF v5.4's second-stage bootloader and its hello_world running unmodified on both cores at 160 MHz to `Hello world!` and through `esp_restart` (rst:0xc SW_CPU_RESET). Evidence: `test_lx6` (4,332 checks), the board's three fixtures, and the ESP-IDF vendor -scenario `esp32_hello_world` (9/9). Not yet: Wi-Fi and Bluetooth, the +scenarios `esp32_hello_world` (9/9), `esp32_blink` (6/6) and +`esp32_ledc_basic` (2/2). Not yet: Wi-Fi and Bluetooth, the double-precision accelerator's instructions, the peripherals the -description's fidelity lists (I2C, I2S, SPI2/3, RMT, LEDC, ADC, ...), +description's fidelity lists (I2C, I2S, SPI2/3, RMT, ADC, ...), sleep. The standalone harness below remains as its own qualification fixtures. diff --git a/docs/coverage.md b/docs/coverage.md index 3c4dc6e27..00c64da55 100644 --- a/docs/coverage.md +++ b/docs/coverage.md @@ -8,7 +8,7 @@ evidence for each model is in [STATUS.md](STATUS.md). | MCU | Modelled | Registers only | Missing | Peripherals | |---|---|---|---|---| -| ESP32 | 14 | 0 | 31 | 45 | +| ESP32 | 15 | 0 | 30 | 45 | | ESP32-C3 | 35 | 0 | 0 | 35 | | ATmega328P | 15 | 0 | 0 | 15 | | PIC24FJ1024GB610 | 11 | 4 | 17 | 32 | @@ -23,7 +23,7 @@ evidence for each model is in [STATUS.md](STATUS.md). ## ESP32 (`espressif/esp32`) Boards: ESP32-DevKitC V4. -14 of 45 peripherals modelled, 0 registers only, 31 missing. +15 of 45 peripherals modelled, 0 registers only, 30 missing. | Peripheral | Model | State | |---|---|---| @@ -53,7 +53,7 @@ Boards: ESP32-DevKitC V4. | RMT | — | **missing** | | PCNT | — | **missing** | | SLC | — | **missing** | -| LEDC | — | **missing** | +| LEDC | `esp32-ledc` | modelled | | EFUSE | `esp32-efuse` | modelled | | NRX | — | **missing** | | BB | — | **missing** | @@ -73,7 +73,7 @@ Boards: ESP32-DevKitC V4. | I2S1 | — | **missing** | | UART2 | `esp32-uart` | modelled | -Declared omissions: Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written); the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept; PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts; the peripherals without a model yet: I2C0/1, I2S0/1, SPI2/3 (HSPI, VSPI), RMT, LEDC, MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption; sleep modes (light and deep sleep, the power domains), brown-out; the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection. +Declared omissions: Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written); the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept; PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts; the peripherals without a model yet: I2C0/1, I2S0/1, SPI2/3 (HSPI, VSPI), RMT, MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption; sleep modes (light and deep sleep, the power domains), brown-out; the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection. ## ESP32-C3 (`espressif/esp32c3`) diff --git a/tests/vendor/esp-idf/examples/esp32_ledc_basic/project.json b/tests/vendor/esp-idf/examples/esp32_ledc_basic/project.json new file mode 100644 index 000000000..dab003ced --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_ledc_basic/project.json @@ -0,0 +1,66 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "esp-idf-esp32_ledc_basic", + "description": "ESP-IDF's ledc_basic on the ESP32-DevKitC V4: the low-speed timer 0 at 4 kHz, 13 bits, channel 0 at half duty on GPIO5.", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + } + ], + "nets": { + "USB5V": [ + "USB.+", + "B1.VBUS" + ], + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + }, + { + "id": "pwm", + "target": "net:B1.GPIO5", + "kind": "digital" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_ledc_basic/scenario.json b/tests/vendor/esp-idf/examples/esp32_ledc_basic/scenario.json new file mode 100644 index 000000000..2fffa0c63 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_ledc_basic/scenario.json @@ -0,0 +1,33 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "esp32_ledc_basic", + "until": "1200ms", + "description": "ledc_basic on the ESP32: the low-speed timer 0 at 4 kHz with 13 bits from APB_CLK (ESP-IDF's divider, CONF's APB_CLK_SEL), channel 0 at a duty of 4096/8192 on GPIO5 through the GPIO matrix (ledc_ls_sig_out0).", + "inputs": [], + "assertions": [ + { + "id": "frequency", + "between": [ + "1000ms", + "1100ms" + ], + "probe": "pwm", + "expect": { + "frequency_hz": 4000, + "tolerance": 0.01 + } + }, + { + "id": "edges", + "between": [ + "1000ms", + "1100ms" + ], + "probe": "pwm", + "expect": { + "edges": 800 + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/run.py b/tests/vendor/esp-idf/run.py index 5e552a009..55b9e73b1 100644 --- a/tests/vendor/esp-idf/run.py +++ b/tests/vendor/esp-idf/run.py @@ -73,12 +73,14 @@ "wifi_station_open": "examples/wifi/getting_started/station", "esp32_hello_world": "examples/get-started/hello_world", "esp32_blink": "examples/get-started/blink", + "esp32_ledc_basic": "examples/peripherals/ledc/ledc_basic", } # the target an example is built for, when not the ESP32-C3 (its board in # examples//project.json), and the toolchain that target needs TARGETS = { "esp32_hello_world": "esp32", "esp32_blink": "esp32", + "esp32_ledc_basic": "esp32", } TOOLCHAINS = {"esp32c3": "riscv32-esp-elf-gcc", "esp32": "xtensa-esp32-elf-gcc"} # examples built only for another's project (with examples//'s From 5fabb5c107f970e8fea87853ecbd88d4f81ab767 Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 03:45:32 +0000 Subject: [PATCH 06/16] ESP32: the supply current from the datasheet's power modes Datasheet v5.3 table 4-2: Modem-sleep of the dual-core chips at 80, 160 and 240 MHz (the range's low end waiting, high end running), 1 uA held; table 5-4's radio currents for when the radios are modelled. --- catalog/mcus/espressif/esp32/mcu.json | 44 +++++++++++++++++++++++++-- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/catalog/mcus/espressif/esp32/mcu.json b/catalog/mcus/espressif/esp32/mcu.json index abcc6854c..c86b2d9aa 100644 --- a/catalog/mcus/espressif/esp32/mcu.json +++ b/catalog/mcus/espressif/esp32/mcu.json @@ -220,6 +220,44 @@ "iol_max": 0.028 } }, + "supply": { + "doc": "ESP32 Series Datasheet v5.3, table 4-2 (power consumption by power modes): Modem-sleep of the dual-core chips, 20-31 mA at 80 MHz, 27-44 mA at 160 MHz, 30-68 mA at 240 MHz, taken as the low end with the CPUs waiting and the high end running (the datasheet gives the range by load, not the split); power off with CHIP_PU low 1 uA. The radios' currents of table 5-4 (802.11b 1 Mbps at +19.5 dBm 240 mA, 802.11g 54 Mbps at +16 dBm 190 mA, 802.11n MCS7 at +14 dBm 180 mA, receiving 95-100 mA) for when they are modelled.", + "run_a": [ + [ + 80000000, + 0.031 + ], + [ + 160000000, + 0.044 + ], + [ + 240000000, + 0.068 + ] + ], + "idle_a": [ + [ + 80000000, + 0.02 + ], + [ + 160000000, + 0.027 + ], + [ + 240000000, + 0.03 + ] + ], + "held_a": 1e-06, + "radio": { + "rx_a": 0.1, + "tx_dsss_a": 0.24, + "tx_ofdm_a": 0.19, + "tx_ht_a": 0.18 + } + }, "console": { "default": "UART0" }, @@ -250,10 +288,10 @@ "validation": [] }, "electrical": { - "claims": "GPIO pin-model defaults at 3.3 V from the datasheet's DC characteristics: VIH 0.75 VDD, VIL 0.25 VDD, VOH 0.8 VDD, VOL 0.1 VDD, 45 kOhm pulls; GPIO34-39 inputs only.", + "claims": "GPIO pin-model defaults at 3.3 V from the datasheet's DC characteristics: VIH 0.75 VDD, VIL 0.25 VDD, VOH 0.8 VDD, VOL 0.1 VDD, 45 kOhm pulls; GPIO34-39 inputs only. The supply current (ADR-036, datasheet v5.3's power modes): the cores running and waiting at their clock, and held off.", "omissions": [ - "the supply current (the datasheet's power modes are not yet in the description)", - "the pads' drive strengths' effect" + "the pads' drive strengths' effect", + "each peripheral's own current (the datasheet gives the modes, not the parts)" ], "validation": [] } From 2f3d4df74a61534876f9a567e8da5eb4c222b6ae Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 04:08:53 +0000 Subject: [PATCH 07/16] ESP32: I2C0 and I2C1, with ESP-IDF's i2c_eeprom The ESP32's I2C controllers from the C3's bit-level model on the ESP32's registers: 16 commands with its op codes (RSTART 0, WRITE 1, READ 2, STOP 3, END 4), the bus timing in APB_CLK cycles as i2c_ll counts it (SCL high + 7, or the filter's share), ACK_ERR, arbitration, the SCL timeout, the FIFOs through DATA and its AHB view, master and slave. The GPIO model gains the signal watch the controller follows the lines with, and DPORT's PERIP_RST_EN resets I2C0, I2C1 and LEDC. ESP-IDF v5.4's i2c_eeprom passes unmodified on the DevKitC with a 24LC256 (esp32_i2c_eeprom 3/3). --- CHANGELOG.md | 8 +- catalog/mcus/espressif/esp32/mcu.json | 9 +- core/mcu/esp32/soc/dport.c | 29 +- core/mcu/esp32/soc/esp32.h | 5 + core/mcu/esp32/soc/gpio.c | 26 +- core/mcu/esp32/soc/i2c.c | 944 ++++++++++++++++++ core/mcu/models.c | 1 + docs/STATUS.md | 7 +- docs/coverage.md | 10 +- .../examples/esp32_i2c_eeprom/project.json | 126 +++ .../examples/esp32_i2c_eeprom/scenario.json | 34 + tests/vendor/esp-idf/run.py | 2 + 12 files changed, 1182 insertions(+), 19 deletions(-) create mode 100644 core/mcu/esp32/soc/i2c.c create mode 100644 tests/vendor/esp-idf/examples/esp32_i2c_eeprom/project.json create mode 100644 tests/vendor/esp-idf/examples/esp32_i2c_eeprom/scenario.json diff --git a/CHANGELOG.md b/CHANGELOG.md index bd9526d0a..b94e50c75 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -19,13 +19,15 @@ versions follow semantic versioning. There is no release yet. copy-table entry; the image equals QEMU's esp32-v3-rom.bin), the register file from esp32.svd, and models for DPORT (APP_CPU, caches and flash MMU, interrupt matrix), RTC_CNTL, eFuse, APB_CTRL clocks, GPIO/IO_MUX with - strapping, UART0-2, TIMG0/1, SPI0/1 with the GT25Q32A flash, SHA, LEDC, the - internal analog I2C, RNG and the AHB view. + strapping, UART0-2, TIMG0/1, SPI0/1 with the GT25Q32A flash, SHA, LEDC, + I2C0/1 (master and slave, 16 commands, APB_CLK timing; DPORT's + PERIP_RST_EN resets them), the internal analog I2C, RNG and the AHB view. - Added the `emblink/esp32_devkitc` board (ESP32-DevKitC V4, WROOM-32E) with its power path, LED, Boot and EN buttons, headers and fixtures. - Espressif's ROM, ESP-IDF v5.4's bootloader and hello_world run unmodified through `esp_restart` (`tests/vendor/esp-idf`: `esp32_hello_world` 9/9, - `esp32_blink` 6/6, `esp32_ledc_basic` 2/2); `test_lx6` checks the core with programs from Espressif's assembler. + `esp32_blink` 6/6, `esp32_ledc_basic` 2/2, `esp32_i2c_eeprom` 3/3 on a + 24LC256); `test_lx6` checks the core with programs from Espressif's assembler. ### Original ESP32 digital per-pin hold diff --git a/catalog/mcus/espressif/esp32/mcu.json b/catalog/mcus/espressif/esp32/mcu.json index c86b2d9aa..1bdc0f9b9 100644 --- a/catalog/mcus/espressif/esp32/mcu.json +++ b/catalog/mcus/espressif/esp32/mcu.json @@ -195,6 +195,10 @@ { "match": "LEDC", "model": "esp32-ledc" + }, + { + "match": "I2C?", + "model": "esp32-i2c" } ], "io": { @@ -263,12 +267,13 @@ }, "fidelity": { "functional": { - "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), the internal analog I2C master, the random number generator and the peripherals' AHB view.", + "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), I2C0 and I2C1 (master and slave on the open-drain lines through the matrix, the 16 commands with RSTART, WRITE, READ, STOP and END, the bus timing in APB_CLK cycles, ACK checks, arbitration, the SCL timeout, the 32-byte FIFOs through DATA and its AHB view, 7- and 10-bit slave addresses; ESP-IDF's i2c_eeprom runs on a 24LC256), PERIP_RST_EN's resets of I2C0, I2C1 and LEDC, the internal analog I2C master, the random number generator and the peripherals' AHB view.", "omissions": [ "Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written)", "the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept", "PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts", - "the peripherals without a model yet: I2C0/1, I2S0/1, SPI2/3 (HSPI, VSPI), RMT, MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption", + "I2C: the non-FIFO mode (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, the input filters (only their share of the SCL high time), 10-bit addressing's R/W check", + "the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), RMT, MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption", "sleep modes (light and deep sleep, the power domains), brown-out", "the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection" ], diff --git a/core/mcu/esp32/soc/dport.c b/core/mcu/esp32/soc/dport.c index f72c1c48c..1091cfbd1 100644 --- a/core/mcu/esp32/soc/dport.c +++ b/core/mcu/esp32/soc/dport.c @@ -26,7 +26,9 @@ * pages whose flash the program has written since they were mapped * show it after a flush; * - CPU_PER_CONF's CPUPERIOD_SEL, which with RTC_CNTL's SOC_CLK_SEL and - * APB_CTRL's divider sets the CPU's clock (apbctrl.c). + * APB_CTRL's divider sets the CPU's clock (apbctrl.c); + * - PERIP_RST_EN: setting the bit of I2C0 (7), LEDC (11) or I2C1 (18) + * returns that peripheral to its reset state. * Inside, the caches hold the mapped pages whole rather than 32 KB of * lines, and both CPUs read through the PRO_CPU's table (ESP-IDF keeps * the two the same); a CPU's cache enable and the buses' mask bits @@ -34,7 +36,9 @@ * Not yet: the cache's lock regions, PSRAM (DRAM1, which the module does * not have), the boot remap (PRO_BOOT_REMAP_CTRL), the APB and AHB * access permissions (DPORT_APB_MASK, AHBLITE_MPU_TABLE), the MMU's - * access-error interrupts, the trace memory and the CPU record. */ + * access-error interrupts, the trace memory and the CPU record, the other + * peripherals' PERIP_RST_EN bits and every PERIP_CLK_EN gate (a gated + * peripheral still answers). */ #include #include "mcu/esp32/soc/esp32.h" @@ -56,6 +60,14 @@ #define APP_DCACHE_DBUG0 0x418u #define CACHE_FLUSH_ENA 0x10u #define CACHE_FLUSH_DONE 0x20u +#define PERIP_RST_EN 0xC4u + +/* PERIP_RST_EN's bits of the modelled peripherals */ +static const struct { + const char *name; + int bit; +} resets[] = { { "I2C0", 7 }, { "LEDC", 11 }, { "I2C1", 18 } }; +#define NRESETS (sizeof resets / sizeof resets[0]) #define MMU_BASE 0x3FF10000u #define MMU_WORDS 2048 /* per CPU: 0x2000 bytes */ @@ -74,6 +86,7 @@ struct e32_dport { u32 mmu[2][MMU_WORDS]; u8 stale[128]; u8 *app_rom; /* the ROM as the APP_CPU sees it */ + struct esk_rf_periph *rst[3]; /* resets[]'s peripherals */ }; static struct e32_dport *dport_of(struct esk_mach *m) @@ -287,8 +300,15 @@ static u32 dp_read(void *ctx, u32 off, int n) static void dp_write(void *ctx, u32 off, int n, u32 v) { struct e32_dport *k = (struct e32_dport *)ctx; + u32 was = reg(k, PERIP_RST_EN); + size_t i; esk_rf_write(k->p, off, n, v); - if (off >= APPCPU_CTRL_A && off <= APPCPU_CTRL_C) { + if (off == PERIP_RST_EN) { + u32 now = reg(k, PERIP_RST_EN); + for (i = 0; i < NRESETS; i++) + if (k->rst[i] && (now & ~was & (1u << resets[i].bit))) + esk_rf_periph_reset(k->rst[i]); + } else if (off >= APPCPU_CTRL_A && off <= APPCPU_CTRL_C) { app_cpu(k); } else if (off == PRO_CACHE_CTRL || off == APP_CACHE_CTRL) { u32 c = reg(k, off); @@ -328,10 +348,13 @@ const struct esk_dev_ops esk_esp32_dport_ops = { void *esk_esp32_dport_create(struct esk_mach *s, struct esk_rf_periph *p) { struct e32_dport *k = (struct e32_dport *)esk_mach_alloc(s, sizeof *k); + size_t i; if (!k) return 0; k->s = s; k->p = p; + for (i = 0; i < NRESETS; i++) + k->rst[i] = esk_rf_periph(s->rf, resets[i].name); if (esk_mach_add_dev(s, MMU_BASE, 2u * MMU_WORDS * 4u, &mmu_ops, k) != ES_OK || esk_esp32_misc_add(s) || esk_esp32_regi2c_add(s)) return 0; diff --git a/core/mcu/esp32/soc/esp32.h b/core/mcu/esp32/soc/esp32.h index 16b4c970c..01aba4180 100644 --- a/core/mcu/esp32/soc/esp32.h +++ b/core/mcu/esp32/soc/esp32.h @@ -17,6 +17,7 @@ * apbctrl.c APB_CTRL: the CPU's and APB's clock dividers * sha.c the SHA accelerator * ledc.c the LED PWM controller + * i2c.c I2C0 and I2C1 * misc.c the random number generator, the AHB view of the * peripherals */ #ifndef ESK_MCU_ESP32_SOC_H @@ -52,6 +53,8 @@ extern const struct esk_dev_ops esk_esp32_apbctrl_ops; void *esk_esp32_apbctrl_create(struct esk_mach *s, struct esk_rf_periph *p); extern const struct esk_dev_ops esk_esp32_ledc_ops; void *esk_esp32_ledc_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_i2c_ops; +void *esk_esp32_i2c_create(struct esk_mach *s, struct esk_rf_periph *p); extern const struct esk_dev_ops esk_esp32_sha_ops; void *esk_esp32_sha_create(struct esk_mach *s, struct esk_rf_periph *p); /* the RNG and the AHB view of the peripherals (misc.c): 0, or -1 */ @@ -95,6 +98,8 @@ void esk_esp32_pins_changed(struct esk_mach *m); void esk_esp32_signal(struct esk_mach *m, int sig, int level, int oe); /* a peripheral input signal's level as the matrix or the IO MUX gives it */ int esk_esp32_signal_in(struct esk_mach *m, int sig); +/* `fn` is called when a pad's input level changed: -1 when full */ +int esk_esp32_signal_watch(struct esk_mach *m, void (*fn)(void *ctx), void *ctx); /* the flash chip (spi.c) */ struct esk_esp32_nor; diff --git a/core/mcu/esp32/soc/gpio.c b/core/mcu/esp32/soc/gpio.c index cbd07fb86..df156be19 100644 --- a/core/mcu/esp32/soc/gpio.c +++ b/core/mcu/esp32/soc/gpio.c @@ -27,7 +27,8 @@ * - A peripheral input (GPIO_FUNCy_IN_SEL_CFG) comes through the matrix * from IN_SEL's pad (0x38: 1, 0x30: 0, IN_INV_SEL inverting) when SEL * is set, else directly from the pad whose IO MUX function it is, else - * 0. + * 0 (1 for the I2C controllers' SCL and SDA). A model may watch the + * pads' input levels (esk_esp32_signal_watch). * - Interrupts (GPIO_PINn's INT_TYPE: 1 rising, 2 falling, 3 any edge, * 4 low level, 5 high level; INT_ENA bit 0 the APP_CPU's, 1 its NMI's, * 2 the PRO_CPU's, 3 its NMI's) set GPIO_STATUS (STATUS1; W1TS and @@ -44,8 +45,7 @@ * reset. * IO MUX's pads come out of reset as the datasheet's table has them (each * pad's IE and pull), not with the SVD's one reset value for all. - * Not yet: the peripherals' signals but the UARTs' (a pad routed to one - * is not driven), the RTC IO MUX (RTC_IO's pad functions, its pulls, the + * Not yet: the RTC IO MUX (RTC_IO's pad functions, its pulls, the * hold), the input filter, sleep mode (the MCU_ pad bits, SLP_SEL), the * drive strengths' effect, the pads' wake-up, the SDIO interrupt. */ #include @@ -91,6 +91,11 @@ struct e32_gpio { esk_mach_pin cfg[NPIN]; u8 sig_on[NSIG], sig_lv[NSIG], sig_oe[NSIG]; int again; + struct { + void (*fn)(void *ctx); + void *ctx; + } watch[8]; + int nwatch; }; static u32 reg(const struct esk_rf_reg *r) { return r ? (u32)r->value : 0; } @@ -281,6 +286,9 @@ static void settle(struct e32_gpio *k) esk_rf_hw(k->in, (u32)in); esk_rf_hw(k->in1, (u32)(in >> 32) & 0xffu); irqs(k, rise, fall); + if (rise | fall) + for (n = 0; n < k->nwatch; n++) + k->watch[n].fn(k->watch[n].ctx); if (k->again) goto again; k->busy = 0; @@ -315,6 +323,18 @@ int esk_esp32_signal_in(struct esk_mach *m, int sig) } if (sig == 14 && mux_sel(k, 3) == 0) /* U0RXD */ return (int)(k->input >> 3 & 1u); + /* the table's defaults: I2CEXT0/1's SCL and SDA idle high */ + return sig == 29 || sig == 30 || sig == 95 || sig == 96; +} + +int esk_esp32_signal_watch(struct esk_mach *m, void (*fn)(void *ctx), void *ctx) +{ + struct e32_gpio *k = gpio_of(m); + if (!k || k->nwatch >= (int)(sizeof k->watch / sizeof k->watch[0])) + return -1; + k->watch[k->nwatch].fn = fn; + k->watch[k->nwatch].ctx = ctx; + k->nwatch++; return 0; } diff --git a/core/mcu/esp32/soc/i2c.c b/core/mcu/esp32/soc/i2c.c new file mode 100644 index 000000000..5919bafe3 --- /dev/null +++ b/core/mcu/esp32/soc/i2c.c @@ -0,0 +1,944 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* i2c.c -- the ESP32's I2C controllers I2C0 and I2C1 (TRM v5 chapter 11) + * on the GPIO matrix's I2CEXT0_SCL and _SDA (signals 29 and 30) and + * I2CEXT1_SCL and _SDA (95 and 96), master or slave (CTR's MS_MODE), + * their interrupts on matrix sources 49 and 50. The ESP32-C3's model + * (mcu/esp32c3/i2c.c) on the ESP32's registers, timing and commands. + * + * - The controller runs from APB_CLK; its settings act as written (the + * ESP32 has no CONF_UPGATE). + * - A master runs COMD0-15 from TRANS_START: each command's byte_num + * (bits 7:0), ack_check_en (8), ack_exp (9), ack_value (10) and + * op_code (13:11: 0 RSTART, 1 WRITE, 2 READ, 3 STOP, 4 END), its + * COMMAND_DONE (bit 31) set when it is done. RSTART makes a START (once + * SCL is high) or a repeated START; WRITE sends byte_num bytes from the + * TX FIFO, the address among them, each with its ACK checked against + * ack_exp when ack_check_en is set (ACK_ERR, then a STOP and the + * commands stop); READ takes byte_num bytes into the RX FIFO, + * answering ack_value; STOP ends the transfer and the commands; END + * holds SCL low and stops (END_DETECT) until the next TRANS_START runs + * the commands from COMD0 again. Each byte a master sends or receives + * raises MASTER_TRAN_COMP and sets SR's BYTE_TRANS. + * - The bus's timing in APB_CLK cycles, as ESP-IDF's i2c_ll counts it: + * SCL low SCL_LOW_PERIOD + 1; let go, high from its rise for + * SCL_HIGH_PERIOD + 7, or + 8 with the SCL filter on at a threshold + * up to 2, + threshold + 6 above (a slave holding SCL low stretches + * the low time); SDA changes SDA_HOLD after SCL falls and is read + * SDA_SAMPLE after it rises; a START holds SDA low SCL_START_HOLD + * before SCL falls, a repeated START waits SCL_RSTART_SETUP with SCL + * high, a STOP SCL_STOP_SETUP before SDA rises and SCL_STOP_HOLD + * after it. + * - The lines are open-drain: with SCL_FORCE_OUT and SDA_FORCE_OUT the + * output is enabled throughout (the pad's PAD_DRIVER then makes it + * open-drain, as ESP-IDF configures it), without them the level and + * the enable are exchanged (low driven, high let go). A master letting + * SDA go that reads it low loses the bus (ARBITRATION_LOST, SR's + * ARB_LOST) and lets both lines go. SCL held low by someone else for + * more than TO's TIME_OUT_REG cycles ends the transfer (TIME_OUT, SR's + * TIME_OUT). + * - The TX and RX FIFOs (32 bytes each) are filled and emptied through + * DATA (ESP-IDF writes it through the AHB view, 0x6001301C and + * 0x6002701C, and reads it at the DPORT address): RXFIFO_OVF receiving + * into a full one; TX_FIFO_RST and RX_FIFO_RST empty them; TXFIFO_EMPTY + * while the TX FIFO holds fewer than TXFIFO_EMPTY_THRHD bytes and + * RXFIFO_FULL while the RX FIFO holds more than RXFIFO_FULL_THRHD; + * RXFIFO_ST and SR's counts follow them. + * - A slave answers SLAVE_ADDR (7 bits, or 10 with ADDR_10BIT_EN: the + * first byte 0x78 | its two high bits, then the low eight): it ACKs, + * puts the bytes written into the RX FIFO (with FIFO_ADDR_CFG_EN the + * first is the RAM address the bytes go to and come from), sends the + * TX FIFO's bytes when read (a NACK from the master ends them), ACKs + * a full RX FIFO (RXFIFO_OVF). SR's SLAVE_ADDRESSED and SLAVE_RW say + * how it was addressed; a STOP raises SLAVE_TRAN_COMP. + * - Both see the bus: BUS_BUSY from a START to a STOP, TRANS_COMPLETE at + * a STOP; TRANS_START when a master makes a START; ACK_REC is the last + * ACK. + * - INT_STATUS is INT_RAW and INT_ENA; INT_CLR clears. DPORT's + * PERIP_RST_EN bits 7 and 18 reset I2C0 and I2C1 (dport.c). + * Where it differs inside: the filters (SCL_ and SDA_FILTER_CFG) are not + * applied (the nets' levels are clean) beyond their share of the high + * time; SR's state fields read 0; a slave reacts at the edge it sees, not + * at its SDA_SAMPLE point. Not yet: the non-FIFO mode (NONFIFO_EN, its + * RX_REC_FULL and TX_SEND_EMPTY, the RAM read directly at 0x100), + * SAMPLE_SCL_LEVEL (sampling while SCL is low), 10-bit addressing's R/W + * check. */ +#include +#include +#include + +#include "mcu/esp32/soc/esp32.h" + +#define FS_PER_S 1000000000000000ull +#define NCMD 16 + +/* CTR */ +#define C_SDA_FORCE (1u << 0) +#define C_SCL_FORCE (1u << 1) +#define C_MS_MODE (1u << 4) +#define C_TRANS_START (1u << 5) +#define C_TX_LSB (1u << 6) +#define C_RX_LSB (1u << 7) +/* FIFO_CONF */ +#define F_ADDR_CFG (1u << 11) +#define F_RX_RST (1u << 12) +#define F_TX_RST (1u << 13) +/* INT_RAW */ +#define I_RXFIFO_FULL (1u << 0) +#define I_TXFIFO_EMPTY (1u << 1) +#define I_RXFIFO_OVF (1u << 2) +#define I_END_DETECT (1u << 3) +#define I_SLAVE_TRAN_COMP (1u << 4) +#define I_ARB_LOST (1u << 5) +#define I_MASTER_TRAN_COMP (1u << 6) +#define I_TRANS_COMPLETE (1u << 7) +#define I_TIME_OUT (1u << 8) +#define I_TRANS_START (1u << 9) +#define I_ACK_ERR (1u << 10) +/* SR */ +#define SR_ACK_REC (1u << 0) +#define SR_SLAVE_RW (1u << 1) +#define SR_TIME_OUT (1u << 2) +#define SR_ARB_LOST (1u << 3) +#define SR_BUS_BUSY (1u << 4) +#define SR_ADDRESSED (1u << 5) +#define SR_BYTE_TRANS (1u << 6) + +enum { OP_RSTART = 0, OP_WRITE = 1, OP_READ = 2, OP_STOP = 3, OP_END = 4 }; + +/* the master's step */ +enum { + P_IDLE, + P_WAIT_BUS, /* SCL low (someone holds it): a START waits for it */ + P_START, /* SDA low: SCL falls after the START hold */ + P_LOW0, /* SCL low: SDA changes after the hold */ + P_LOW1, /* SCL low: let go of it at the low period's end */ + P_WAITHI, /* SCL let go, waiting for it to rise */ + P_HIGH0, /* SCL high: SDA read at the sample point */ + P_HIGH1, /* SCL high: SCL falls at the high period's end */ + P_RS_SETUP, /* SCL high: SDA falls for the repeated START */ + P_STOP_SETUP, /* SCL high: SDA rises for the STOP */ + P_STOP_HOLD, /* the bus free time after a STOP */ + P_HELD /* END: SCL held low */ +}; + +/* what a clock pulse carries */ +enum { K_DOUT, K_DIN, K_AIN, K_AOUT, K_RS, K_STOP }; + +/* the slave's state */ +enum { S_IDLE, S_ADDR, S_ADDR2, S_RX, S_TX, S_WAIT }; + +struct e32_i2c { + struct esk_mach *s; + struct esk_rf_periph *p; + struct esk_rf_reg *ctr, *sr, *to, *saddr, *fifo_st, *fifo_conf, *raw, *ena, *st; + struct esk_rf_reg *low, *high, *hold, *sample, *sth, *rss, *sph, *sps, *sclf; + struct esk_rf_reg *comd[NCMD]; + int source, sig_scl, sig_sda; + /* the FIFOs' RAM */ + u8 txram[32], rxram[32]; + u32 twr, trd, tcnt, rwr, rrd, rcnt; + /* the lines: what it drives (1 lets go), what it sees */ + int scl_o, sda_o, scl_i, sda_i; + /* the next event: an absolute cycle and fs past it */ + int ev; + u64 ev_c, ev_f, cur_c, cur_f; + /* the master */ + int phase, kind, waiting_to, ci, op, bitn; + u32 cmd, nbytes, byte; + int sda_next; + /* the slave */ + int sstate, sbit, srw, sfirst, spend, spend_sda; + u32 sbyte; + int clocked, level, in_step; +}; + +static u32 reg(const struct esk_rf_reg *r) { return (u32)r->value; } + +static void update(struct e32_i2c *k) +{ + u32 st = reg(k->raw) & reg(k->ena) & 0x1fffu; + int level = st != 0; + esk_rf_hw(k->st, st); + if (level != k->level) { + k->level = level; + esk_esp32_source(k->s, k->source, level); + } +} + +static void raise(struct e32_i2c *k, u32 bits) +{ + esk_rf_hw(k->raw, reg(k->raw) | bits); + update(k); +} + +static void sr_set(struct e32_i2c *k, u32 bits, int on) +{ + esk_rf_hw(k->sr, on ? reg(k->sr) | bits : reg(k->sr) & ~bits); +} + +static u32 reverse8(u32 b) +{ + u32 r = 0; + int i; + for (i = 0; i < 8; i++) + r |= ((b >> i) & 1u) << (7 - i); + return r; +} + +/* ---- time ------------------------------------------------------------------ */ + +static double apb_fs(const struct e32_i2c *k) +{ + u32 hz = esk_esp32_apb_hz(k->s); + return hz ? (double)FS_PER_S / (double)hz : 0; +} + +static u64 fs_per_cycle(const struct e32_i2c *k) +{ + u32 hz = esk_mach_core_hz(k->s); + return hz ? FS_PER_S / hz : 0; +} + +/* the event `n` APB_CLK cycles after the present */ +static void after(struct e32_i2c *k, u32 n) +{ + u64 fpc = fs_per_cycle(k), d; + double af = apb_fs(k); + if (!fpc || af <= 0) { + k->ev = 0; + return; + } + d = (u64)((double)n * af + 0.5) + k->cur_f; + k->ev_c = k->cur_c + d / fpc; + k->ev_f = d % fpc; + k->ev = 1; + k->s->bus.touched = 1; /* the machine's next event may be this one */ +} + +/* the present: a register write's, an edge's or an event's time */ +static void now_at(struct e32_i2c *k, u64 cycle) +{ + k->cur_c = cycle; + k->cur_f = 0; +} + +static void clocking(struct e32_i2c *k) +{ + esk_rf_clock(k->p, &k->clocked, k->ev); +} + +/* ---- the lines ------------------------------------------------------------------ */ + +static void lines(struct e32_i2c *k, int scl, int sda) +{ + u32 c = reg(k->ctr); + int force_scl = (c & C_SCL_FORCE) != 0, force_sda = (c & C_SDA_FORCE) != 0; + k->scl_o = scl; + k->sda_o = sda; + esk_esp32_signal(k->s, k->sig_scl, scl, force_scl || !scl); + esk_esp32_signal(k->s, k->sig_sda, sda, force_sda || !sda); +} + +static int scl_in(struct e32_i2c *k) { return esk_esp32_signal_in(k->s, k->sig_scl); } +static int sda_in(struct e32_i2c *k) { return esk_esp32_signal_in(k->s, k->sig_sda); } + +/* ---- the FIFOs ------------------------------------------------------------------- */ + +static void fifo_status(struct e32_i2c *k) +{ + u32 conf = reg(k->fifo_conf), raw = reg(k->raw); + esk_rf_hw(k->sr, (reg(k->sr) & ~(0x3fu << 8 | 0x3fu << 18)) | (k->rcnt & 0x3fu) << 8 | (k->tcnt & 0x3fu) << 18); + esk_rf_hw(k->fifo_st, (k->rrd & 31u) | (k->rwr & 31u) << 5 | (k->trd & 31u) << 10 | (k->twr & 31u) << 15); + if (k->tcnt < ((conf >> 5) & 31u)) + raw |= I_TXFIFO_EMPTY; + if (k->rcnt > (conf & 31u)) + raw |= I_RXFIFO_FULL; + esk_rf_hw(k->raw, raw); + update(k); +} + +static u32 tx_pop(struct e32_i2c *k) +{ + u32 b = k->txram[k->trd & 31u]; + k->trd = (k->trd + 1u) & 31u; + if (k->tcnt) + k->tcnt--; + fifo_status(k); + return b; +} + +static void rx_push(struct e32_i2c *k, u32 b) +{ + if (k->rcnt >= 32u) { + raise(k, I_RXFIFO_OVF); + return; + } + k->rxram[k->rwr & 31u] = (u8)(b & 0xffu); + k->rwr = (k->rwr + 1u) & 31u; + k->rcnt++; + fifo_status(k); +} + +/* ---- the master ------------------------------------------------------------------ */ + +static u32 t_low(const struct e32_i2c *k) { return (reg(k->low) & 0x3fffu) + 1u; } + +static u32 t_high(const struct e32_i2c *k) +{ + u32 f = reg(k->sclf), thres = f & 7u, extra = 7u; + if (f & 8u) + extra = thres <= 2u ? 8u : thres + 6u; + return (reg(k->high) & 0x3fffu) + extra; +} + +static u32 at_least1(u32 v) { return v ? v : 1u; } +static u32 t_hold(const struct e32_i2c *k) { return at_least1(reg(k->hold) & 0x3ffu); } +static u32 t_sample(const struct e32_i2c *k) { return at_least1(reg(k->sample) & 0x3ffu); } + +static void master_idle(struct e32_i2c *k) +{ + k->phase = P_IDLE; + k->ev = 0; + lines(k, 1, 1); +} + +static void cmd_done(struct e32_i2c *k) +{ + if (k->ci < NCMD) + esk_rf_hw(k->comd[k->ci], reg(k->comd[k->ci]) | 1u << 31); +} + +/* a clock pulse from SCL's fall: SDA's level for it after the hold */ +static void begin_pulse(struct e32_i2c *k, int kind, int sda) +{ + u32 hold = t_hold(k), low = t_low(k); + k->kind = kind; + k->sda_next = sda; + k->phase = P_LOW0; + after(k, hold < low ? hold : low - 1u); +} + +static void begin_byte(struct e32_i2c *k) +{ + k->bitn = 0; + sr_set(k, SR_BYTE_TRANS, 0); + if (k->op == OP_WRITE) { + u32 b = tx_pop(k); + if (reg(k->ctr) & C_TX_LSB) /* the bits reversed: still sent from bit 7 */ + b = reverse8(b); + k->byte = b; + begin_pulse(k, K_DOUT, (int)((b >> 7) & 1u)); + } else { + k->byte = 0; + begin_pulse(k, K_DIN, 1); + } +} + +/* the next command, SCL low (or the bus idle for a first START) */ +static void next_command(struct e32_i2c *k) +{ + for (;;) { + u32 c; + if (k->ci >= NCMD) { + k->phase = P_HELD; + k->ev = 0; + return; + } + c = reg(k->comd[k->ci]); + k->cmd = c; + k->op = (int)((c >> 11) & 7u); + k->nbytes = c & 0xffu; + switch (k->op) { + case OP_RSTART: + if (k->phase == P_IDLE || k->phase == P_STOP_HOLD) { + if (!scl_in(k)) { + k->phase = P_WAIT_BUS; + k->ev = 0; + return; + } + k->phase = P_START; + raise(k, I_TRANS_START); + lines(k, 1, 0); + after(k, at_least1(reg(k->sth) & 0x3ffu)); + } else { + begin_pulse(k, K_RS, 1); + } + return; + case OP_WRITE: + case OP_READ: + if (!k->nbytes) { + cmd_done(k); + k->ci++; + continue; + } + begin_byte(k); + return; + case OP_STOP: + begin_pulse(k, K_STOP, 0); + return; + case OP_END: + cmd_done(k); + k->phase = P_HELD; + k->ev = 0; + raise(k, I_END_DETECT); + return; + default: /* not a command: nothing to do */ + cmd_done(k); + k->ci++; + continue; + } + } +} + +/* SCL just fell after a pulse: what comes next */ +static void pulse_done(struct e32_i2c *k) +{ + switch (k->kind) { + case K_DOUT: + if (++k->bitn < 8) { + begin_pulse(k, K_DOUT, (int)((k->byte >> (7 - k->bitn)) & 1u)); + return; + } + begin_pulse(k, K_AIN, 1); + return; + case K_DIN: + if (++k->bitn < 8) { + begin_pulse(k, K_DIN, 1); + return; + } + begin_pulse(k, K_AOUT, (int)((k->cmd >> 10) & 1u)); + return; + case K_AIN: { + int ack = (reg(k->sr) & SR_ACK_REC) != 0; + sr_set(k, SR_BYTE_TRANS, 1); + raise(k, I_MASTER_TRAN_COMP); + if ((k->cmd & (1u << 8)) && ack != (int)((k->cmd >> 9) & 1u)) { + raise(k, I_ACK_ERR); + k->ci = NCMD; /* the commands stop */ + begin_pulse(k, K_STOP, 0); + return; + } + break; + } + case K_AOUT: { + u32 b = k->byte; + if (reg(k->ctr) & C_RX_LSB) + b = reverse8(b); + rx_push(k, b); + sr_set(k, SR_BYTE_TRANS, 1); + raise(k, I_MASTER_TRAN_COMP); + break; + } + case K_RS: + cmd_done(k); + k->ci++; + next_command(k); + return; + default: + return; + } + /* a byte done */ + if (--k->nbytes > 0) { + begin_byte(k); + return; + } + cmd_done(k); + k->ci++; + next_command(k); +} + +/* SCL is high: the high time counts from its rise */ +static void high_begins(struct e32_i2c *k) +{ + u32 s = t_sample(k), h = t_high(k); + k->waiting_to = 0; + switch (k->kind) { + case K_RS: + k->phase = P_RS_SETUP; + after(k, at_least1(reg(k->rss) & 0x3ffu)); + return; + case K_STOP: + k->phase = P_STOP_SETUP; + after(k, at_least1(reg(k->sps) & 0x3ffu)); + return; + default: + k->phase = P_HIGH0; + after(k, s < h ? s : h - 1u); + return; + } +} + +static void master_step(struct e32_i2c *k) +{ + switch (k->phase) { + case P_START: + lines(k, 0, 0); + cmd_done(k); + k->ci++; + next_command(k); + return; + case P_LOW0: + lines(k, 0, k->sda_next); + k->phase = P_LOW1; + after(k, t_low(k) > t_hold(k) ? t_low(k) - t_hold(k) : 1u); + return; + case P_LOW1: + k->phase = P_WAITHI; + k->ev = 0; + lines(k, 1, k->sda_o); + if (k->phase == P_WAITHI && scl_in(k)) { + high_begins(k); + } else if (k->phase == P_WAITHI) { /* SCL held: the timeout */ + k->waiting_to = 1; + after(k, at_least1(reg(k->to) & 0xfffffu)); + } + return; + case P_WAITHI: /* the timeout came first */ + if (k->waiting_to) { + sr_set(k, SR_TIME_OUT, 1); + raise(k, I_TIME_OUT); + master_idle(k); + } + return; + case P_HIGH0: { + int sda = sda_in(k); + u32 h = t_high(k), s = t_sample(k); + if (k->kind == K_DOUT && k->sda_o && !sda) { + sr_set(k, SR_ARB_LOST, 1); + raise(k, I_ARB_LOST); + k->ci = NCMD; + master_idle(k); + return; + } + if (k->kind == K_DIN) + k->byte = k->byte << 1 | (u32)sda; + if (k->kind == K_AIN) + sr_set(k, SR_ACK_REC, sda); + k->phase = P_HIGH1; + after(k, h > s ? h - s : 1u); + return; + } + case P_HIGH1: + lines(k, 0, k->sda_o); + pulse_done(k); + return; + case P_RS_SETUP: + raise(k, I_TRANS_START); + lines(k, 1, 0); + k->phase = P_START; + after(k, at_least1(reg(k->sth) & 0x3ffu)); + return; + case P_STOP_SETUP: + lines(k, 1, 1); + cmd_done(k); + k->phase = P_STOP_HOLD; + after(k, at_least1(reg(k->sph) & 0x3fffu)); + return; + case P_STOP_HOLD: + k->phase = P_IDLE; + k->ev = 0; + return; + default: + return; + } +} + +/* ---- the slave -------------------------------------------------------------------- */ + +/* SDA's next level, SDA_HOLD after SCL fell */ +static void slave_sda(struct e32_i2c *k, int level) +{ + k->spend = 1; + k->spend_sda = level; + after(k, t_hold(k)); +} + +static u32 slave_tx_byte(struct e32_i2c *k) +{ + u32 b = k->txram[k->trd & 31u]; + k->trd = (k->trd + 1u) & 31u; + if (k->tcnt) + k->tcnt--; + fifo_status(k); + return b; +} + +static void slave_rise(struct e32_i2c *k) +{ + int sda = k->sda_i; + switch (k->sstate) { + case S_ADDR: + case S_ADDR2: + case S_RX: + if (k->sbit < 8) { + k->sbyte = k->sbyte << 1 | (u32)sda; + k->sbit++; + } else { + k->sbit = 9; + } + return; + case S_TX: + if (k->sbit < 8) { + k->sbit++; + } else { + k->sbit = 9; + sr_set(k, SR_ACK_REC, sda); + if (sda) /* the master's NACK: the last byte */ + k->sstate = S_WAIT; + } + return; + default: + return; + } +} + +static void slave_fall(struct e32_i2c *k) +{ + u32 sa = reg(k->saddr); + switch (k->sstate) { + case S_ADDR: + if (k->sbit == 8) { + if ((k->sbyte >> 1) != (sa & 0x7fu)) { + k->sstate = S_WAIT; + return; + } + k->srw = (int)(k->sbyte & 1u); + sr_set(k, SR_ADDRESSED, 1); + sr_set(k, SR_SLAVE_RW, k->srw); + k->sfirst = 1; + slave_sda(k, 0); + return; + } + if (k->sbit == 9) { /* after the address's ACK */ + k->sbit = 0; + k->sbyte = 0; + if ((sa & (1u << 31)) && !k->srw) { + k->sstate = S_ADDR2; + slave_sda(k, 1); + return; + } + if (k->srw) { + u32 b = slave_tx_byte(k); + k->sstate = S_TX; + k->sbyte = b; + slave_sda(k, (int)((b >> 7) & 1u)); + } else { + k->sstate = S_RX; + slave_sda(k, 1); + } + } + return; + case S_ADDR2: + if (k->sbit == 8) { + if ((k->sbyte & 0xffu) != ((sa >> 7) & 0xffu)) { + k->sstate = S_WAIT; + return; + } + slave_sda(k, 0); + return; + } + if (k->sbit == 9) { + k->sbit = 0; + k->sbyte = 0; + k->sstate = S_RX; + slave_sda(k, 1); + } + return; + case S_RX: + if (k->sbit == 8) { + u32 b = k->sbyte & 0xffu; + if (reg(k->ctr) & C_RX_LSB) + b = reverse8(b); + if (k->sfirst && (reg(k->fifo_conf) & F_ADDR_CFG)) /* the RAM address */ + k->rwr = k->trd = b & 31u; + else + rx_push(k, b); + k->sfirst = 0; + sr_set(k, SR_BYTE_TRANS, 1); + slave_sda(k, 0); + return; + } + if (k->sbit == 9) { + k->sbit = 0; + k->sbyte = 0; + sr_set(k, SR_BYTE_TRANS, 0); + slave_sda(k, 1); + } + return; + case S_TX: + if (k->sbit < 8) { + slave_sda(k, (int)((k->sbyte >> (7 - k->sbit)) & 1u)); + return; + } + if (k->sbit == 8) { /* the master's ACK: let SDA go */ + sr_set(k, SR_BYTE_TRANS, 1); + slave_sda(k, 1); + return; + } + { /* the next byte */ + u32 b; + k->sbit = 0; + sr_set(k, SR_BYTE_TRANS, 0); + b = slave_tx_byte(k); + k->sbyte = b; + slave_sda(k, (int)((b >> 7) & 1u)); + } + return; + default: + return; + } +} + +static void slave_step(struct e32_i2c *k) +{ + if (k->spend) { + k->spend = 0; + lines(k, 1, k->spend_sda); + } +} + +/* ---- the bus as seen -------------------------------------------------------------- */ + +static void watch(void *ctx) +{ + struct e32_i2c *k = (struct e32_i2c *)ctx; + struct esk_mach *s = k->s; + int scl = scl_in(k), sda = sda_in(k), master = (reg(k->ctr) & C_MS_MODE) != 0; + u64 lag = (u64)s->input_lead + s->output_lag; + if (scl == k->scl_i && sda == k->sda_i) + return; + if (!k->in_step) + now_at(k, s->cycles > lag ? s->cycles - lag : 0); + /* START and STOP: SDA moving while SCL stays high */ + if (scl && k->scl_i && sda != k->sda_i) { + k->sda_i = sda; + if (!sda) { + sr_set(k, SR_BUS_BUSY, 1); + if (!master) { + k->sstate = S_ADDR; + k->sbit = 0; + k->sbyte = 0; + k->spend = 0; + if (k->sda_o == 0 || k->scl_o == 0) + lines(k, 1, 1); + } + } else { /* a STOP */ + sr_set(k, SR_BUS_BUSY, 0); + raise(k, I_TRANS_COMPLETE); + if (!master) { + k->sstate = S_IDLE; + sr_set(k, SR_ADDRESSED, 0); + raise(k, I_SLAVE_TRAN_COMP); + if (k->sda_o == 0) + lines(k, 1, 1); + } + } + } + k->sda_i = sda; + if (scl != k->scl_i) { + k->scl_i = scl; + if (master) { + if (scl && k->phase == P_WAITHI) { + k->ev = 0; + high_begins(k); + } else if (scl && k->phase == P_WAIT_BUS) { + k->phase = P_IDLE; + next_command(k); + } + } else if (scl) { + slave_rise(k); + } else { + slave_fall(k); + } + } + clocking(k); +} + +/* ---- registers ---------------------------------------------------------------------- */ + +static void fsm_reset(struct e32_i2c *k) +{ + k->phase = P_IDLE; + k->ev = 0; + k->sstate = S_IDLE; + k->spend = 0; + k->waiting_to = 0; + lines(k, 1, 1); + k->scl_i = scl_in(k); + k->sda_i = sda_in(k); +} + +static void i2c_tick(void *ctx, u32 cycles) +{ + struct e32_i2c *k = (struct e32_i2c *)ctx; + struct esk_mach *s = k->s; + (void)cycles; + while (k->ev && k->ev_c <= s->cycles) { + k->ev = 0; + k->cur_c = k->ev_c; + k->cur_f = k->ev_f; + s->output_lag = (u32)(s->cycles - k->ev_c); + k->in_step = 1; + if (reg(k->ctr) & C_MS_MODE) + master_step(k); + else + slave_step(k); + k->in_step = 0; + s->output_lag = 0; + } + clocking(k); +} + +static int i2c_next(void *ctx, u32 *cycles) +{ + struct e32_i2c *k = (struct e32_i2c *)ctx; + u64 d; + if (!k->ev) + return 0; + d = k->ev_c > k->s->cycles ? k->ev_c - k->s->cycles : 1u; + *cycles = d > 0xffffffffu ? 0xffffffffu : (u32)d; + return 1; +} + +static u32 i2c_read(void *ctx, u32 off, int n) +{ + struct e32_i2c *k = (struct e32_i2c *)ctx; + if ((off & ~3u) == 0x1Cu) { /* DATA: the RX FIFO */ + u32 b = k->rxram[k->rrd & 31u]; + if (!k->rcnt) + return b; + k->rrd = (k->rrd + 1u) & 31u; + k->rcnt--; + fifo_status(k); + return b; + } + return esk_rf_read(k->p, off, n); +} + +static void i2c_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_i2c *k = (struct e32_i2c *)ctx; + u32 w = off & ~3u, was = reg(k->ctr); + now_at(k, k->s->cycles); + switch (w) { + case 0x1Cu: /* DATA: the TX FIFO */ + if (k->tcnt >= 32u) + return; /* full: the byte is lost */ + k->txram[k->twr & 31u] = (u8)(v & 0xffu); + k->twr = (k->twr + 1u) & 31u; + k->tcnt++; + fifo_status(k); + return; + case 0x24u: /* INT_CLR */ + esk_rf_hw(k->raw, reg(k->raw) & ~v); + fifo_status(k); /* the FIFO levels' interrupts raise again */ + return; + case 0x08u: + case 0x14u: + case 0x2Cu: + return; /* SR, RXFIFO_ST, INT_STATUS */ + default: + break; + } + esk_rf_write(k->p, off, n, v); + if (w == 0x20u || w == 0x28u) + update(k); + if (w == esk_rf_off(k->fifo_conf)) { + if (v & F_TX_RST) + k->twr = k->trd = k->tcnt = 0; + if (v & F_RX_RST) + k->rwr = k->rrd = k->rcnt = 0; + fifo_status(k); + } + if (w == esk_rf_off(k->ctr)) { + u32 c = reg(k->ctr); + if ((c ^ was) & (C_SCL_FORCE | C_SDA_FORCE | C_MS_MODE)) + lines(k, k->scl_o, k->sda_o); + if ((c & C_TRANS_START) && (c & C_MS_MODE) && apb_fs(k) > 0) { + int held = k->phase == P_HELD; + sr_set(k, SR_ARB_LOST | SR_TIME_OUT, 0); + k->ci = 0; + if (held) { /* SCL is low: the next command's pulse from now */ + k->phase = P_LOW0; + next_command(k); + } else if (k->phase == P_IDLE || k->phase == P_STOP_HOLD) { + k->phase = P_IDLE; + next_command(k); + } + } + esk_rf_hw(k->ctr, c & ~C_TRANS_START); /* it clears itself */ + } + clocking(k); +} + +static void i2c_reset(void *ctx) +{ + struct e32_i2c *k = (struct e32_i2c *)ctx; + k->twr = k->trd = k->tcnt = k->rwr = k->rrd = k->rcnt = 0; + k->level = 0; + esk_esp32_source(k->s, k->source, 0); + k->clocked = 0; + fsm_reset(k); + fifo_status(k); + update(k); + clocking(k); +} + +const struct esk_dev_ops esk_esp32_i2c_ops = { + "esp32-i2c", i2c_read, i2c_write, i2c_reset, i2c_tick, i2c_next, +}; + +void *esk_esp32_i2c_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_i2c *k = (struct e32_i2c *)esk_mach_alloc(s, sizeof *k); + static const struct { + size_t at; + const char *name; + } regs[] = { + { offsetof(struct e32_i2c, ctr), "CTR" }, + { offsetof(struct e32_i2c, sr), "SR" }, + { offsetof(struct e32_i2c, to), "TO" }, + { offsetof(struct e32_i2c, saddr), "SLAVE_ADDR" }, + { offsetof(struct e32_i2c, fifo_st), "RXFIFO_ST" }, + { offsetof(struct e32_i2c, fifo_conf), "FIFO_CONF" }, + { offsetof(struct e32_i2c, raw), "INT_RAW" }, + { offsetof(struct e32_i2c, ena), "INT_ENA" }, + { offsetof(struct e32_i2c, st), "INT_STATUS" }, + { offsetof(struct e32_i2c, low), "SCL_LOW_PERIOD" }, + { offsetof(struct e32_i2c, high), "SCL_HIGH_PERIOD" }, + { offsetof(struct e32_i2c, hold), "SDA_HOLD" }, + { offsetof(struct e32_i2c, sample), "SDA_SAMPLE" }, + { offsetof(struct e32_i2c, sth), "SCL_START_HOLD" }, + { offsetof(struct e32_i2c, rss), "SCL_RSTART_SETUP" }, + { offsetof(struct e32_i2c, sph), "SCL_STOP_HOLD" }, + { offsetof(struct e32_i2c, sps), "SCL_STOP_SETUP" }, + { offsetof(struct e32_i2c, sclf), "SCL_FILTER_CFG" }, + }; + char name[24]; + size_t i; + int unit; + if (!k) + return 0; + memset(k, 0, sizeof *k); + k->s = s; + k->p = p; + unit = strcmp(p->name, "I2C1") == 0; + k->source = unit ? 50 : 49; + k->sig_scl = unit ? 95 : 29; + k->sig_sda = unit ? 96 : 30; + for (i = 0; i < sizeof regs / sizeof regs[0]; i++) { + struct esk_rf_reg *r = esk_rf_reg(p, regs[i].name); + if (!r) + return 0; + memcpy((char *)k + regs[i].at, &r, sizeof r); + } + for (i = 0; i < NCMD; i++) { + snprintf(name, sizeof name, "COMD%d", (int)i); + if (!(k->comd[i] = esk_rf_reg(p, name))) + return 0; + } + if (esk_esp32_signal_watch(s, watch, k) != 0) + return 0; + return k; +} diff --git a/core/mcu/models.c b/core/mcu/models.c index 314801791..52c983242 100644 --- a/core/mcu/models.c +++ b/core/mcu/models.c @@ -72,6 +72,7 @@ static const struct esk_rf_model_type model_types[] = { { "esp32-timg", &esk_esp32_timg_ops, esk_esp32_timg_create }, { "esp32-sha", &esk_esp32_sha_ops, esk_esp32_sha_create }, { "esp32-ledc", &esk_esp32_ledc_ops, esk_esp32_ledc_create }, + { "esp32-i2c", &esk_esp32_i2c_ops, esk_esp32_i2c_create }, { "esp32-iomux", &esk_esp32_iomux_ops, esk_esp32_iomux_create }, { "esp32c3-intmtx", &esk_esp32c3_intmtx_ops, esk_esp32c3_intmtx_create }, { "esp32c3-uart", &esk_esp32c3_uart_ops, esk_esp32c3_uart_create }, diff --git a/docs/STATUS.md b/docs/STATUS.md index c563bbea0..511f80037 100644 --- a/docs/STATUS.md +++ b/docs/STATUS.md @@ -14,10 +14,11 @@ Espressif's ROM (ECO3), ESP-IDF v5.4's second-stage bootloader and its hello_world running unmodified on both cores at 160 MHz to `Hello world!` and through `esp_restart` (rst:0xc SW_CPU_RESET). Evidence: `test_lx6` (4,332 checks), the board's three fixtures, and the ESP-IDF vendor -scenarios `esp32_hello_world` (9/9), `esp32_blink` (6/6) and -`esp32_ledc_basic` (2/2). Not yet: Wi-Fi and Bluetooth, the +scenarios `esp32_hello_world` (9/9), `esp32_blink` (6/6), +`esp32_ledc_basic` (2/2) and `esp32_i2c_eeprom` (3/3, I2C0 writing and +reading a 24LC256 at 400 kHz). Not yet: Wi-Fi and Bluetooth, the double-precision accelerator's instructions, the peripherals the -description's fidelity lists (I2C, I2S, SPI2/3, RMT, ADC, ...), +description's fidelity lists (I2S, SPI2/3, RMT, ADC, ...), sleep. The standalone harness below remains as its own qualification fixtures. diff --git a/docs/coverage.md b/docs/coverage.md index 00c64da55..99d40d33f 100644 --- a/docs/coverage.md +++ b/docs/coverage.md @@ -8,7 +8,7 @@ evidence for each model is in [STATUS.md](STATUS.md). | MCU | Modelled | Registers only | Missing | Peripherals | |---|---|---|---|---| -| ESP32 | 15 | 0 | 30 | 45 | +| ESP32 | 17 | 0 | 28 | 45 | | ESP32-C3 | 35 | 0 | 0 | 35 | | ATmega328P | 15 | 0 | 0 | 15 | | PIC24FJ1024GB610 | 11 | 4 | 17 | 32 | @@ -23,7 +23,7 @@ evidence for each model is in [STATUS.md](STATUS.md). ## ESP32 (`espressif/esp32`) Boards: ESP32-DevKitC V4. -15 of 45 peripherals modelled, 0 registers only, 30 missing. +17 of 45 peripherals modelled, 0 registers only, 28 missing. | Peripheral | Model | State | |---|---|---| @@ -47,7 +47,7 @@ Boards: ESP32-DevKitC V4. | UHCI1 | — | **missing** | | I2S0 | — | **missing** | | UART1 | `esp32-uart` | modelled | -| I2C0 | — | **missing** | +| I2C0 | `esp32-i2c` | modelled | | UHCI0 | — | **missing** | | SLCHOST | — | **missing** | | RMT | — | **missing** | @@ -63,7 +63,7 @@ Boards: ESP32-DevKitC V4. | SPI2 | — | **missing** | | SPI3 | — | **missing** | | APB_CTRL | `esp32-apbctrl` | modelled | -| I2C1 | — | **missing** | +| I2C1 | `esp32-i2c` | modelled | | SDHOST | — | **missing** | | EMAC_DMA | — | **missing** | | EMAC_EXT | — | **missing** | @@ -73,7 +73,7 @@ Boards: ESP32-DevKitC V4. | I2S1 | — | **missing** | | UART2 | `esp32-uart` | modelled | -Declared omissions: Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written); the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept; PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts; the peripherals without a model yet: I2C0/1, I2S0/1, SPI2/3 (HSPI, VSPI), RMT, MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption; sleep modes (light and deep sleep, the power domains), brown-out; the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection. +Declared omissions: Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written); the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept; PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts; I2C: the non-FIFO mode (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, the input filters (only their share of the SCL high time), 10-bit addressing's R/W check; the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), RMT, MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption; sleep modes (light and deep sleep, the power domains), brown-out; the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection. ## ESP32-C3 (`espressif/esp32c3`) diff --git a/tests/vendor/esp-idf/examples/esp32_i2c_eeprom/project.json b/tests/vendor/esp-idf/examples/esp32_i2c_eeprom/project.json new file mode 100644 index 000000000..b6da657ea --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_i2c_eeprom/project.json @@ -0,0 +1,126 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "esp-idf-esp32_i2c_eeprom", + "description": "ESP-IDF's i2c/i2c_eeprom on the ESP32-DevKitC V4: a 24LC256 at 0x50 (A0-A2 and WP grounded) on SCL IO4 and SDA IO5 at 400 kHz, the example's defaults, with 4.7 kohm pull-ups to 3V3 (the example enables no internal pull-ups). The part's write cycle is set to 2 ms, a part faster than the datasheet's 5 ms maximum: the example waits pdMS_TO_TICKS(10), one tick at FreeRTOS's 100 Hz, which ends at the next tick, and a part taking its maximum would NACK the read, on a real bench too.", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + }, + { + "id": "U2", + "component": "emblink/eeprom_24lc256", + "params": { + "view_at": 16, + "twr": "2m" + }, + "layout": { + "x": 120, + "y": 460 + } + }, + { + "id": "R1", + "component": "emblink/resistor", + "params": { + "resistance": 4700 + }, + "layout": { + "x": 300, + "y": 440 + } + }, + { + "id": "R2", + "component": "emblink/resistor", + "params": { + "resistance": 4700 + }, + "layout": { + "x": 340, + "y": 440 + } + } + ], + "nets": { + "USB5V": [ + "USB.+", + "B1.VBUS" + ], + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1", + "U2.GND", + "U2.A0", + "U2.A1", + "U2.A2", + "U2.WP" + ], + "3V3": [ + "B1.3V3", + "U2.VCC", + "R1.1", + "R2.1" + ], + "I2C_SCL": [ + "B1.IO4", + "U2.SCL", + "R1.2" + ], + "I2C_SDA": [ + "B1.IO5", + "U2.SDA", + "R2.2" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + }, + { + "id": "eeprom", + "target": "output:U2.view", + "kind": "value" + }, + { + "id": "cycles", + "target": "output:U2.cycles", + "kind": "value" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_i2c_eeprom/scenario.json b/tests/vendor/esp-idf/examples/esp32_i2c_eeprom/scenario.json new file mode 100644 index 000000000..d2d891de0 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_i2c_eeprom/scenario.json @@ -0,0 +1,34 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "esp32_i2c_eeprom", + "until": "1500ms", + "description": "i2c_eeprom on the ESP32: 0..47 written in one transaction (two address bytes, 48 data, a page from 0x0010 within the 64-byte page), 10 ms for the write cycle, then read back with a repeated START and printed 16 to a line, again every 50 ticks (500 ms). I2C0 runs it as one command and an END at a time (the ESP32's STOP needs its own transfer, SOC_I2C_STOP_INDEPENDENT), from APB_CLK at 400 kHz.", + "inputs": [], + "assertions": [ + { + "id": "stored", + "at": "1s", + "probe": "eeprom", + "expect": { + "contains": "000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F202122232425262728292A2B2C2D2E2FFFFF" + } + }, + { + "id": "read-back", + "at": "1s", + "probe": "console", + "expect": { + "contains": "00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f \r\n10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f \r\n20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f \r\n" + } + }, + { + "id": "again", + "at": "1400ms", + "probe": "cycles", + "expect": { + "equals": 3 + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/run.py b/tests/vendor/esp-idf/run.py index 55b9e73b1..d5cd3d58d 100644 --- a/tests/vendor/esp-idf/run.py +++ b/tests/vendor/esp-idf/run.py @@ -74,6 +74,7 @@ "esp32_hello_world": "examples/get-started/hello_world", "esp32_blink": "examples/get-started/blink", "esp32_ledc_basic": "examples/peripherals/ledc/ledc_basic", + "esp32_i2c_eeprom": "examples/peripherals/i2c/i2c_eeprom", } # the target an example is built for, when not the ESP32-C3 (its board in # examples//project.json), and the toolchain that target needs @@ -81,6 +82,7 @@ "esp32_hello_world": "esp32", "esp32_blink": "esp32", "esp32_ledc_basic": "esp32", + "esp32_i2c_eeprom": "esp32", } TOOLCHAINS = {"esp32c3": "riscv32-esp-elf-gcc", "esp32": "xtensa-esp32-elf-gcc"} # examples built only for another's project (with examples//'s From e290d3f45127033ea09d0c20175e4a08799d4958 Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 04:15:06 +0000 Subject: [PATCH 08/16] ESP32: the catalog checks pass tools/validate.py rejected the ESP32's description: the schema had no xtensa backend and capped a port at 32 pins (the ESP32's GPIO bank has 40), Espressif's SVD lists fields that overlap (a whole-register STATUS beside its parts, two names for one bit), there was no gcc-xtensa toolchain profile, and the fidelity's validation entries were prose. svd2regs.py gains --resolve-overlaps (a field containing another taken out, of fields over the same bits the first kept, recorded in source); the ESP32's register file is regenerated with it, WIFI_CLK_EN kept as one field and the SVD's stray fields in CPUSDIO_INT1 and SAR_MEAS_WAIT2 reserved. The board and the MCU have their French text. --- catalog/boards/esp32_devkitc/board.json | 24 +- catalog/mcus/espressif/esp32/mcu.json | 48 +++- catalog/mcus/espressif/esp32/registers.json | 288 +------------------- catalog/toolchains/gcc-xtensa.json | 69 +++++ schemas/mcu.schema.json | 4 +- tools/importers/svd2regs.py | 44 ++- tools/test_svd2regs.py | 15 + 7 files changed, 195 insertions(+), 297 deletions(-) create mode 100644 catalog/toolchains/gcc-xtensa.json diff --git a/catalog/boards/esp32_devkitc/board.json b/catalog/boards/esp32_devkitc/board.json index d98c1ccf4..8f7c7d7b7 100644 --- a/catalog/boards/esp32_devkitc/board.json +++ b/catalog/boards/esp32_devkitc/board.json @@ -538,5 +538,25 @@ }, "tests": [ "tests/*.json" - ] -} \ No newline at end of file + ], + "i18n": { + "fr": { + "source": "6536a91c8d63", + "description": "L'ESP32-DevKitC V4 d'Espressif avec un module ESP32-WROOM-32E (l'ESP32-D0WD-V3 avec son quartz de 40 MHz et 4 Mo de flash), le régulateur AMS1117-3.3 qui fait 3,3 V à partir des 5 V du micro-USB à travers une Schottky BAT760, la LED rouge d'alimentation, le bouton Boot sur GPIO0, le bouton EN sur CHIP_PU avec son RC, et deux connecteurs de 19 broches. Le pont USB-UART CP2102N sur UART0 (GPIO1/GPIO3) est la console série de la session, et un port série sur l'hôte (embsim serve --serial). Le firmware est une image de flash (bin), telle qu'idf.py et esptool l'écrivent.", + "fidelity": { + "functional": { + "claims": "Les nets, les ports, la LED d'alimentation et les deux boutons comme composants ; l'ESP32 exécute son firmware depuis l'image de flash (voir sa description) : la ROM d'Espressif, le bootloader de second niveau et l'application, comme sur la carte. EN tire CHIP_PU à l'état bas et la puce redémarre avec rst:0x1 (POWERON_RESET) ; Boot maintenu pendant ce temps fait attendre la ROM en mode téléchargement. Le port du CP2102N est la console de la session sur UART0 (GPIO1/GPIO3) et un port série sur l'hôte.", + "omissions": [ + "le CP2102N lui-même : son énumération USB, ses lignes modem et donc le circuit de programmation automatique (Q1, Q2 et R21, R22 qui laissent les DTR et RTS d'esptool piloter EN et GPIO0) : appuyer sur Boot et EN fait ce qu'ils font", + "les diodes ESD des lignes USB (LESD5D5.0CT1G) et le connecteur USB", + "les broches de flash GPIO6-11 sur les connecteurs (D0-D3, CMD, CLK) : le module les garde pour sa flash et les ports les omettent", + "le dessin de la carte et le modèle du banc" + ] + }, + "electrical": { + "claims": "Le chemin d'alimentation du schéma : VBUS à travers la Schottky vers 5 V, l'AMS1117-3.3 vers 3,3 V, la LED, le RC de EN." + } + } + } + } +} diff --git a/catalog/mcus/espressif/esp32/mcu.json b/catalog/mcus/espressif/esp32/mcu.json index 1bdc0f9b9..d28ecda12 100644 --- a/catalog/mcus/espressif/esp32/mcu.json +++ b/catalog/mcus/espressif/esp32/mcu.json @@ -267,7 +267,7 @@ }, "fidelity": { "functional": { - "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), I2C0 and I2C1 (master and slave on the open-drain lines through the matrix, the 16 commands with RSTART, WRITE, READ, STOP and END, the bus timing in APB_CLK cycles, ACK checks, arbitration, the SCL timeout, the 32-byte FIFOs through DATA and its AHB view, 7- and 10-bit slave addresses; ESP-IDF's i2c_eeprom runs on a 24LC256), PERIP_RST_EN's resets of I2C0, I2C1 and LEDC, the internal analog I2C master, the random number generator and the peripherals' AHB view.", + "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), I2C0 and I2C1 (master and slave on the open-drain lines through the matrix, the 16 commands with RSTART, WRITE, READ, STOP and END, the bus timing in APB_CLK cycles, ACK checks, arbitration, the SCL timeout, the 32-byte FIFOs through DATA and its AHB view, 7- and 10-bit slave addresses; ESP-IDF's i2c_eeprom runs on a 24LC256), PERIP_RST_EN's resets of I2C0, I2C1 and LEDC, the internal analog I2C master, the random number generator and the peripherals' AHB view. The evidence: test_lx6.c's programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16) and the APP_CPU's ROM data kept apart; ESP-IDF v5.4's hello_world, blink, ledc_basic and i2c_eeprom built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart; the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin.", "omissions": [ "Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written)", "the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept", @@ -278,9 +278,12 @@ "the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection" ], "validation": [ - "tests/unit/test_lx6.c: programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16), and the APP_CPU's ROM data kept apart", - "tests/vendor/esp-idf: ESP-IDF v5.4's hello_world, blink and ledc_basic built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart", - "the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin" + "repo:tests/unit/test_lx6.c", + "repo:tests/vendor/esp-idf/run.py", + "repo:tests/vendor/esp-idf/examples/esp32_hello_world/scenario.json", + "repo:tests/vendor/esp-idf/examples/esp32_blink/scenario.json", + "repo:tests/vendor/esp-idf/examples/esp32_ledc_basic/scenario.json", + "repo:tests/vendor/esp-idf/examples/esp32_i2c_eeprom/scenario.json" ] }, "timed": { @@ -383,5 +386,40 @@ ], "packages": { "wroom32e": "wroom32e.json" + }, + "i18n": { + "fr": { + "source": "40e3065d4198", + "description": "Espressif ESP32 (ESP32-D0WD-V3, révision de puce v3.1) : deux cœurs Xtensa LX6 jusqu'à 240 MHz, 520 Kio de SRAM, 448 Kio de ROM, 16 Kio de mémoire RTC, une flash SPI externe derrière les caches des cœurs, Wi-Fi et Bluetooth ; le MCU de l'ESP32-DevKitC. La ROM d'Espressif, le bootloader de second niveau d'ESP-IDF et les applications ESP-IDF tournent sur les deux cœurs ; les radios ne sont pas encore modélisées.", + "fidelity": { + "functional": { + "claims": "Les deux cœurs Xtensa LX6 (mcu/xtensa/lx6.c, lx6fp.c) tels que les configure le core-isa.h d'Espressif : les instructions de base et de densité, les registres fenêtrés (64, le contrôle de débordement de chaque instruction, CALL4/8/12, ENTRY, RETW et son sous-débordement, MOVSP, ROTW, L32E/S32E), les boucles sans surcoût, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, les booléens, S32C1I avec SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), le paquet MAC16, la FPU simple précision (modes d'arrondi et drapeaux IEEE ; les séquences de division et de racine carrée qu'exécute libgcc donnent des résultats correctement arrondis), les exceptions XEA2 avec vecteurs relocalisables, 32 interruptions aux niveaux et types de core-isa.h (niveau, front, logicielles, les temporisateurs CCOMPARE0-2 contre CCOUNT, NMI), RSIL, WAITI, RFI, BREAK, IBREAK, DBREAK et ICOUNT de l'option de débogage, la protection par régions (huit régions de 512 Mo, 15 sans accès), les chargements et écritures non alignés, et les accès de données en 32 bits seulement du bus d'instructions. Les deux cœurs partagent la machine, l'APP_CPU maintenu en reset jusqu'à ce que DPORT le libère et voyant la ROM avec ses pointeurs vers les données ROM du PRO_CPU déplacés vers les siennes, comme dans l'image ROM APP_CPU d'Espressif. Le démarrage : la ROM d'Espressif (esp32_rev300_rom.elf, révision v3) depuis le vecteur de reset, sa bannière, les broches de configuration (GPIO_STRAP : SPI_FAST_FLASH_BOOT, ou le mode téléchargement avec GPIO0 bas), les causes de reset (RTC_CNTL), le contrôle anti-glitch de l'eFuse, la lecture de la flash par SPI1, le bootloader de second niveau d'ESP-IDF et sa vérification d'image sur l'accélérateur SHA, la MMU flash des caches, et l'application sur les deux cœurs. Les modèles : DPORT (reset, horloge et blocage de l'APP_CPU, CPU_PER_CONF, vidage et état des caches, tables de la MMU flash, les 69 sources de la matrice d'interruptions, les interruptions inter-CPU), RTC_CNTL (causes de reset, le temporisateur RTC, le chien de garde RTC avec sa protection au démarrage sur flash, les resets et blocages logiciels, les registres de stockage, SOC_CLK_SEL), APB_CTRL (les horloges CPU et APB depuis XTAL, PLL ou RC_FAST), le contrôleur eFuse avec les bits d'usine de la puce (ESP32-D0WD-V3 v3.1, une MAC avec son CRC, ou celle des réglages de la carte), GPIO et IO_MUX (40 plots, la matrice, tirages, drain ouvert, interruptions sur chaque CPU, le verrou de configuration), UART0-2 (FIFO, trames au débit, interruptions), TIMG0/1 (T0, T1, le temporisateur LAC, le MWDT avec sa protection au démarrage sur flash, la calibration de RTC_SLOW_CLK), SPI0/SPI1 avec la flash Giantec GT25Q32A du module (C4 60 16, l'identifiant que rapporte la carte du propriétaire), l'accélérateur SHA (SHA-1, -256, -384, -512), LEDC (huit canaux MLI rapides et huit lents sur huit temporisateurs, le fondu, sur ledc_hs/ls_sig_out de la matrice), I2C0 et I2C1 (maître et esclave sur les lignes à drain ouvert à travers la matrice, les 16 commandes avec RSTART, WRITE, READ, STOP et END, le timing du bus en cycles d'APB_CLK, les contrôles d'ACK, l'arbitrage, le délai d'attente sur SCL, les FIFO de 32 octets par DATA et sa vue AHB, les adresses esclaves sur 7 et 10 bits ; l'exemple i2c_eeprom d'ESP-IDF fonctionne avec une 24LC256), les resets de PERIP_RST_EN pour I2C0, I2C1 et LEDC, le maître I2C analogique interne, le générateur de nombres aléatoires et la vue AHB des périphériques. Les preuves : les programmes de test_lx6.c assemblés par l'assembleur d'Espressif (entiers, décalages, multiplication et division, boucles, branchements, mémoire avec S32C1I, récursion fenêtrée à travers les vecteurs de fenêtre de la ROM, SYSCALL, l'interruption du temporisateur CCOMPARE, FPU, MAC16) et les données ROM de l'APP_CPU tenues à part ; hello_world, blink, ledc_basic et i2c_eeprom d'ESP-IDF v5.4 compilés sans modification pour la cible esp32 sur l'ESP32-DevKitC V4, de la bannière de la ROM jusqu'à esp_restart ; l'image ROM est identique octet pour octet à l'esp32-v3-rom.bin du QEMU d'Espressif, et la vue qu'en a l'APP_CPU à son esp32-v3-rom-app.bin.", + "omissions": [ + "le Wi-Fi, le Bluetooth et l'étage RF (WIFI_MAC, BB, NRX, FE : leurs registres gardent ce qui y est écrit)", + "les instructions de l'accélérateur double précision (F64ADDC, F64ITER et les autres : leurs encodages sont publics, pas ce qu'elles font ; un programme qui en exécute une s'arrête avec un diagnostic), bien que ses registres soient conservés", + "la PSRAM (DRAM1), le remappage de démarrage, les permissions d'accès APB/AHB, les régions verrouillées et le timing des caches (les pages mappées sont lues entières), les interruptions d'erreur d'accès de la MMU", + "I2C : le mode hors FIFO (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, les filtres d'entrée (seulement leur part du temps haut de SCL), le contrôle R/W de l'adressage sur 10 bits", + "les périphériques sans modèle pour l'instant : I2S0/1, SPI2/3 (HSPI, VSPI), RMT, MCPWM, PCNT, TWAI, SDMMC, EMAC, les ADC SAR, les DAC, le capteur tactile, l'IO MUX RTC et le coprocesseur ULP, les accélérateurs AES et RSA, le chiffrement de la flash", + "les modes de veille (veille légère et profonde, les domaines d'alimentation), la détection de baisse de tension", + "le contrôle du schéma de codage 3/4 de l'eFuse, la protection en écriture par champ du BLOCK0" + ] + }, + "timed": { + "claims": "Timing des instructions estimé : un cycle, trois pour un branchement pris, un saut, un appel ou un retour, deux pour MULL, douze pour une division, trois pour l'entrée d'une exception ; CCOUNT compte ces cycles. Les horloges suivent les registres : CPU_CLK depuis XTAL (40 MHz en sortie de reset), les 80, 160 ou 240 MHz de la PLL, ou RC_FAST ; APB_CLK ; RTC_SLOW_CLK aux 150 kHz nominaux de l'oscillateur RC.", + "omissions": [ + "les verrouillages du pipeline LX6 et le timing du tampon de boucle", + "les défauts de cache et la latence de la flash (le temps de bus des transferts SPI est compté sur SPI1, ainsi que les temps de programmation et d'effacement de la flash)", + "l'erreur et la dérive des oscillateurs RC" + ] + }, + "electrical": { + "claims": "Valeurs par défaut du modèle de broche GPIO à 3,3 V d'après les caractéristiques DC de la fiche technique : VIH 0,75 VDD, VIL 0,25 VDD, VOH 0,8 VDD, VOL 0,1 VDD, tirages de 45 kOhm ; GPIO34-39 en entrée seulement. Le courant d'alimentation (ADR-036, modes d'alimentation de la fiche technique v5.3) : les cœurs actifs et en attente à leur horloge, et maintenus éteints.", + "omissions": [ + "l'effet de la force de sortie des plots", + "le courant propre de chaque périphérique (la fiche technique donne les modes, pas les parties)" + ] + } + } + } } -} \ No newline at end of file +} diff --git a/catalog/mcus/espressif/esp32/registers.json b/catalog/mcus/espressif/esp32/registers.json index 7287b6ae6..eca92b1ef 100644 --- a/catalog/mcus/espressif/esp32/registers.json +++ b/catalog/mcus/espressif/esp32/registers.json @@ -4,7 +4,7 @@ "id": "espressif/esp32/registers", "version": "1.0.0", "device": "ESP32", - "source": "converted from esp32.svd by tools/importers/svd2regs.py; peripherals left out: RNG (the random number generator's one register (RNG_DATA, TRM 26), which the SVD puts at the AHB address 0x60035144; the chip's model answers at 0x3FF75144 and its AHB alias (misc.c))", + "source": "converted from esp32.svd by tools/importers/svd2regs.py; peripherals left out: RNG (the random number generator's one register (RNG_DATA, TRM 26), which the SVD puts at the AHB address 0x60035144; the chip's model answers at 0x3FF75144 and its AHB alias (misc.c)); fields corrected from the reference manual: DPORT.WIFI_CLK_EN.WIFI_CLK_EN:0:32; fields reserved by the reference manual taken out: GPIO.CPUSDIO_INT1.PIN_PAD_DRIVER, GPIO.CPUSDIO_INT1.PIN_INT_TYPE, GPIO.CPUSDIO_INT1.PIN_WAKEUP_ENABLE, GPIO.CPUSDIO_INT1.PIN_CONFIG, GPIO.CPUSDIO_INT1.PIN_INT_ENA, SENS.SAR_MEAS_WAIT2.FORCE_XPD_SAR_SW; overlapping fields taken out: DPORT.PRO_DCACHE_DBUG0 (PRO_CACHE_MMU_IA), DPORT.PRO_DCACHE_DBUG3 (PRO_CPU_DISABLED_CACHE_IA), DPORT.APP_DCACHE_DBUG0 (APP_CACHE_MMU_IA), DPORT.APP_DCACHE_DBUG3 (APP_CPU_DISABLED_CACHE_IA), DPORT.PRO_CPU_RECORD_PDEBUGINST (RECORD_PRO_PDEBUGINST), DPORT.PRO_CPU_RECORD_PDEBUGSTATUS (RECORD_PRO_PDEBUGSTATUS, RECORD_PDEBUGSTATUS_INSNTYPE), DPORT.PRO_CPU_RECORD_PDEBUGDATA (RECORD_PRO_PDEBUGDATA, RECORD_PDEBUGDATA_EXCVEC, RECORD_PDEBUGDATA_INSNTYPE_SR, RECORD_PDEBUGDATA_INSNTYPE_RER, RECORD_PDEBUGDATA_INSNTYPE_WER, RECORD_PDEBUGDATA_INSNTYPE_ER, RECORD_PDEBUGDATA_STALL_IPIF, RECORD_PDEBUGDATA_INSNTYPE_RSR, RECORD_PDEBUGDATA_INSNTYPE_WSR, RECORD_PDEBUGDATA_INSNTYPE_XSR, RECORD_PDEBUGDATA_STALL_BPIFETCH, RECORD_PDEBUGDATA_EXCCAUSE, RECORD_PDEBUGDATA_STALL_BANKCONFL), DPORT.PRO_CPU_RECORD_PDEBUGLS0STAT (RECORD_PRO_PDEBUGLS0STAT), DPORT.CACHE_IA_INT_EN (CACHE_IA_INT_EN), UART0.MEM_RX_STATUS (MEM_RX_STATUS), RTC_CNTL.LOW_POWER_ST (LOW_POWER_DIAG0), RTC_CNTL.BROWN_OUT (RTC_MEM_CRC_ADDR, RTC_MEM_CRC_LEN, RTC_MEM_CRC_FINISH), RMT.CH0STATUS (STATUS), RMT.CH1STATUS (STATUS), RMT.CH2STATUS (STATUS), RMT.CH3STATUS (STATUS), RMT.CH4STATUS (STATUS), RMT.CH5STATUS (STATUS), RMT.CH6STATUS (STATUS), RMT.CH7STATUS (STATUS), PCNT.U0_STATUS (CORE_STATUS_U0), PCNT.U1_STATUS (CORE_STATUS_U0), PCNT.U2_STATUS (CORE_STATUS_U0), PCNT.U3_STATUS (CORE_STATUS_U0), PCNT.U4_STATUS (CORE_STATUS_U0), PCNT.U5_STATUS (CORE_STATUS_U0), PCNT.U6_STATUS (CORE_STATUS_U0), PCNT.U7_STATUS (CORE_STATUS_U0)", "interrupts": { "WIFI_MAC": 0, "WIFI_NMI": 1, @@ -1404,21 +1404,6 @@ "WIFI_CLK_EN", 0, 32 - ], - [ - "WIFI_CLK_WIFI_EN", - 0, - 3 - ], - [ - "WIFI_CLK_WIFI_BT_COMMON", - 0, - 6 - ], - [ - "WIFI_CLK_BT_EN", - 11, - 3 ] ] }, @@ -3887,12 +3872,6 @@ 0, 1 ], - [ - "PRO_CACHE_MMU_IA", - 0, - 1, - "r" - ], [ "PRO_CACHE_IA", 1, @@ -3971,12 +3950,6 @@ 9, "r" ], - [ - "PRO_CPU_DISABLED_CACHE_IA", - 9, - 6, - "r" - ], [ "PRO_CPU_DISABLED_CACHE_IA_OPPOSITE", 9, @@ -4096,12 +4069,6 @@ 0, 1 ], - [ - "APP_CACHE_MMU_IA", - 0, - 1, - "r" - ], [ "APP_CACHE_IA", 1, @@ -4180,12 +4147,6 @@ 9, "r" ], - [ - "APP_CPU_DISABLED_CACHE_IA", - 9, - 6, - "r" - ], [ "APP_CPU_DISABLED_CACHE_IA_OPPOSITE", 9, @@ -4346,12 +4307,6 @@ "name": "PRO_CPU_RECORD_PDEBUGINST", "offset": "0x44C", "fields": [ - [ - "RECORD_PRO_PDEBUGINST", - 0, - 32, - "r" - ], [ "RECORD_PDEBUGINST_SZ", 0, @@ -4383,21 +4338,10 @@ "name": "PRO_CPU_RECORD_PDEBUGSTATUS", "offset": "0x450", "fields": [ - [ - "RECORD_PRO_PDEBUGSTATUS", - 0, - 8, - "r" - ], [ "RECORD_PDEBUGSTATUS_BBCAUSE", 0, 6 - ], - [ - "RECORD_PDEBUGSTATUS_INSNTYPE", - 0, - 6 ] ] }, @@ -4405,52 +4349,21 @@ "name": "PRO_CPU_RECORD_PDEBUGDATA", "offset": "0x454", "fields": [ - [ - "RECORD_PRO_PDEBUGDATA", - 0, - 32, - "r" - ], [ "RECORD_PDEBUGDATA_DEP_OTHER", 0, 1 ], - [ - "RECORD_PDEBUGDATA_EXCVEC", - 0, - 5 - ], - [ - "RECORD_PDEBUGDATA_INSNTYPE_SR", - 0, - 8 - ], - [ - "RECORD_PDEBUGDATA_INSNTYPE_RER", - 0, - 1 - ], [ "RECORD_PDEBUGDATA_STALL_BUFF", 1, 1 ], - [ - "RECORD_PDEBUGDATA_INSNTYPE_WER", - 1, - 1 - ], [ "RECORD_PDEBUGDATA_STALL_BUFFCONFL", 2, 1 ], - [ - "RECORD_PDEBUGDATA_INSNTYPE_ER", - 2, - 12 - ], [ "RECORD_PDEBUGDATA_STALL_DCM", 3, @@ -4476,36 +4389,16 @@ 8, 1 ], - [ - "RECORD_PDEBUGDATA_STALL_IPIF", - 8, - 1 - ], - [ - "RECORD_PDEBUGDATA_INSNTYPE_RSR", - 8, - 1 - ], [ "RECORD_PDEBUGDATA_STALL_TIE", 9, 1 ], - [ - "RECORD_PDEBUGDATA_INSNTYPE_WSR", - 9, - 1 - ], [ "RECORD_PDEBUGDATA_STALL_RUN", 10, 1 ], - [ - "RECORD_PDEBUGDATA_INSNTYPE_XSR", - 10, - 1 - ], [ "RECORD_PDEBUGDATA_DEP_STR", 11, @@ -4516,11 +4409,6 @@ 12, 1 ], - [ - "RECORD_PDEBUGDATA_STALL_BPIFETCH", - 12, - 1 - ], [ "RECORD_PDEBUGDATA_STALL_L32R", 13, @@ -4541,16 +4429,6 @@ 16, 1 ], - [ - "RECORD_PDEBUGDATA_EXCCAUSE", - 16, - 6 - ], - [ - "RECORD_PDEBUGDATA_STALL_BANKCONFL", - 16, - 1 - ], [ "RECORD_PDEBUGDATA_DEP_HALT", 17, @@ -4584,12 +4462,6 @@ "name": "PRO_CPU_RECORD_PDEBUGLS0STAT", "offset": "0x45C", "fields": [ - [ - "RECORD_PRO_PDEBUGLS0STAT", - 0, - 32, - "r" - ], [ "RECORD_PDEBUGLS0STAT_TYPE", 0, @@ -5626,11 +5498,6 @@ "name": "CACHE_IA_INT_EN", "offset": "0x5A0", "fields": [ - [ - "CACHE_IA_INT_EN", - 0, - 28 - ], [ "CACHE_IA_INT_APP_DROM0", 0, @@ -8168,12 +8035,6 @@ "name": "MEM_RX_STATUS", "offset": "0x60", "fields": [ - [ - "MEM_RX_STATUS", - 0, - 24, - "r" - ], [ "MEM_RX_RD_ADDR", 2, @@ -10339,31 +10200,6 @@ 0, 8, "r" - ], - [ - "PIN_PAD_DRIVER", - 2, - 1 - ], - [ - "PIN_INT_TYPE", - 7, - 3 - ], - [ - "PIN_WAKEUP_ENABLE", - 10, - 1 - ], - [ - "PIN_CONFIG", - 11, - 2 - ], - [ - "PIN_INT_ENA", - 13, - 5 ] ] }, @@ -20164,12 +20000,6 @@ "name": "LOW_POWER_ST", "offset": "0xC0", "fields": [ - [ - "LOW_POWER_DIAG0", - 0, - 32, - "r" - ], [ "RDY_FOR_WAKEUP", 19, @@ -20330,11 +20160,6 @@ 8, 1 ], - [ - "RTC_MEM_CRC_ADDR", - 9, - 11 - ], [ "CLOSE_FLASH_ENA", 14, @@ -20350,11 +20175,6 @@ 16, 10 ], - [ - "RTC_MEM_CRC_LEN", - 20, - 11 - ], [ "RST_ENA", 26, @@ -20375,11 +20195,6 @@ 31, 1, "r" - ], - [ - "RTC_MEM_CRC_FINISH", - 31, - 1 ] ] }, @@ -22311,11 +22126,6 @@ "offset": "0x0C", "reset": "0x0020000A", "fields": [ - [ - "FORCE_XPD_SAR_SW", - 0, - 1 - ], [ "SAR_AMP_WAIT3", 0, @@ -33935,12 +33745,6 @@ "name": "CH0STATUS", "offset": "0x60", "fields": [ - [ - "STATUS", - 0, - 32, - "r" - ], [ "MEM_WADDR_EX", 0, @@ -33995,12 +33799,6 @@ "name": "CH1STATUS", "offset": "0x64", "fields": [ - [ - "STATUS", - 0, - 32, - "r" - ], [ "MEM_WADDR_EX", 0, @@ -34055,12 +33853,6 @@ "name": "CH2STATUS", "offset": "0x68", "fields": [ - [ - "STATUS", - 0, - 32, - "r" - ], [ "MEM_WADDR_EX", 0, @@ -34115,12 +33907,6 @@ "name": "CH3STATUS", "offset": "0x6C", "fields": [ - [ - "STATUS", - 0, - 32, - "r" - ], [ "MEM_WADDR_EX", 0, @@ -34175,12 +33961,6 @@ "name": "CH4STATUS", "offset": "0x70", "fields": [ - [ - "STATUS", - 0, - 32, - "r" - ], [ "MEM_WADDR_EX", 0, @@ -34235,12 +34015,6 @@ "name": "CH5STATUS", "offset": "0x74", "fields": [ - [ - "STATUS", - 0, - 32, - "r" - ], [ "MEM_WADDR_EX", 0, @@ -34295,12 +34069,6 @@ "name": "CH6STATUS", "offset": "0x78", "fields": [ - [ - "STATUS", - 0, - 32, - "r" - ], [ "MEM_WADDR_EX", 0, @@ -34355,12 +34123,6 @@ "name": "CH7STATUS", "offset": "0x7C", "fields": [ - [ - "STATUS", - 0, - 32, - "r" - ], [ "MEM_WADDR_EX", 0, @@ -36756,12 +36518,6 @@ "name": "U0_STATUS", "offset": "0x90", "fields": [ - [ - "CORE_STATUS_U0", - 0, - 32, - "r" - ], [ "ZERO_MODE", 0, @@ -36798,12 +36554,6 @@ "name": "U1_STATUS", "offset": "0x94", "fields": [ - [ - "CORE_STATUS_U0", - 0, - 32, - "r" - ], [ "ZERO_MODE", 0, @@ -36840,12 +36590,6 @@ "name": "U2_STATUS", "offset": "0x98", "fields": [ - [ - "CORE_STATUS_U0", - 0, - 32, - "r" - ], [ "ZERO_MODE", 0, @@ -36882,12 +36626,6 @@ "name": "U3_STATUS", "offset": "0x9C", "fields": [ - [ - "CORE_STATUS_U0", - 0, - 32, - "r" - ], [ "ZERO_MODE", 0, @@ -36924,12 +36662,6 @@ "name": "U4_STATUS", "offset": "0xA0", "fields": [ - [ - "CORE_STATUS_U0", - 0, - 32, - "r" - ], [ "ZERO_MODE", 0, @@ -36966,12 +36698,6 @@ "name": "U5_STATUS", "offset": "0xA4", "fields": [ - [ - "CORE_STATUS_U0", - 0, - 32, - "r" - ], [ "ZERO_MODE", 0, @@ -37008,12 +36734,6 @@ "name": "U6_STATUS", "offset": "0xA8", "fields": [ - [ - "CORE_STATUS_U0", - 0, - 32, - "r" - ], [ "ZERO_MODE", 0, @@ -37050,12 +36770,6 @@ "name": "U7_STATUS", "offset": "0xAC", "fields": [ - [ - "CORE_STATUS_U0", - 0, - 32, - "r" - ], [ "ZERO_MODE", 0, diff --git a/catalog/toolchains/gcc-xtensa.json b/catalog/toolchains/gcc-xtensa.json new file mode 100644 index 000000000..ad69dd7f4 --- /dev/null +++ b/catalog/toolchains/gcc-xtensa.json @@ -0,0 +1,69 @@ +{ + "schema_version": 1, + "kind": "toolchain", + "id": "gcc-xtensa", + "name": "Espressif's GNU Xtensa toolchain (xtensa-esp32-elf-gcc)", + "description": "Espressif's crosstool-NG GCC for the ESP32's Xtensa LX6 cores, the one ESP-IDF installs (idf_tools.py, ~/.espressif/tools/xtensa-esp-elf): xtensa-esp32-elf-gcc is the ESP32's configuration (core-isa.h's), with newlib. ESP-IDF's own build (idf.py) makes the flash images the vendor scenarios run; this profile compiles a project's sources into an ELF.", + "detect": { + "command": [ + "xtensa-esp32-elf-gcc", + "--version" + ], + "version_regex": "\\) ([0-9.]+)", + "min_version": "12.2", + "prefix": "xtensa-esp32-elf-" + }, + "targets": { + "esp32": { + "cc": [ + "xtensa-esp32-elf-gcc", + "-mlongcalls" + ], + "link_flags": [ + "-nostartfiles", + "-Wl,--gc-sections", + "--specs=nosys.specs" + ] + } + }, + "steps": { + "compile": [ + "${cc}", + "${cflags}", + "${defines}", + "${include}", + "-g", + "-O2", + "-ffunction-sections", + "-fdata-sections", + "-Wall", + "-c", + "${source}", + "-o", + "${object}" + ], + "link": [ + "${cc}", + "${cflags}", + "${link_flags}", + "-T${linker_script}", + "-Wl,-Map=${map}", + "${objects}", + "-o", + "${image}" + ], + "convert": null + }, + "outputs": { + "image": "elf", + "debug": "dwarf", + "map": true + }, + "environment": { + "PATH_hint": [ + "~/.espressif/tools/xtensa-esp-elf/*/xtensa-esp-elf/bin", + "C:/Espressif/tools/xtensa-esp-elf/*/xtensa-esp-elf/bin", + "/opt/esp/tools/xtensa-esp-elf/*/xtensa-esp-elf/bin" + ] + } +} diff --git a/schemas/mcu.schema.json b/schemas/mcu.schema.json index 2105fc1cb..ca9562da9 100644 --- a/schemas/mcu.schema.json +++ b/schemas/mcu.schema.json @@ -27,7 +27,7 @@ "required": ["backend", "model"], "additionalProperties": false, "properties": { - "backend": {"type": "string", "enum": ["cortex-m", "riscv", "avr", "mips", "pic32", "pic24", "pic16"]}, + "backend": {"type": "string", "enum": ["cortex-m", "riscv", "avr", "mips", "pic32", "pic24", "pic16", "xtensa"]}, "model": {"type": "string", "minLength": 1}, "priority_bits": {"type": "integer", "minimum": 0, "maximum": 8}, "pmp_entries": {"type": "integer", "minimum": 0, "maximum": 64, "description": "A RISC-V core's physical memory protection entries (16 when absent); pmpcfg and pmpaddr past them read 0"}, @@ -209,7 +209,7 @@ "additionalProperties": false, "properties": { "name": {"type": "string", "pattern": "^[A-Z][A-Z0-9]*$"}, - "pins": {"type": "integer", "minimum": 1, "maximum": 32}, + "pins": {"type": "integer", "minimum": 1, "maximum": 64, "description": "Pins in the port: up to 32 for most parts, more where one bank is wider (the ESP32's 40 GPIOs, GPIO_OUT and OUT1)."}, "mask": {"$ref": "common.schema.json#/$defs/hex_or_size", "description": "Bit mask of implemented pins when not contiguous from 0."} } } diff --git a/tools/importers/svd2regs.py b/tools/importers/svd2regs.py index 24c437dac..1585941c2 100644 --- a/tools/importers/svd2regs.py +++ b/tools/importers/svd2regs.py @@ -40,7 +40,15 @@ (repeatable) a memory inside a peripheral the SVD leaves out, as WORDS 32-bit registers NAME0, NAME1, ... (the ESP32-C3's - RMT RAM); recorded likewise""" + RMT RAM); recorded likewise + --resolve-overlaps fields that share bits, which some SVDs + list as alternative views of one register + (Espressif's: a whole-register STATUS + beside its parts): a field containing + another is taken out, and of fields over + the same bits the first is kept; recorded + likewise (after --reserve, so a wrong + field can be taken out first)""" import argparse import json import re @@ -308,6 +316,36 @@ def apply_reserved(doc: dict, specs: list[str]) -> None: doc["source"] += "; fields reserved by the reference manual taken out: " + ", ".join(done) +def resolve_overlaps(doc: dict) -> None: + """In each register, fields that contain another taken out, and of + fields over the same bits all but the first.""" + done = [] + for p in doc["peripherals"]: + for r in p.get("registers", []): + fields = r.get("fields", []) + masks = [((1 << f[2]) - 1) << f[1] for f in fields] + out = set() + for i, mi in enumerate(masks): + for j, mj in enumerate(masks): + if i == j or j in out: + continue + if mi == mj and j < i: + out.add(i) # the same bits: the first kept + elif mi != mj and mi & mj == mj: + out.add(i) # i contains j + kept = [f for k, f in enumerate(fields) if k not in out] + masks = [((1 << f[2]) - 1) << f[1] for f in kept] + if any(masks[a] & masks[b] for a in range(len(masks)) for b in range(a + 1, len(masks))): + raise SystemExit(f"--resolve-overlaps: {p['name']}.{r['name']}: fields still overlap; " + "take the wrong one out with --reserve") + if not out: + continue + r["fields"] = kept + done.append(f"{p['name']}.{r['name']} ({', '.join(fields[k][0] for k in sorted(out))})") + if done: + doc["source"] += "; overlapping fields taken out: " + ", ".join(done) + + def apply_merges(doc: dict, specs: list[str]) -> None: """The one-bit fields NAME0..NAMEn, contiguous, joined into NAME.""" done = [] @@ -412,6 +450,8 @@ def main(argv: Optional[list[str]] = None) -> int: help="one-bit fields NAME0..NAMEn joined into NAME") ap.add_argument("--reserve", action="append", default=[], metavar="PERIPH.REG.NAME", help="a field whose bits the reference manual reserves, taken out") + ap.add_argument("--resolve-overlaps", action="store_true", + help="fields containing another, or repeating its bits, taken out") args = ap.parse_args(argv) doc = convert(args.svd, args.id or (args.svd.stem.lower() + "/registers")) apply_drops(doc, args.drop) @@ -421,6 +461,8 @@ def main(argv: Optional[list[str]] = None) -> int: apply_registers(doc, args.register) apply_fields(doc, args.field) apply_reserved(doc, args.reserve) + if args.resolve_overlaps: + resolve_overlaps(doc) apply_resets(doc, args.reset) apply_interrupts(doc, args.interrupts) args.output.write_text(json.dumps(doc, indent=1) + "\n", encoding="utf-8") diff --git a/tools/test_svd2regs.py b/tools/test_svd2regs.py index 7c78471f7..bc9145c98 100644 --- a/tools/test_svd2regs.py +++ b/tools/test_svd2regs.py @@ -111,6 +111,21 @@ def test_reserved_field(self): with self.assertRaises(SystemExit): svd2regs.apply_reserved(doc, ["TIM3.CNT.CNT_H"]) + def test_resolve_overlaps(self): + def doc_of(fields): + return {"source": "s", "interrupts": {}, "peripherals": [{"name": "PCNT", "base": "0x0", "registers": [ + {"name": "U0_STATUS", "offset": "0x90", "fields": fields}]}]} + # a whole-register view beside its parts, and two names for one bit + doc = doc_of([["CORE_STATUS_U0", 0, 32, "r"], ["ZERO_MODE", 0, 2, "r"], ["THRES1", 2, 1, "r"], + ["DET", 31, 1, "r"], ["FINISH", 31, 1, "r"]]) + svd2regs.resolve_overlaps(doc) + self.assertEqual([f[0] for f in doc["peripherals"][0]["registers"][0]["fields"]], + ["ZERO_MODE", "THRES1", "DET"]) + self.assertIn("PCNT.U0_STATUS (CORE_STATUS_U0, FINISH)", doc["source"]) + # a partial overlap is left to --reserve + with self.assertRaises(SystemExit): + svd2regs.resolve_overlaps(doc_of([["A", 0, 4], ["B", 2, 4]])) + def test_added_register(self): doc = {"source": "s", "interrupts": {}, "peripherals": [{"name": "SYSCFG", "base": "0x0", "registers": [ {"name": "CMPCR", "offset": "0x20", "fields": []}]}]} From 7585110e56c79f25fea7189b07e1ea67bae06308 Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 04:26:30 +0000 Subject: [PATCH 09/16] Gallery: the ESP32-DevKitC running ESP-IDF's i2c_eeprom --- docs/gallery/README.md | 9 +++++++++ docs/gallery/esp32-devkitc/design.png | Bin 0 -> 498099 bytes docs/gallery/esp32-devkitc/run.png | Bin 0 -> 469357 bytes 3 files changed, 9 insertions(+) create mode 100644 docs/gallery/esp32-devkitc/design.png create mode 100644 docs/gallery/esp32-devkitc/run.png diff --git a/docs/gallery/README.md b/docs/gallery/README.md index 4b9fd97db..115e2093f 100644 --- a/docs/gallery/README.md +++ b/docs/gallery/README.md @@ -5,6 +5,15 @@ evolves. Newer milestones come first. The milestone sets from M1 on are captured `ui/apps/workbench/scripts/screenshots.mjs` (the same views each time: `pnpm build`, then `node scripts/screenshots.mjs --out ../../../docs/gallery/`). +## The ESP32-DevKitC running ESP-IDF's i2c_eeprom (2026-11-08) + +The original ESP32 on the machine framework: ESP-IDF v5.4's i2c_eeprom, +built unmodified, writing a 24LC256 through I2C0 at 400 kHz and reading it +back (the part's write cycles counted under the meters). + +| ![Design](esp32-devkitc/design.png) | ![Run](esp32-devkitc/run.png) | +|---|---| + ## The library by category and sub-category (2026-11-03) The real catalog's 205 parts filed as an EDA's device picker files them; diff --git a/docs/gallery/esp32-devkitc/design.png b/docs/gallery/esp32-devkitc/design.png new file mode 100644 index 0000000000000000000000000000000000000000..0dddb9b51ff52aea0b3e7a1c82267d44e121e7cc GIT binary patch literal 498099 zcmeFYWmge}6`pe#zX8*r- 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zT!gM=gsrk%=felU+&eY-I_)q>!g}h0!T-M2#Oke(kbvL*SG7hX7NF`N=31#-+Y)#0 z?j2bKu7Eb{+a#&3s`pLdtP;2XVS$d{!y*p&NI?jL>mK>pq??!+-sYLf=H9Scey;C( zY%ix-ud?#D_#V)I8P|9;1)`>pXh<8R3^*&lCF+y_iqSMROO?~C>+#U>f3Vf>)k8v* zfK#vf)n|1rEkh%r@#Lpcdga@d|3Ud?76QHdQYj2=bN6eJM z+4rIogv_36s~7=PW#qa@Xc1@+ysWm||C1!}R5yKr*o7)A%qk4WFp>~y1Y}Mf9kjHB zd8t_^yg^nJMUH>adh^`&O5a5~fQqcF87BXxJoT#g((-A0YBX>{BsTT;A z09^C^_k6r^6l=5S@TT0)G~l1ZwDW~8ogeKA2#B04$8@BrW^7ASfTw;0WY4>n>>uvi zGW_nmxDCMdlr*oP;Es%GYGbm|%E6^yRB(!%;Go3kAjA2;UztPZ|NRTlfT{f_OXmOo z{(mV#{eNQWZvev&$@%#%&nU<+CAoU>RFjh685s19g*E&yezO8p Date: Sun, 8 Nov 2026 04:43:21 +0000 Subject: [PATCH 10/16] ESP32: gptimer, uart_echo and real_time_stats; MEM_RX_STATUS Three more of ESP-IDF's examples run unmodified on the DevKitC: gptimer (TIMG0, 17/17), uart_echo on UART2 (6/6) and real_time_stats across both cores (10/10, with IDLE0 and IDLE1). uart_echo echoed 128 bytes for each line: on the ESP32, ESP-IDF's uart_ll_get_rxfifo_len counts the bytes waiting from MEM_RX_STATUS's read and write addresses (the DPORT read's FIFO count is not to be trusted), and with both at 0 takes a nonzero count for a full FIFO. The UART model now moves the two addresses with each byte. --- CHANGELOG.md | 4 +- catalog/mcus/espressif/esp32/mcu.json | 11 +- core/mcu/esp32/soc/uart.c | 16 +- docs/STATUS.md | 5 +- .../examples/esp32_gptimer/project.json | 61 ++++++++ .../examples/esp32_gptimer/scenario.json | 146 ++++++++++++++++++ .../esp32_real_time_stats/project.json | 61 ++++++++ .../esp32_real_time_stats/scenario.json | 90 +++++++++++ .../examples/esp32_uart_echo/project.json | 91 +++++++++++ .../examples/esp32_uart_echo/scenario.json | 71 +++++++++ tests/vendor/esp-idf/run.py | 6 + 11 files changed, 553 insertions(+), 9 deletions(-) create mode 100644 tests/vendor/esp-idf/examples/esp32_gptimer/project.json create mode 100644 tests/vendor/esp-idf/examples/esp32_gptimer/scenario.json create mode 100644 tests/vendor/esp-idf/examples/esp32_real_time_stats/project.json create mode 100644 tests/vendor/esp-idf/examples/esp32_real_time_stats/scenario.json create mode 100644 tests/vendor/esp-idf/examples/esp32_uart_echo/project.json create mode 100644 tests/vendor/esp-idf/examples/esp32_uart_echo/scenario.json diff --git a/CHANGELOG.md b/CHANGELOG.md index b94e50c75..0e3f4da43 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -27,7 +27,9 @@ versions follow semantic versioning. There is no release yet. - Espressif's ROM, ESP-IDF v5.4's bootloader and hello_world run unmodified through `esp_restart` (`tests/vendor/esp-idf`: `esp32_hello_world` 9/9, `esp32_blink` 6/6, `esp32_ledc_basic` 2/2, `esp32_i2c_eeprom` 3/3 on a - 24LC256); `test_lx6` checks the core with programs from Espressif's assembler. + 24LC256, `esp32_gptimer` 17/17, `esp32_uart_echo` 6/6 on UART2, + `esp32_real_time_stats` 10/10 across both cores; the UARTs keep + MEM_RX_STATUS's addresses, from which ESP-IDF counts the bytes waiting); `test_lx6` checks the core with programs from Espressif's assembler. ### Original ESP32 digital per-pin hold diff --git a/catalog/mcus/espressif/esp32/mcu.json b/catalog/mcus/espressif/esp32/mcu.json index d28ecda12..f8e536095 100644 --- a/catalog/mcus/espressif/esp32/mcu.json +++ b/catalog/mcus/espressif/esp32/mcu.json @@ -267,7 +267,7 @@ }, "fidelity": { "functional": { - "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), I2C0 and I2C1 (master and slave on the open-drain lines through the matrix, the 16 commands with RSTART, WRITE, READ, STOP and END, the bus timing in APB_CLK cycles, ACK checks, arbitration, the SCL timeout, the 32-byte FIFOs through DATA and its AHB view, 7- and 10-bit slave addresses; ESP-IDF's i2c_eeprom runs on a 24LC256), PERIP_RST_EN's resets of I2C0, I2C1 and LEDC, the internal analog I2C master, the random number generator and the peripherals' AHB view. The evidence: test_lx6.c's programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16) and the APP_CPU's ROM data kept apart; ESP-IDF v5.4's hello_world, blink, ledc_basic and i2c_eeprom built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart; the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin.", + "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts, MEM_RX_STATUS's addresses that ESP-IDF counts the bytes waiting from), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), I2C0 and I2C1 (master and slave on the open-drain lines through the matrix, the 16 commands with RSTART, WRITE, READ, STOP and END, the bus timing in APB_CLK cycles, ACK checks, arbitration, the SCL timeout, the 32-byte FIFOs through DATA and its AHB view, 7- and 10-bit slave addresses; ESP-IDF's i2c_eeprom runs on a 24LC256), PERIP_RST_EN's resets of I2C0, I2C1 and LEDC, the internal analog I2C master, the random number generator and the peripherals' AHB view. The evidence: test_lx6.c's programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16) and the APP_CPU's ROM data kept apart; ESP-IDF v5.4's hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo and real_time_stats built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart; the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin.", "omissions": [ "Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written)", "the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept", @@ -283,7 +283,10 @@ "repo:tests/vendor/esp-idf/examples/esp32_hello_world/scenario.json", "repo:tests/vendor/esp-idf/examples/esp32_blink/scenario.json", "repo:tests/vendor/esp-idf/examples/esp32_ledc_basic/scenario.json", - "repo:tests/vendor/esp-idf/examples/esp32_i2c_eeprom/scenario.json" + "repo:tests/vendor/esp-idf/examples/esp32_i2c_eeprom/scenario.json", + "repo:tests/vendor/esp-idf/examples/esp32_gptimer/scenario.json", + "repo:tests/vendor/esp-idf/examples/esp32_uart_echo/scenario.json", + "repo:tests/vendor/esp-idf/examples/esp32_real_time_stats/scenario.json" ] }, "timed": { @@ -389,11 +392,11 @@ }, "i18n": { "fr": { - "source": "40e3065d4198", + "source": "0ba7d2d0d3b6", "description": "Espressif ESP32 (ESP32-D0WD-V3, révision de puce v3.1) : deux cœurs Xtensa LX6 jusqu'à 240 MHz, 520 Kio de SRAM, 448 Kio de ROM, 16 Kio de mémoire RTC, une flash SPI externe derrière les caches des cœurs, Wi-Fi et Bluetooth ; le MCU de l'ESP32-DevKitC. La ROM d'Espressif, le bootloader de second niveau d'ESP-IDF et les applications ESP-IDF tournent sur les deux cœurs ; les radios ne sont pas encore modélisées.", "fidelity": { "functional": { - "claims": "Les deux cœurs Xtensa LX6 (mcu/xtensa/lx6.c, lx6fp.c) tels que les configure le core-isa.h d'Espressif : les instructions de base et de densité, les registres fenêtrés (64, le contrôle de débordement de chaque instruction, CALL4/8/12, ENTRY, RETW et son sous-débordement, MOVSP, ROTW, L32E/S32E), les boucles sans surcoût, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, les booléens, S32C1I avec SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), le paquet MAC16, la FPU simple précision (modes d'arrondi et drapeaux IEEE ; les séquences de division et de racine carrée qu'exécute libgcc donnent des résultats correctement arrondis), les exceptions XEA2 avec vecteurs relocalisables, 32 interruptions aux niveaux et types de core-isa.h (niveau, front, logicielles, les temporisateurs CCOMPARE0-2 contre CCOUNT, NMI), RSIL, WAITI, RFI, BREAK, IBREAK, DBREAK et ICOUNT de l'option de débogage, la protection par régions (huit régions de 512 Mo, 15 sans accès), les chargements et écritures non alignés, et les accès de données en 32 bits seulement du bus d'instructions. Les deux cœurs partagent la machine, l'APP_CPU maintenu en reset jusqu'à ce que DPORT le libère et voyant la ROM avec ses pointeurs vers les données ROM du PRO_CPU déplacés vers les siennes, comme dans l'image ROM APP_CPU d'Espressif. Le démarrage : la ROM d'Espressif (esp32_rev300_rom.elf, révision v3) depuis le vecteur de reset, sa bannière, les broches de configuration (GPIO_STRAP : SPI_FAST_FLASH_BOOT, ou le mode téléchargement avec GPIO0 bas), les causes de reset (RTC_CNTL), le contrôle anti-glitch de l'eFuse, la lecture de la flash par SPI1, le bootloader de second niveau d'ESP-IDF et sa vérification d'image sur l'accélérateur SHA, la MMU flash des caches, et l'application sur les deux cœurs. Les modèles : DPORT (reset, horloge et blocage de l'APP_CPU, CPU_PER_CONF, vidage et état des caches, tables de la MMU flash, les 69 sources de la matrice d'interruptions, les interruptions inter-CPU), RTC_CNTL (causes de reset, le temporisateur RTC, le chien de garde RTC avec sa protection au démarrage sur flash, les resets et blocages logiciels, les registres de stockage, SOC_CLK_SEL), APB_CTRL (les horloges CPU et APB depuis XTAL, PLL ou RC_FAST), le contrôleur eFuse avec les bits d'usine de la puce (ESP32-D0WD-V3 v3.1, une MAC avec son CRC, ou celle des réglages de la carte), GPIO et IO_MUX (40 plots, la matrice, tirages, drain ouvert, interruptions sur chaque CPU, le verrou de configuration), UART0-2 (FIFO, trames au débit, interruptions), TIMG0/1 (T0, T1, le temporisateur LAC, le MWDT avec sa protection au démarrage sur flash, la calibration de RTC_SLOW_CLK), SPI0/SPI1 avec la flash Giantec GT25Q32A du module (C4 60 16, l'identifiant que rapporte la carte du propriétaire), l'accélérateur SHA (SHA-1, -256, -384, -512), LEDC (huit canaux MLI rapides et huit lents sur huit temporisateurs, le fondu, sur ledc_hs/ls_sig_out de la matrice), I2C0 et I2C1 (maître et esclave sur les lignes à drain ouvert à travers la matrice, les 16 commandes avec RSTART, WRITE, READ, STOP et END, le timing du bus en cycles d'APB_CLK, les contrôles d'ACK, l'arbitrage, le délai d'attente sur SCL, les FIFO de 32 octets par DATA et sa vue AHB, les adresses esclaves sur 7 et 10 bits ; l'exemple i2c_eeprom d'ESP-IDF fonctionne avec une 24LC256), les resets de PERIP_RST_EN pour I2C0, I2C1 et LEDC, le maître I2C analogique interne, le générateur de nombres aléatoires et la vue AHB des périphériques. Les preuves : les programmes de test_lx6.c assemblés par l'assembleur d'Espressif (entiers, décalages, multiplication et division, boucles, branchements, mémoire avec S32C1I, récursion fenêtrée à travers les vecteurs de fenêtre de la ROM, SYSCALL, l'interruption du temporisateur CCOMPARE, FPU, MAC16) et les données ROM de l'APP_CPU tenues à part ; hello_world, blink, ledc_basic et i2c_eeprom d'ESP-IDF v5.4 compilés sans modification pour la cible esp32 sur l'ESP32-DevKitC V4, de la bannière de la ROM jusqu'à esp_restart ; l'image ROM est identique octet pour octet à l'esp32-v3-rom.bin du QEMU d'Espressif, et la vue qu'en a l'APP_CPU à son esp32-v3-rom-app.bin.", + "claims": "Les deux cœurs Xtensa LX6 (mcu/xtensa/lx6.c, lx6fp.c) tels que les configure le core-isa.h d'Espressif : les instructions de base et de densité, les registres fenêtrés (64, le contrôle de débordement de chaque instruction, CALL4/8/12, ENTRY, RETW et son sous-débordement, MOVSP, ROTW, L32E/S32E), les boucles sans surcoût, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, les booléens, S32C1I avec SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), le paquet MAC16, la FPU simple précision (modes d'arrondi et drapeaux IEEE ; les séquences de division et de racine carrée qu'exécute libgcc donnent des résultats correctement arrondis), les exceptions XEA2 avec vecteurs relocalisables, 32 interruptions aux niveaux et types de core-isa.h (niveau, front, logicielles, les temporisateurs CCOMPARE0-2 contre CCOUNT, NMI), RSIL, WAITI, RFI, BREAK, IBREAK, DBREAK et ICOUNT de l'option de débogage, la protection par régions (huit régions de 512 Mo, 15 sans accès), les chargements et écritures non alignés, et les accès de données en 32 bits seulement du bus d'instructions. Les deux cœurs partagent la machine, l'APP_CPU maintenu en reset jusqu'à ce que DPORT le libère et voyant la ROM avec ses pointeurs vers les données ROM du PRO_CPU déplacés vers les siennes, comme dans l'image ROM APP_CPU d'Espressif. Le démarrage : la ROM d'Espressif (esp32_rev300_rom.elf, révision v3) depuis le vecteur de reset, sa bannière, les broches de configuration (GPIO_STRAP : SPI_FAST_FLASH_BOOT, ou le mode téléchargement avec GPIO0 bas), les causes de reset (RTC_CNTL), le contrôle anti-glitch de l'eFuse, la lecture de la flash par SPI1, le bootloader de second niveau d'ESP-IDF et sa vérification d'image sur l'accélérateur SHA, la MMU flash des caches, et l'application sur les deux cœurs. Les modèles : DPORT (reset, horloge et blocage de l'APP_CPU, CPU_PER_CONF, vidage et état des caches, tables de la MMU flash, les 69 sources de la matrice d'interruptions, les interruptions inter-CPU), RTC_CNTL (causes de reset, le temporisateur RTC, le chien de garde RTC avec sa protection au démarrage sur flash, les resets et blocages logiciels, les registres de stockage, SOC_CLK_SEL), APB_CTRL (les horloges CPU et APB depuis XTAL, PLL ou RC_FAST), le contrôleur eFuse avec les bits d'usine de la puce (ESP32-D0WD-V3 v3.1, une MAC avec son CRC, ou celle des réglages de la carte), GPIO et IO_MUX (40 plots, la matrice, tirages, drain ouvert, interruptions sur chaque CPU, le verrou de configuration), UART0-2 (FIFO, trames au débit, interruptions, les adresses de MEM_RX_STATUS d'après lesquelles ESP-IDF compte les octets en attente), TIMG0/1 (T0, T1, le temporisateur LAC, le MWDT avec sa protection au démarrage sur flash, la calibration de RTC_SLOW_CLK), SPI0/SPI1 avec la flash Giantec GT25Q32A du module (C4 60 16, l'identifiant que rapporte la carte du propriétaire), l'accélérateur SHA (SHA-1, -256, -384, -512), LEDC (huit canaux MLI rapides et huit lents sur huit temporisateurs, le fondu, sur ledc_hs/ls_sig_out de la matrice), I2C0 et I2C1 (maître et esclave sur les lignes à drain ouvert à travers la matrice, les 16 commandes avec RSTART, WRITE, READ, STOP et END, le timing du bus en cycles d'APB_CLK, les contrôles d'ACK, l'arbitrage, le délai d'attente sur SCL, les FIFO de 32 octets par DATA et sa vue AHB, les adresses esclaves sur 7 et 10 bits ; l'exemple i2c_eeprom d'ESP-IDF fonctionne avec une 24LC256), les resets de PERIP_RST_EN pour I2C0, I2C1 et LEDC, le maître I2C analogique interne, le générateur de nombres aléatoires et la vue AHB des périphériques. Les preuves : les programmes de test_lx6.c assemblés par l'assembleur d'Espressif (entiers, décalages, multiplication et division, boucles, branchements, mémoire avec S32C1I, récursion fenêtrée à travers les vecteurs de fenêtre de la ROM, SYSCALL, l'interruption du temporisateur CCOMPARE, FPU, MAC16) et les données ROM de l'APP_CPU tenues à part ; hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo et real_time_stats d'ESP-IDF v5.4 compilés sans modification pour la cible esp32 sur l'ESP32-DevKitC V4, de la bannière de la ROM jusqu'à esp_restart ; l'image ROM est identique octet pour octet à l'esp32-v3-rom.bin du QEMU d'Espressif, et la vue qu'en a l'APP_CPU à son esp32-v3-rom-app.bin.", "omissions": [ "le Wi-Fi, le Bluetooth et l'étage RF (WIFI_MAC, BB, NRX, FE : leurs registres gardent ce qui y est écrit)", "les instructions de l'accélérateur double précision (F64ADDC, F64ITER et les autres : leurs encodages sont publics, pas ce qu'elles font ; un programme qui en exécute une s'arrête avec un diagnostic), bien que ses registres soient conservés", diff --git a/core/mcu/esp32/soc/uart.c b/core/mcu/esp32/soc/uart.c index 349132885..23eb0ab14 100644 --- a/core/mcu/esp32/soc/uart.c +++ b/core/mcu/esp32/soc/uart.c @@ -29,7 +29,11 @@ * is INT_RAW and INT_ENA, and raises the matrix source (UART0 34, * UART1 35, UART2 36) while nonzero; * - STATUS reads the FIFOs' counts (with MEM_CNT_STATUS's high bits) - * and the lines; RXFIFO_RST and TXFIFO_RST empty the FIFOs while set. + * and the lines; MEM_RX_STATUS the RX RAM's read and write addresses + * (RD_ADDR, WR_ADDR), from which ESP-IDF's uart_ll counts the bytes + * waiting on the ESP32, each moving on a byte and wrapping at the RX + * FIFO's size (counted from the FIFO's start: the RAM's absolute + * addresses are not modelled); RXFIFO_RST and TXFIFO_RST empty the FIFOs while set. * Not modelled: autobaud, IrDA, RS485, the AT_CMD character, software * flow control (XON/XOFF), the RX glitch filter, light-sleep wake-up, * UHCI, the FIFO RAM's sharing between the UARTs beyond its sizes. */ @@ -63,10 +67,11 @@ struct e32_uart { struct esk_mach *s; struct esk_rf_periph *p; struct esk_rf_reg *fifo, *raw, *st, *ena, *clr, *clkdiv, *status, *conf0, *conf1, *idle, *mem, - *memcnt; + *memcnt, *memrx; int unit, source, level; u8 tx[4 * BLOCK], rx[2 * BLOCK]; int ntx, nrx; + u32 rx_rd, rx_wr; /* the RX RAM's read and write addresses (MEM_RX_STATUS) */ int busy; /* a frame, a break or the idle gap is on the TX line */ int clocked; /* the device's clock runs (esk_rf_clock) */ int phase; /* 0 a frame, 1 the idle after it, 2 a break */ @@ -162,6 +167,8 @@ static void update(struct e32_uart *u) ((u32)u->ntx & 0xffu) << 16); if (u->memcnt) esk_rf_hw(u->memcnt, (u32)(u->nrx >> 8) | (u32)(u->ntx >> 8) << 3); + if (u->memrx) + esk_rf_hw(u->memrx, (u->rx_rd & 0x7ffu) << 2 | (u->rx_wr & 0x7ffu) << 13); if ((reg(u->st) != 0) != u->level) { u->level = reg(u->st) != 0; esk_esp32_source(u->s, u->source, u->level); @@ -245,6 +252,7 @@ static void receive(struct e32_uart *u, u32 bits, int framing_error, int brk) set_raw(u, RAW_FRM_ERR); if (u->nrx < rx_cap(u)) { u->rx[u->nrx++] = (u8)(bits & ((1u << n) - 1u)); + u->rx_wr = (u->rx_wr + 1u) % (u32)rx_cap(u); u->rx_any = 1; } else { set_raw(u, RAW_RXFIFO_OVF); @@ -300,6 +308,7 @@ static u32 ur_read(void *ctx, u32 off, int n) if (!u->s->bus.debug) { memmove(u->rx, u->rx + 1, (size_t)(u->nrx - 1)); u->nrx--; + u->rx_rd = (u->rx_rd + 1u) % (u32)rx_cap(u); if (!u->nrx) u->rx_any = 0; update(u); @@ -327,6 +336,7 @@ static void ur_write(void *ctx, u32 off, int n, u32 v) u->ntx = 0; if (reg(u->conf0) & CONF0_RXFIFO_RST) { u->nrx = 0; + u->rx_rd = u->rx_wr = 0; u->rx_any = 0; } if ((reg(u->conf0) & CONF0_TXD_BRK) && !(was0 & CONF0_TXD_BRK)) @@ -403,6 +413,7 @@ static void ur_reset(void *ctx) { struct e32_uart *u = (struct e32_uart *)ctx; u->ntx = u->nrx = 0; + u->rx_rd = u->rx_wr = 0; u->busy = 0; u->clocked = 0; u->left = 0; @@ -443,6 +454,7 @@ void *esk_esp32_uart_create(struct esk_mach *s, struct esk_rf_periph *p) c->idle = esk_rf_reg(p, "IDLE_CONF"); c->mem = esk_rf_reg(p, "MEM_CONF"); c->memcnt = esk_rf_reg(p, "MEM_CNT_STATUS"); + c->memrx = esk_rf_reg(p, "MEM_RX_STATUS"); if (!c->fifo || !c->raw || !c->st || !c->ena || !c->clr || !c->clkdiv || !c->status || !c->conf0 || !c->conf1 || !c->idle || !c->mem) return 0; diff --git a/docs/STATUS.md b/docs/STATUS.md index 511f80037..37798483c 100644 --- a/docs/STATUS.md +++ b/docs/STATUS.md @@ -15,8 +15,9 @@ hello_world running unmodified on both cores at 160 MHz to `Hello world!` and through `esp_restart` (rst:0xc SW_CPU_RESET). Evidence: `test_lx6` (4,332 checks), the board's three fixtures, and the ESP-IDF vendor scenarios `esp32_hello_world` (9/9), `esp32_blink` (6/6), -`esp32_ledc_basic` (2/2) and `esp32_i2c_eeprom` (3/3, I2C0 writing and -reading a 24LC256 at 400 kHz). Not yet: Wi-Fi and Bluetooth, the +`esp32_ledc_basic` (2/2), `esp32_i2c_eeprom` (3/3, I2C0 writing and +reading a 24LC256 at 400 kHz), `esp32_gptimer` (17/17), `esp32_uart_echo` +(6/6) and `esp32_real_time_stats` (10/10). Not yet: Wi-Fi and Bluetooth, the double-precision accelerator's instructions, the peripherals the description's fidelity lists (I2S, SPI2/3, RMT, ADC, ...), sleep. The standalone harness below remains as its own qualification diff --git a/tests/vendor/esp-idf/examples/esp32_gptimer/project.json b/tests/vendor/esp-idf/examples/esp32_gptimer/project.json new file mode 100644 index 000000000..d30d5c047 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_gptimer/project.json @@ -0,0 +1,61 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "esp-idf-esp32_gptimer", + "description": "ESP-IDF's peripherals/timer_group/gptimer on the ESP32-DevKitC V4, plugged into USB; the console is UART0 through the CP2102N.", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + } + ], + "nets": { + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1" + ], + "USB5V": [ + "USB.+", + "B1.VBUS" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_gptimer/scenario.json b/tests/vendor/esp-idf/examples/esp32_gptimer/scenario.json new file mode 100644 index 000000000..fba0039f7 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_gptimer/scenario.json @@ -0,0 +1,146 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "esp32_gptimer", + "until": "9600ms", + "description": "gptimer: TIMG0's T0 at 1 MHz (APB_CLK / 80). Stopped at its 1 s alarm, the count the ISR reads is 1000001 (about 1 us from the alarm to the read at 160 MHz; ESP-IDF's README shows 1000002 on its chip); set to 100 and read back; four auto-reloads a second apart, each read 1 after its reload to 0; then four alarms moved 1 s on each time. Each event is pinned by a window (absent before, present after) rather than by the log's timestamps, which move by a millisecond with the image's size (the build's paths and compile time are in it).", + "inputs": [], + "assertions": [ + { + "id": "not-before-alarm", + "at": "1200ms", + "probe": "console", + "expect": { + "not_contains": "Timer stopped" + } + }, + { + "id": "stopped", + "at": "1300ms", + "probe": "console", + "expect": { + "contains": "example: Timer stopped, count=1000001\r\n" + } + }, + { + "id": "set", + "at": "1300ms", + "probe": "console", + "expect": { + "contains": "example: Timer count value=100\r\n" + } + }, + { + "id": "reload-not-early", + "at": "2200ms", + "probe": "console", + "expect": { + "not_contains": "Timer reloaded" + } + }, + { + "id": "reloaded", + "at": "2300ms", + "probe": "console", + "expect": { + "contains": "example: Timer reloaded, count=1\r\n" + } + }, + { + "id": "reloading", + "at": "5200ms", + "probe": "console", + "expect": { + "not_contains": "example: Stop timer" + } + }, + { + "id": "reloads-done", + "at": "5300ms", + "probe": "console", + "expect": { + "contains": "example: Stop timer" + } + }, + { + "id": "alarm1-not-early", + "at": "6200ms", + "probe": "console", + "expect": { + "not_contains": "example: Timer alarmed, count=1000001" + } + }, + { + "id": "alarm1", + "at": "6300ms", + "probe": "console", + "expect": { + "contains": "example: Timer alarmed, count=1000001\r\n" + } + }, + { + "id": "alarm2-not-early", + "at": "7200ms", + "probe": "console", + "expect": { + "not_contains": "example: Timer alarmed, count=2000001" + } + }, + { + "id": "alarm2", + "at": "7300ms", + "probe": "console", + "expect": { + "contains": "example: Timer alarmed, count=2000001\r\n" + } + }, + { + "id": "alarm3-not-early", + "at": "8200ms", + "probe": "console", + "expect": { + "not_contains": "example: Timer alarmed, count=3000001" + } + }, + { + "id": "alarm3", + "at": "8300ms", + "probe": "console", + "expect": { + "contains": "example: Timer alarmed, count=3000001\r\n" + } + }, + { + "id": "alarm4-not-early", + "at": "9200ms", + "probe": "console", + "expect": { + "not_contains": "example: Timer alarmed, count=4000001" + } + }, + { + "id": "alarm4", + "at": "9300ms", + "probe": "console", + "expect": { + "contains": "example: Timer alarmed, count=4000001\r\n" + } + }, + { + "id": "deleted", + "at": "9600ms", + "probe": "console", + "expect": { + "contains": "example: Delete timer" + } + }, + { + "id": "no-miss", + "at": "9600ms", + "probe": "console", + "expect": { + "not_contains": "Missed one count event" + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_real_time_stats/project.json b/tests/vendor/esp-idf/examples/esp32_real_time_stats/project.json new file mode 100644 index 000000000..1b585c2b9 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_real_time_stats/project.json @@ -0,0 +1,61 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "esp-idf-esp32_real_time_stats", + "description": "ESP-IDF's system/freertos/real_time_stats on the ESP32-DevKitC V4, plugged into USB; the console is UART0 through the CP2102N.", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + } + ], + "nets": { + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1" + ], + "USB5V": [ + "USB.+", + "B1.VBUS" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_real_time_stats/scenario.json b/tests/vendor/esp-idf/examples/esp32_real_time_stats/scenario.json new file mode 100644 index 000000000..31671eb94 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_real_time_stats/scenario.json @@ -0,0 +1,90 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "esp32_real_time_stats", + "until": "3500ms", + "description": "real_time_stats (FreeRTOS's run-time statistics on esp_timer's microseconds): six spin tasks of 500000 iterations and 100 ms sleeps, measured over 100 ticks (1 s) twice. The table's run times are the core's timing model's (each spin about 30 ms on either core at 160 MHz, about ten cycles an iteration from the flash cache), so the scenario checks the table's rows, not the figures: every spin task and both cores' idle tasks (IDLE0, IDLE1) listed, main deleted, the stats obtained each time. ESP-IDF's console turns each \\n into \\r\\n.", + "inputs": [], + "assertions": [ + { + "id": "first", + "at": "600ms", + "probe": "console", + "expect": { + "contains": "Getting real time stats over 100 ticks\r\n" + } + }, + { + "id": "table", + "at": "1500ms", + "probe": "console", + "expect": { + "contains": "| Task | Run Time | Percentage\r\n" + } + }, + { + "id": "spin0", + "at": "1500ms", + "probe": "console", + "expect": { + "contains": "| spin0 | " + } + }, + { + "id": "spin5", + "at": "1500ms", + "probe": "console", + "expect": { + "contains": "| spin5 | " + } + }, + { + "id": "idle0", + "at": "1500ms", + "probe": "console", + "expect": { + "contains": "| IDLE0 | " + } + }, + { + "id": "idle1", + "at": "1500ms", + "probe": "console", + "expect": { + "contains": "| IDLE1 | " + } + }, + { + "id": "main-deleted", + "at": "1500ms", + "probe": "console", + "expect": { + "contains": "| main | Deleted\r\n" + } + }, + { + "id": "obtained", + "at": "1500ms", + "probe": "console", + "expect": { + "contains": "Real time stats obtained\r\n" + } + }, + { + "id": "second", + "at": "3500ms", + "probe": "console", + "expect": { + "contains": "Real time stats obtained\r\n\r\n\r\nGetting real time stats over 100 ticks\r\n" + } + }, + { + "id": "no-error", + "at": "3500ms", + "probe": "console", + "expect": { + "not_contains": "Error getting real time stats" + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_uart_echo/project.json b/tests/vendor/esp-idf/examples/esp32_uart_echo/project.json new file mode 100644 index 000000000..ceed1c3d4 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_uart_echo/project.json @@ -0,0 +1,91 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "esp-idf-esp32_uart_echo", + "description": "ESP-IDF's uart/uart_echo on the ESP32-DevKitC V4: UART2 (the example's port on the ESP32) on TXD IO4 and RXD IO5 at 115200 baud, the example's defaults, to a 3.3 V USB-serial adapter's terminal.", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + }, + { + "id": "VT1", + "component": "emblink/virtual_terminal", + "params": { + "baud": 115200 + }, + "layout": { + "x": 120, + "y": 460 + } + } + ], + "nets": { + "USB5V": [ + "USB.+", + "B1.VBUS" + ], + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1", + "VT1.GND" + ], + "U2TXD": [ + "B1.IO4", + "VT1.RX" + ], + "U2RXD": [ + "B1.IO5", + "VT1.TX" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + }, + { + "id": "sent", + "target": "serial:VT1", + "kind": "serial" + }, + { + "id": "received", + "target": "output:VT1.rx_text", + "kind": "value" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_uart_echo/scenario.json b/tests/vendor/esp-idf/examples/esp32_uart_echo/scenario.json new file mode 100644 index 000000000..c8b4c25c6 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_uart_echo/scenario.json @@ -0,0 +1,71 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "esp32_uart_echo", + "until": "1200ms", + "description": "uart_echo: what the terminal sends to IO5 comes back on IO4, and the console logs it. The echo task reads with a 20 ms timeout (two FreeRTOS ticks), so a line typed at once comes back whole.", + "inputs": [ + { + "at": "500ms", + "target": "VT1", + "input": "tx_text", + "value": "hello EmbSIM" + }, + { + "at": "900ms", + "target": "VT1", + "input": "tx_text", + "value": "0123456789" + } + ], + "assertions": [ + { + "id": "quiet", + "at": "450ms", + "probe": "received", + "expect": { + "equals": "" + } + }, + { + "id": "sent", + "at": "600ms", + "probe": "sent", + "expect": { + "equals": "hello EmbSIM" + } + }, + { + "id": "echo", + "at": "600ms", + "probe": "received", + "expect": { + "equals": "hello EmbSIM" + } + }, + { + "id": "logged", + "at": "600ms", + "probe": "console", + "expect": { + "contains": "UART TEST: Recv str: hello EmbSIM\r\n" + } + }, + { + "id": "again", + "at": "1200ms", + "probe": "received", + "expect": { + "equals": "hello EmbSIM0123456789" + } + }, + { + "id": "logged-again", + "at": "1200ms", + "probe": "console", + "expect": { + "contains": "UART TEST: Recv str: 0123456789\r\n" + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/run.py b/tests/vendor/esp-idf/run.py index d5cd3d58d..63712fede 100644 --- a/tests/vendor/esp-idf/run.py +++ b/tests/vendor/esp-idf/run.py @@ -75,6 +75,9 @@ "esp32_blink": "examples/get-started/blink", "esp32_ledc_basic": "examples/peripherals/ledc/ledc_basic", "esp32_i2c_eeprom": "examples/peripherals/i2c/i2c_eeprom", + "esp32_gptimer": "examples/peripherals/timer_group/gptimer", + "esp32_uart_echo": "examples/peripherals/uart/uart_echo", + "esp32_real_time_stats": "examples/system/freertos/real_time_stats", } # the target an example is built for, when not the ESP32-C3 (its board in # examples//project.json), and the toolchain that target needs @@ -83,6 +86,9 @@ "esp32_blink": "esp32", "esp32_ledc_basic": "esp32", "esp32_i2c_eeprom": "esp32", + "esp32_gptimer": "esp32", + "esp32_uart_echo": "esp32", + "esp32_real_time_stats": "esp32", } TOOLCHAINS = {"esp32c3": "riscv32-esp-elf-gcc", "esp32": "xtensa-esp32-elf-gcc"} # examples built only for another's project (with examples//'s From d337a4efe04fc666d8ca62a43a71579b2b3a74c9 Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 04:50:12 +0000 Subject: [PATCH 11/16] ESP32: the RMT, with ESP-IDF's blink on a WS2812B The ESP32's remote control peripheral from the C3's model on the ESP32's registers: eight channels each sending or receiving through the matrix (rmt_sig_out0-7, rmt_sig_in0-7), 64-word blocks of the 512-word RAM (added to the register file with svd2regs' --memory: the SVD leaves it out), the clock from APB_CLK or REF_TICK, end markers, continuous mode, wrap, TX_LIM, the carrier, the receiver's idle threshold and filter, CHnDATA, three interrupt bits a channel. ESP-IDF's get-started/blink with its LED-strip option runs unmodified on the DevKitC with a WS2812B on IO18 (esp32_blink_strip 7/7). --- CHANGELOG.md | 5 +- catalog/mcus/espressif/esp32/mcu.json | 19 +- catalog/mcus/espressif/esp32/registers.json | 6100 ++++++++++++++++- core/mcu/esp32/soc/esp32.h | 3 + core/mcu/esp32/soc/rmt.c | 679 ++ core/mcu/models.c | 1 + docs/STATUS.md | 5 +- docs/coverage.md | 8 +- .../examples/esp32_blink_strip/project.json | 100 + .../examples/esp32_blink_strip/scenario.json | 66 + .../esp32_blink_strip/sdkconfig.defaults | 3 + tests/vendor/esp-idf/run.py | 2 + 12 files changed, 6743 insertions(+), 248 deletions(-) create mode 100644 core/mcu/esp32/soc/rmt.c create mode 100644 tests/vendor/esp-idf/examples/esp32_blink_strip/project.json create mode 100644 tests/vendor/esp-idf/examples/esp32_blink_strip/scenario.json create mode 100644 tests/vendor/esp-idf/examples/esp32_blink_strip/sdkconfig.defaults diff --git a/CHANGELOG.md b/CHANGELOG.md index 0e3f4da43..d4a82d03a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -21,14 +21,15 @@ versions follow semantic versioning. There is no release yet. interrupt matrix), RTC_CNTL, eFuse, APB_CTRL clocks, GPIO/IO_MUX with strapping, UART0-2, TIMG0/1, SPI0/1 with the GT25Q32A flash, SHA, LEDC, I2C0/1 (master and slave, 16 commands, APB_CLK timing; DPORT's - PERIP_RST_EN resets them), the internal analog I2C, RNG and the AHB view. + PERIP_RST_EN resets them), the RMT's eight channels, the internal analog I2C, RNG and the AHB view. - Added the `emblink/esp32_devkitc` board (ESP32-DevKitC V4, WROOM-32E) with its power path, LED, Boot and EN buttons, headers and fixtures. - Espressif's ROM, ESP-IDF v5.4's bootloader and hello_world run unmodified through `esp_restart` (`tests/vendor/esp-idf`: `esp32_hello_world` 9/9, `esp32_blink` 6/6, `esp32_ledc_basic` 2/2, `esp32_i2c_eeprom` 3/3 on a 24LC256, `esp32_gptimer` 17/17, `esp32_uart_echo` 6/6 on UART2, - `esp32_real_time_stats` 10/10 across both cores; the UARTs keep + `esp32_real_time_stats` 10/10 across both cores, + `esp32_blink_strip` 7/7 on a WS2812B through the RMT; the UARTs keep MEM_RX_STATUS's addresses, from which ESP-IDF counts the bytes waiting); `test_lx6` checks the core with programs from Espressif's assembler. ### Original ESP32 digital per-pin hold diff --git a/catalog/mcus/espressif/esp32/mcu.json b/catalog/mcus/espressif/esp32/mcu.json index f8e536095..587b267dc 100644 --- a/catalog/mcus/espressif/esp32/mcu.json +++ b/catalog/mcus/espressif/esp32/mcu.json @@ -199,6 +199,10 @@ { "match": "I2C?", "model": "esp32-i2c" + }, + { + "match": "RMT", + "model": "esp32-rmt" } ], "io": { @@ -267,13 +271,14 @@ }, "fidelity": { "functional": { - "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts, MEM_RX_STATUS's addresses that ESP-IDF counts the bytes waiting from), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), I2C0 and I2C1 (master and slave on the open-drain lines through the matrix, the 16 commands with RSTART, WRITE, READ, STOP and END, the bus timing in APB_CLK cycles, ACK checks, arbitration, the SCL timeout, the 32-byte FIFOs through DATA and its AHB view, 7- and 10-bit slave addresses; ESP-IDF's i2c_eeprom runs on a 24LC256), PERIP_RST_EN's resets of I2C0, I2C1 and LEDC, the internal analog I2C master, the random number generator and the peripherals' AHB view. The evidence: test_lx6.c's programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16) and the APP_CPU's ROM data kept apart; ESP-IDF v5.4's hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo and real_time_stats built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart; the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin.", + "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts, MEM_RX_STATUS's addresses that ESP-IDF counts the bytes waiting from), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), I2C0 and I2C1 (master and slave on the open-drain lines through the matrix, the 16 commands with RSTART, WRITE, READ, STOP and END, the bus timing in APB_CLK cycles, ACK checks, arbitration, the SCL timeout, the 32-byte FIFOs through DATA and its AHB view, 7- and 10-bit slave addresses; ESP-IDF's i2c_eeprom runs on a 24LC256), the RMT (eight channels sending or receiving through the matrix, 64-word blocks of the 512-word RAM, end markers, continuous mode, wrap, TX_LIM's threshold, the carrier, the receiver's idle threshold and filter, the RAM through CHnDATA; ESP-IDF's led_strip lights a WS2812B), PERIP_RST_EN's resets of I2C0, I2C1 and LEDC, the internal analog I2C master, the random number generator and the peripherals' AHB view. The evidence: test_lx6.c's programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16) and the APP_CPU's ROM data kept apart; ESP-IDF v5.4's hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats and blink with its LED strip built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart; the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin.", "omissions": [ "Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written)", "the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept", "PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts", + "RMT: the memory's power-down (MEM_PD), STATUS's STATE and the APB-side error bits, the carrier on an idle output", "I2C: the non-FIFO mode (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, the input filters (only their share of the SCL high time), 10-bit addressing's R/W check", - "the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), RMT, MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption", + "the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption", "sleep modes (light and deep sleep, the power domains), brown-out", "the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection" ], @@ -286,7 +291,8 @@ "repo:tests/vendor/esp-idf/examples/esp32_i2c_eeprom/scenario.json", "repo:tests/vendor/esp-idf/examples/esp32_gptimer/scenario.json", "repo:tests/vendor/esp-idf/examples/esp32_uart_echo/scenario.json", - "repo:tests/vendor/esp-idf/examples/esp32_real_time_stats/scenario.json" + "repo:tests/vendor/esp-idf/examples/esp32_real_time_stats/scenario.json", + "repo:tests/vendor/esp-idf/examples/esp32_blink_strip/scenario.json" ] }, "timed": { @@ -392,17 +398,18 @@ }, "i18n": { "fr": { - "source": "0ba7d2d0d3b6", + "source": "f8310c3fa74c", "description": "Espressif ESP32 (ESP32-D0WD-V3, révision de puce v3.1) : deux cœurs Xtensa LX6 jusqu'à 240 MHz, 520 Kio de SRAM, 448 Kio de ROM, 16 Kio de mémoire RTC, une flash SPI externe derrière les caches des cœurs, Wi-Fi et Bluetooth ; le MCU de l'ESP32-DevKitC. La ROM d'Espressif, le bootloader de second niveau d'ESP-IDF et les applications ESP-IDF tournent sur les deux cœurs ; les radios ne sont pas encore modélisées.", "fidelity": { "functional": { - "claims": "Les deux cœurs Xtensa LX6 (mcu/xtensa/lx6.c, lx6fp.c) tels que les configure le core-isa.h d'Espressif : les instructions de base et de densité, les registres fenêtrés (64, le contrôle de débordement de chaque instruction, CALL4/8/12, ENTRY, RETW et son sous-débordement, MOVSP, ROTW, L32E/S32E), les boucles sans surcoût, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, les booléens, S32C1I avec SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), le paquet MAC16, la FPU simple précision (modes d'arrondi et drapeaux IEEE ; les séquences de division et de racine carrée qu'exécute libgcc donnent des résultats correctement arrondis), les exceptions XEA2 avec vecteurs relocalisables, 32 interruptions aux niveaux et types de core-isa.h (niveau, front, logicielles, les temporisateurs CCOMPARE0-2 contre CCOUNT, NMI), RSIL, WAITI, RFI, BREAK, IBREAK, DBREAK et ICOUNT de l'option de débogage, la protection par régions (huit régions de 512 Mo, 15 sans accès), les chargements et écritures non alignés, et les accès de données en 32 bits seulement du bus d'instructions. Les deux cœurs partagent la machine, l'APP_CPU maintenu en reset jusqu'à ce que DPORT le libère et voyant la ROM avec ses pointeurs vers les données ROM du PRO_CPU déplacés vers les siennes, comme dans l'image ROM APP_CPU d'Espressif. Le démarrage : la ROM d'Espressif (esp32_rev300_rom.elf, révision v3) depuis le vecteur de reset, sa bannière, les broches de configuration (GPIO_STRAP : SPI_FAST_FLASH_BOOT, ou le mode téléchargement avec GPIO0 bas), les causes de reset (RTC_CNTL), le contrôle anti-glitch de l'eFuse, la lecture de la flash par SPI1, le bootloader de second niveau d'ESP-IDF et sa vérification d'image sur l'accélérateur SHA, la MMU flash des caches, et l'application sur les deux cœurs. Les modèles : DPORT (reset, horloge et blocage de l'APP_CPU, CPU_PER_CONF, vidage et état des caches, tables de la MMU flash, les 69 sources de la matrice d'interruptions, les interruptions inter-CPU), RTC_CNTL (causes de reset, le temporisateur RTC, le chien de garde RTC avec sa protection au démarrage sur flash, les resets et blocages logiciels, les registres de stockage, SOC_CLK_SEL), APB_CTRL (les horloges CPU et APB depuis XTAL, PLL ou RC_FAST), le contrôleur eFuse avec les bits d'usine de la puce (ESP32-D0WD-V3 v3.1, une MAC avec son CRC, ou celle des réglages de la carte), GPIO et IO_MUX (40 plots, la matrice, tirages, drain ouvert, interruptions sur chaque CPU, le verrou de configuration), UART0-2 (FIFO, trames au débit, interruptions, les adresses de MEM_RX_STATUS d'après lesquelles ESP-IDF compte les octets en attente), TIMG0/1 (T0, T1, le temporisateur LAC, le MWDT avec sa protection au démarrage sur flash, la calibration de RTC_SLOW_CLK), SPI0/SPI1 avec la flash Giantec GT25Q32A du module (C4 60 16, l'identifiant que rapporte la carte du propriétaire), l'accélérateur SHA (SHA-1, -256, -384, -512), LEDC (huit canaux MLI rapides et huit lents sur huit temporisateurs, le fondu, sur ledc_hs/ls_sig_out de la matrice), I2C0 et I2C1 (maître et esclave sur les lignes à drain ouvert à travers la matrice, les 16 commandes avec RSTART, WRITE, READ, STOP et END, le timing du bus en cycles d'APB_CLK, les contrôles d'ACK, l'arbitrage, le délai d'attente sur SCL, les FIFO de 32 octets par DATA et sa vue AHB, les adresses esclaves sur 7 et 10 bits ; l'exemple i2c_eeprom d'ESP-IDF fonctionne avec une 24LC256), les resets de PERIP_RST_EN pour I2C0, I2C1 et LEDC, le maître I2C analogique interne, le générateur de nombres aléatoires et la vue AHB des périphériques. Les preuves : les programmes de test_lx6.c assemblés par l'assembleur d'Espressif (entiers, décalages, multiplication et division, boucles, branchements, mémoire avec S32C1I, récursion fenêtrée à travers les vecteurs de fenêtre de la ROM, SYSCALL, l'interruption du temporisateur CCOMPARE, FPU, MAC16) et les données ROM de l'APP_CPU tenues à part ; hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo et real_time_stats d'ESP-IDF v5.4 compilés sans modification pour la cible esp32 sur l'ESP32-DevKitC V4, de la bannière de la ROM jusqu'à esp_restart ; l'image ROM est identique octet pour octet à l'esp32-v3-rom.bin du QEMU d'Espressif, et la vue qu'en a l'APP_CPU à son esp32-v3-rom-app.bin.", + "claims": "Les deux cœurs Xtensa LX6 (mcu/xtensa/lx6.c, lx6fp.c) tels que les configure le core-isa.h d'Espressif : les instructions de base et de densité, les registres fenêtrés (64, le contrôle de débordement de chaque instruction, CALL4/8/12, ENTRY, RETW et son sous-débordement, MOVSP, ROTW, L32E/S32E), les boucles sans surcoût, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, les booléens, S32C1I avec SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), le paquet MAC16, la FPU simple précision (modes d'arrondi et drapeaux IEEE ; les séquences de division et de racine carrée qu'exécute libgcc donnent des résultats correctement arrondis), les exceptions XEA2 avec vecteurs relocalisables, 32 interruptions aux niveaux et types de core-isa.h (niveau, front, logicielles, les temporisateurs CCOMPARE0-2 contre CCOUNT, NMI), RSIL, WAITI, RFI, BREAK, IBREAK, DBREAK et ICOUNT de l'option de débogage, la protection par régions (huit régions de 512 Mo, 15 sans accès), les chargements et écritures non alignés, et les accès de données en 32 bits seulement du bus d'instructions. Les deux cœurs partagent la machine, l'APP_CPU maintenu en reset jusqu'à ce que DPORT le libère et voyant la ROM avec ses pointeurs vers les données ROM du PRO_CPU déplacés vers les siennes, comme dans l'image ROM APP_CPU d'Espressif. Le démarrage : la ROM d'Espressif (esp32_rev300_rom.elf, révision v3) depuis le vecteur de reset, sa bannière, les broches de configuration (GPIO_STRAP : SPI_FAST_FLASH_BOOT, ou le mode téléchargement avec GPIO0 bas), les causes de reset (RTC_CNTL), le contrôle anti-glitch de l'eFuse, la lecture de la flash par SPI1, le bootloader de second niveau d'ESP-IDF et sa vérification d'image sur l'accélérateur SHA, la MMU flash des caches, et l'application sur les deux cœurs. Les modèles : DPORT (reset, horloge et blocage de l'APP_CPU, CPU_PER_CONF, vidage et état des caches, tables de la MMU flash, les 69 sources de la matrice d'interruptions, les interruptions inter-CPU), RTC_CNTL (causes de reset, le temporisateur RTC, le chien de garde RTC avec sa protection au démarrage sur flash, les resets et blocages logiciels, les registres de stockage, SOC_CLK_SEL), APB_CTRL (les horloges CPU et APB depuis XTAL, PLL ou RC_FAST), le contrôleur eFuse avec les bits d'usine de la puce (ESP32-D0WD-V3 v3.1, une MAC avec son CRC, ou celle des réglages de la carte), GPIO et IO_MUX (40 plots, la matrice, tirages, drain ouvert, interruptions sur chaque CPU, le verrou de configuration), UART0-2 (FIFO, trames au débit, interruptions, les adresses de MEM_RX_STATUS d'après lesquelles ESP-IDF compte les octets en attente), TIMG0/1 (T0, T1, le temporisateur LAC, le MWDT avec sa protection au démarrage sur flash, la calibration de RTC_SLOW_CLK), SPI0/SPI1 avec la flash Giantec GT25Q32A du module (C4 60 16, l'identifiant que rapporte la carte du propriétaire), l'accélérateur SHA (SHA-1, -256, -384, -512), LEDC (huit canaux MLI rapides et huit lents sur huit temporisateurs, le fondu, sur ledc_hs/ls_sig_out de la matrice), I2C0 et I2C1 (maître et esclave sur les lignes à drain ouvert à travers la matrice, les 16 commandes avec RSTART, WRITE, READ, STOP et END, le timing du bus en cycles d'APB_CLK, les contrôles d'ACK, l'arbitrage, le délai d'attente sur SCL, les FIFO de 32 octets par DATA et sa vue AHB, les adresses esclaves sur 7 et 10 bits ; l'exemple i2c_eeprom d'ESP-IDF fonctionne avec une 24LC256), le RMT (huit canaux qui émettent ou reçoivent à travers la matrice, des blocs de 64 mots de la RAM de 512 mots, les marqueurs de fin, le mode continu, le rebouclage, le seuil de TX_LIM, la porteuse, le seuil d'inactivité et le filtre du récepteur, la RAM par CHnDATA ; le led_strip d'ESP-IDF allume une WS2812B), les resets de PERIP_RST_EN pour I2C0, I2C1 et LEDC, le maître I2C analogique interne, le générateur de nombres aléatoires et la vue AHB des périphériques. Les preuves : les programmes de test_lx6.c assemblés par l'assembleur d'Espressif (entiers, décalages, multiplication et division, boucles, branchements, mémoire avec S32C1I, récursion fenêtrée à travers les vecteurs de fenêtre de la ROM, SYSCALL, l'interruption du temporisateur CCOMPARE, FPU, MAC16) et les données ROM de l'APP_CPU tenues à part ; hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats et blink avec son ruban de LED d'ESP-IDF v5.4 compilés sans modification pour la cible esp32 sur l'ESP32-DevKitC V4, de la bannière de la ROM jusqu'à esp_restart ; l'image ROM est identique octet pour octet à l'esp32-v3-rom.bin du QEMU d'Espressif, et la vue qu'en a l'APP_CPU à son esp32-v3-rom-app.bin.", "omissions": [ "le Wi-Fi, le Bluetooth et l'étage RF (WIFI_MAC, BB, NRX, FE : leurs registres gardent ce qui y est écrit)", "les instructions de l'accélérateur double précision (F64ADDC, F64ITER et les autres : leurs encodages sont publics, pas ce qu'elles font ; un programme qui en exécute une s'arrête avec un diagnostic), bien que ses registres soient conservés", "la PSRAM (DRAM1), le remappage de démarrage, les permissions d'accès APB/AHB, les régions verrouillées et le timing des caches (les pages mappées sont lues entières), les interruptions d'erreur d'accès de la MMU", + "RMT : la mise hors tension de la mémoire (MEM_PD), le champ STATE de STATUS et les bits d'erreur côté APB, la porteuse sur une sortie inactive", "I2C : le mode hors FIFO (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, les filtres d'entrée (seulement leur part du temps haut de SCL), le contrôle R/W de l'adressage sur 10 bits", - "les périphériques sans modèle pour l'instant : I2S0/1, SPI2/3 (HSPI, VSPI), RMT, MCPWM, PCNT, TWAI, SDMMC, EMAC, les ADC SAR, les DAC, le capteur tactile, l'IO MUX RTC et le coprocesseur ULP, les accélérateurs AES et RSA, le chiffrement de la flash", + "les périphériques sans modèle pour l'instant : I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, les ADC SAR, les DAC, le capteur tactile, l'IO MUX RTC et le coprocesseur ULP, les accélérateurs AES et RSA, le chiffrement de la flash", "les modes de veille (veille légère et profonde, les domaines d'alimentation), la détection de baisse de tension", "le contrôle du schéma de codage 3/4 de l'eFuse, la protection en écriture par champ du BLOCK0" ] diff --git a/catalog/mcus/espressif/esp32/registers.json b/catalog/mcus/espressif/esp32/registers.json index eca92b1ef..b6a5b7d95 100644 --- a/catalog/mcus/espressif/esp32/registers.json +++ b/catalog/mcus/espressif/esp32/registers.json @@ -4,7 +4,7 @@ "id": "espressif/esp32/registers", "version": "1.0.0", "device": "ESP32", - "source": "converted from esp32.svd by tools/importers/svd2regs.py; peripherals left out: RNG (the random number generator's one register (RNG_DATA, TRM 26), which the SVD puts at the AHB address 0x60035144; the chip's model answers at 0x3FF75144 and its AHB alias (misc.c)); fields corrected from the reference manual: DPORT.WIFI_CLK_EN.WIFI_CLK_EN:0:32; fields reserved by the reference manual taken out: GPIO.CPUSDIO_INT1.PIN_PAD_DRIVER, GPIO.CPUSDIO_INT1.PIN_INT_TYPE, GPIO.CPUSDIO_INT1.PIN_WAKEUP_ENABLE, GPIO.CPUSDIO_INT1.PIN_CONFIG, GPIO.CPUSDIO_INT1.PIN_INT_ENA, SENS.SAR_MEAS_WAIT2.FORCE_XPD_SAR_SW; overlapping fields taken out: DPORT.PRO_DCACHE_DBUG0 (PRO_CACHE_MMU_IA), DPORT.PRO_DCACHE_DBUG3 (PRO_CPU_DISABLED_CACHE_IA), DPORT.APP_DCACHE_DBUG0 (APP_CACHE_MMU_IA), DPORT.APP_DCACHE_DBUG3 (APP_CPU_DISABLED_CACHE_IA), DPORT.PRO_CPU_RECORD_PDEBUGINST (RECORD_PRO_PDEBUGINST), DPORT.PRO_CPU_RECORD_PDEBUGSTATUS (RECORD_PRO_PDEBUGSTATUS, RECORD_PDEBUGSTATUS_INSNTYPE), DPORT.PRO_CPU_RECORD_PDEBUGDATA (RECORD_PRO_PDEBUGDATA, RECORD_PDEBUGDATA_EXCVEC, RECORD_PDEBUGDATA_INSNTYPE_SR, RECORD_PDEBUGDATA_INSNTYPE_RER, RECORD_PDEBUGDATA_INSNTYPE_WER, RECORD_PDEBUGDATA_INSNTYPE_ER, RECORD_PDEBUGDATA_STALL_IPIF, RECORD_PDEBUGDATA_INSNTYPE_RSR, RECORD_PDEBUGDATA_INSNTYPE_WSR, RECORD_PDEBUGDATA_INSNTYPE_XSR, RECORD_PDEBUGDATA_STALL_BPIFETCH, RECORD_PDEBUGDATA_EXCCAUSE, RECORD_PDEBUGDATA_STALL_BANKCONFL), DPORT.PRO_CPU_RECORD_PDEBUGLS0STAT (RECORD_PRO_PDEBUGLS0STAT), DPORT.CACHE_IA_INT_EN (CACHE_IA_INT_EN), UART0.MEM_RX_STATUS (MEM_RX_STATUS), RTC_CNTL.LOW_POWER_ST (LOW_POWER_DIAG0), RTC_CNTL.BROWN_OUT (RTC_MEM_CRC_ADDR, RTC_MEM_CRC_LEN, RTC_MEM_CRC_FINISH), RMT.CH0STATUS (STATUS), RMT.CH1STATUS (STATUS), RMT.CH2STATUS (STATUS), RMT.CH3STATUS (STATUS), RMT.CH4STATUS (STATUS), RMT.CH5STATUS (STATUS), RMT.CH6STATUS (STATUS), RMT.CH7STATUS (STATUS), PCNT.U0_STATUS (CORE_STATUS_U0), PCNT.U1_STATUS (CORE_STATUS_U0), PCNT.U2_STATUS (CORE_STATUS_U0), PCNT.U3_STATUS (CORE_STATUS_U0), PCNT.U4_STATUS (CORE_STATUS_U0), PCNT.U5_STATUS (CORE_STATUS_U0), PCNT.U6_STATUS (CORE_STATUS_U0), PCNT.U7_STATUS (CORE_STATUS_U0)", + "source": "converted from esp32.svd by tools/importers/svd2regs.py; peripherals left out: RNG (the random number generator's one register (RNG_DATA, TRM 26), which the SVD puts at the AHB address 0x60035144; the chip's model answers at 0x3FF75144 and its AHB alias (misc.c)); memories added: RMT.RAM at 0x800, 512 words (the channels' RAM, eight blocks of 64 words (TRM 15.2.2, RMTMEM at 0x3FF56800)); fields corrected from the reference manual: DPORT.WIFI_CLK_EN.WIFI_CLK_EN:0:32; fields reserved by the reference manual taken out: GPIO.CPUSDIO_INT1.PIN_PAD_DRIVER, GPIO.CPUSDIO_INT1.PIN_INT_TYPE, GPIO.CPUSDIO_INT1.PIN_WAKEUP_ENABLE, GPIO.CPUSDIO_INT1.PIN_CONFIG, GPIO.CPUSDIO_INT1.PIN_INT_ENA, SENS.SAR_MEAS_WAIT2.FORCE_XPD_SAR_SW; overlapping fields taken out: DPORT.PRO_DCACHE_DBUG0 (PRO_CACHE_MMU_IA), DPORT.PRO_DCACHE_DBUG3 (PRO_CPU_DISABLED_CACHE_IA), DPORT.APP_DCACHE_DBUG0 (APP_CACHE_MMU_IA), DPORT.APP_DCACHE_DBUG3 (APP_CPU_DISABLED_CACHE_IA), DPORT.PRO_CPU_RECORD_PDEBUGINST (RECORD_PRO_PDEBUGINST), DPORT.PRO_CPU_RECORD_PDEBUGSTATUS (RECORD_PRO_PDEBUGSTATUS, RECORD_PDEBUGSTATUS_INSNTYPE), DPORT.PRO_CPU_RECORD_PDEBUGDATA (RECORD_PRO_PDEBUGDATA, RECORD_PDEBUGDATA_EXCVEC, RECORD_PDEBUGDATA_INSNTYPE_SR, RECORD_PDEBUGDATA_INSNTYPE_RER, RECORD_PDEBUGDATA_INSNTYPE_WER, RECORD_PDEBUGDATA_INSNTYPE_ER, RECORD_PDEBUGDATA_STALL_IPIF, RECORD_PDEBUGDATA_INSNTYPE_RSR, RECORD_PDEBUGDATA_INSNTYPE_WSR, RECORD_PDEBUGDATA_INSNTYPE_XSR, RECORD_PDEBUGDATA_STALL_BPIFETCH, RECORD_PDEBUGDATA_EXCCAUSE, RECORD_PDEBUGDATA_STALL_BANKCONFL), DPORT.PRO_CPU_RECORD_PDEBUGLS0STAT (RECORD_PRO_PDEBUGLS0STAT), DPORT.CACHE_IA_INT_EN (CACHE_IA_INT_EN), UART0.MEM_RX_STATUS (MEM_RX_STATUS), RTC_CNTL.LOW_POWER_ST (LOW_POWER_DIAG0), RTC_CNTL.BROWN_OUT (RTC_MEM_CRC_ADDR, RTC_MEM_CRC_LEN, RTC_MEM_CRC_FINISH), RMT.CH0STATUS (STATUS), RMT.CH1STATUS (STATUS), RMT.CH2STATUS (STATUS), RMT.CH3STATUS (STATUS), RMT.CH4STATUS (STATUS), RMT.CH5STATUS (STATUS), RMT.CH6STATUS (STATUS), RMT.CH7STATUS (STATUS), PCNT.U0_STATUS (CORE_STATUS_U0), PCNT.U1_STATUS (CORE_STATUS_U0), PCNT.U2_STATUS (CORE_STATUS_U0), PCNT.U3_STATUS (CORE_STATUS_U0), PCNT.U4_STATUS (CORE_STATUS_U0), PCNT.U5_STATUS (CORE_STATUS_U0), PCNT.U6_STATUS (CORE_STATUS_U0), PCNT.U7_STATUS (CORE_STATUS_U0)", "interrupts": { "WIFI_MAC": 0, "WIFI_NMI": 1, @@ -32872,134 +32872,80 @@ ] }, { - "name": "CH1CONF0", - "offset": "0x28", - "reset": "0x31100002", + "name": "CH0CONF1", + "offset": "0x24", + "reset": "0x00000F20", "fields": [ [ - "DIV_CNT", + "TX_START", 0, - 8 - ], - [ - "IDLE_THRES", - 8, - 16 - ], - [ - "MEM_SIZE", - 24, - 4 - ], - [ - "CARRIER_EN", - 28, 1 ], [ - "CARRIER_OUT_LV", - 29, + "RX_EN", + 1, 1 ], [ - "MEM_PD", - 30, + "MEM_WR_RST", + 2, 1 ], [ - "CLK_EN", - 31, + "MEM_RD_RST", + 3, 1 - ] - ] - }, - { - "name": "CH2CONF0", - "offset": "0x30", - "reset": "0x31100002", - "fields": [ - [ - "DIV_CNT", - 0, - 8 - ], - [ - "IDLE_THRES", - 8, - 16 - ], - [ - "MEM_SIZE", - 24, - 4 ], [ - "CARRIER_EN", - 28, + "APB_MEM_RST", + 4, 1 ], [ - "CARRIER_OUT_LV", - 29, + "MEM_OWNER", + 5, 1 ], [ - "MEM_PD", - 30, + "TX_CONTI_MODE", + 6, 1 ], [ - "CLK_EN", - 31, + "RX_FILTER_EN", + 7, 1 - ] - ] - }, - { - "name": "CH3CONF0", - "offset": "0x38", - "reset": "0x31100002", - "fields": [ - [ - "DIV_CNT", - 0, - 8 ], [ - "IDLE_THRES", + "RX_FILTER_THRES", 8, - 16 - ], - [ - "MEM_SIZE", - 24, - 4 + 8 ], [ - "CARRIER_EN", - 28, + "REF_CNT_RST", + 16, 1 ], [ - "CARRIER_OUT_LV", - 29, + "REF_ALWAYS_ON", + 17, 1 ], [ - "MEM_PD", - 30, + "IDLE_OUT_LV", + 18, 1 ], [ - "CLK_EN", - 31, + "IDLE_OUT_EN", + 19, 1 ] ] }, { - "name": "CH4CONF0", - "offset": "0x40", + "name": "CH1CONF0", + "offset": "0x28", "reset": "0x31100002", "fields": [ [ @@ -33040,92 +32986,80 @@ ] }, { - "name": "CH5CONF0", - "offset": "0x48", - "reset": "0x31100002", + "name": "CH1CONF1", + "offset": "0x2C", + "reset": "0x00000F20", "fields": [ [ - "DIV_CNT", + "TX_START", 0, - 8 + 1 ], [ - "IDLE_THRES", - 8, - 16 + "RX_EN", + 1, + 1 ], [ - "MEM_SIZE", - 24, - 4 + "MEM_WR_RST", + 2, + 1 ], [ - "CARRIER_EN", - 28, + "MEM_RD_RST", + 3, 1 ], [ - "CARRIER_OUT_LV", - 29, + "APB_MEM_RST", + 4, 1 ], [ - "MEM_PD", - 30, + "MEM_OWNER", + 5, 1 ], [ - "CLK_EN", - 31, + "TX_CONTI_MODE", + 6, 1 - ] - ] - }, - { - "name": "CH6CONF0", - "offset": "0x50", - "reset": "0x31100002", - "fields": [ - [ - "DIV_CNT", - 0, - 8 ], [ - "IDLE_THRES", - 8, - 16 + "RX_FILTER_EN", + 7, + 1 ], [ - "MEM_SIZE", - 24, - 4 + "RX_FILTER_THRES", + 8, + 8 ], [ - "CARRIER_EN", - 28, + "REF_CNT_RST", + 16, 1 ], [ - "CARRIER_OUT_LV", - 29, + "REF_ALWAYS_ON", + 17, 1 ], [ - "MEM_PD", - 30, + "IDLE_OUT_LV", + 18, 1 ], [ - "CLK_EN", - 31, + "IDLE_OUT_EN", + 19, 1 ] ] }, { - "name": "CH7CONF0", - "offset": "0x58", + "name": "CH2CONF0", + "offset": "0x30", "reset": "0x31100002", "fields": [ [ @@ -33166,8 +33100,8 @@ ] }, { - "name": "CH0CONF1", - "offset": "0x24", + "name": "CH2CONF1", + "offset": "0x34", "reset": "0x00000F20", "fields": [ [ @@ -33238,80 +33172,50 @@ ] }, { - "name": "CH1CONF1", - "offset": "0x2C", - "reset": "0x00000F20", + "name": "CH3CONF0", + "offset": "0x38", + "reset": "0x31100002", "fields": [ [ - "TX_START", + "DIV_CNT", 0, - 1 - ], - [ - "RX_EN", - 1, - 1 - ], - [ - "MEM_WR_RST", - 2, - 1 - ], - [ - "MEM_RD_RST", - 3, - 1 - ], - [ - "APB_MEM_RST", - 4, - 1 - ], - [ - "MEM_OWNER", - 5, - 1 - ], - [ - "TX_CONTI_MODE", - 6, - 1 + 8 ], [ - "RX_FILTER_EN", - 7, - 1 + "IDLE_THRES", + 8, + 16 ], [ - "RX_FILTER_THRES", - 8, - 8 + "MEM_SIZE", + 24, + 4 ], [ - "REF_CNT_RST", - 16, + "CARRIER_EN", + 28, 1 ], [ - "REF_ALWAYS_ON", - 17, + "CARRIER_OUT_LV", + 29, 1 ], [ - "IDLE_OUT_LV", - 18, + "MEM_PD", + 30, 1 ], [ - "IDLE_OUT_EN", - 19, + "CLK_EN", + 31, 1 ] ] }, { - "name": "CH2CONF1", - "offset": "0x34", + "name": "CH3CONF1", + "offset": "0x3C", "reset": "0x00000F20", "fields": [ [ @@ -33382,73 +33286,43 @@ ] }, { - "name": "CH3CONF1", - "offset": "0x3C", - "reset": "0x00000F20", + "name": "CH4CONF0", + "offset": "0x40", + "reset": "0x31100002", "fields": [ [ - "TX_START", + "DIV_CNT", 0, - 1 - ], - [ - "RX_EN", - 1, - 1 - ], - [ - "MEM_WR_RST", - 2, - 1 - ], - [ - "MEM_RD_RST", - 3, - 1 - ], - [ - "APB_MEM_RST", - 4, - 1 - ], - [ - "MEM_OWNER", - 5, - 1 - ], - [ - "TX_CONTI_MODE", - 6, - 1 + 8 ], [ - "RX_FILTER_EN", - 7, - 1 + "IDLE_THRES", + 8, + 16 ], [ - "RX_FILTER_THRES", - 8, - 8 + "MEM_SIZE", + 24, + 4 ], [ - "REF_CNT_RST", - 16, + "CARRIER_EN", + 28, 1 ], [ - "REF_ALWAYS_ON", - 17, + "CARRIER_OUT_LV", + 29, 1 ], [ - "IDLE_OUT_LV", - 18, + "MEM_PD", + 30, 1 ], [ - "IDLE_OUT_EN", - 19, + "CLK_EN", + 31, 1 ] ] @@ -33525,6 +33399,48 @@ ] ] }, + { + "name": "CH5CONF0", + "offset": "0x48", + "reset": "0x31100002", + "fields": [ + [ + "DIV_CNT", + 0, + 8 + ], + [ + "IDLE_THRES", + 8, + 16 + ], + [ + "MEM_SIZE", + 24, + 4 + ], + [ + "CARRIER_EN", + 28, + 1 + ], + [ + "CARRIER_OUT_LV", + 29, + 1 + ], + [ + "MEM_PD", + 30, + 1 + ], + [ + "CLK_EN", + 31, + 1 + ] + ] + }, { "name": "CH5CONF1", "offset": "0x4C", @@ -33597,6 +33513,48 @@ ] ] }, + { + "name": "CH6CONF0", + "offset": "0x50", + "reset": "0x31100002", + "fields": [ + [ + "DIV_CNT", + 0, + 8 + ], + [ + "IDLE_THRES", + 8, + 16 + ], + [ + "MEM_SIZE", + 24, + 4 + ], + [ + "CARRIER_EN", + 28, + 1 + ], + [ + "CARRIER_OUT_LV", + 29, + 1 + ], + [ + "MEM_PD", + 30, + 1 + ], + [ + "CLK_EN", + 31, + 1 + ] + ] + }, { "name": "CH6CONF1", "offset": "0x54", @@ -33669,6 +33627,48 @@ ] ] }, + { + "name": "CH7CONF0", + "offset": "0x58", + "reset": "0x31100002", + "fields": [ + [ + "DIV_CNT", + 0, + 8 + ], + [ + "IDLE_THRES", + 8, + 16 + ], + [ + "MEM_SIZE", + 24, + 4 + ], + [ + "CARRIER_EN", + 28, + 1 + ], + [ + "CARRIER_OUT_LV", + 29, + 1 + ], + [ + "MEM_PD", + 30, + 1 + ], + [ + "CLK_EN", + 31, + 1 + ] + ] + }, { "name": "CH7CONF1", "offset": "0x5C", @@ -35288,6 +35288,5638 @@ 32 ] ] + }, + { + "name": "RAM0", + "offset": "0x800", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM1", + "offset": "0x804", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM2", + "offset": "0x808", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM3", + "offset": "0x80C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM4", + "offset": "0x810", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM5", + "offset": "0x814", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM6", + "offset": "0x818", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM7", + "offset": "0x81C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM8", + "offset": "0x820", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM9", + "offset": "0x824", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM10", + "offset": "0x828", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM11", + "offset": "0x82C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM12", + "offset": "0x830", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM13", + "offset": "0x834", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM14", + "offset": "0x838", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM15", + "offset": "0x83C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM16", + "offset": "0x840", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM17", + "offset": "0x844", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM18", + "offset": "0x848", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM19", + "offset": "0x84C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM20", + "offset": "0x850", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM21", + "offset": "0x854", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM22", + "offset": "0x858", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM23", + "offset": "0x85C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM24", + "offset": "0x860", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM25", + "offset": "0x864", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM26", + "offset": "0x868", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM27", + "offset": "0x86C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM28", + "offset": "0x870", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM29", + "offset": "0x874", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM30", + "offset": "0x878", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM31", + "offset": "0x87C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM32", + "offset": "0x880", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM33", + "offset": "0x884", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM34", + "offset": "0x888", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM35", + "offset": "0x88C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM36", + "offset": "0x890", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM37", + "offset": "0x894", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM38", + "offset": "0x898", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM39", + "offset": "0x89C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM40", + "offset": "0x8A0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM41", + "offset": "0x8A4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM42", + "offset": "0x8A8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM43", + "offset": "0x8AC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM44", + "offset": "0x8B0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM45", + "offset": "0x8B4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM46", + "offset": "0x8B8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM47", + "offset": "0x8BC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM48", + "offset": "0x8C0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM49", + "offset": "0x8C4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM50", + "offset": "0x8C8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM51", + "offset": "0x8CC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM52", + "offset": "0x8D0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM53", + "offset": "0x8D4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM54", + "offset": "0x8D8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM55", + "offset": "0x8DC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM56", + "offset": "0x8E0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM57", + "offset": "0x8E4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM58", + "offset": "0x8E8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM59", + "offset": "0x8EC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM60", + "offset": "0x8F0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM61", + "offset": "0x8F4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM62", + "offset": "0x8F8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM63", + "offset": "0x8FC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM64", + "offset": "0x900", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM65", + "offset": "0x904", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM66", + "offset": "0x908", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM67", + "offset": "0x90C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM68", + "offset": "0x910", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM69", + "offset": "0x914", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM70", + "offset": "0x918", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM71", + "offset": "0x91C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM72", + "offset": "0x920", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM73", + "offset": "0x924", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM74", + "offset": "0x928", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM75", + "offset": "0x92C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM76", + "offset": "0x930", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM77", + "offset": "0x934", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM78", + "offset": "0x938", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM79", + "offset": "0x93C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM80", + "offset": "0x940", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM81", + "offset": "0x944", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM82", + "offset": "0x948", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM83", + "offset": "0x94C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM84", + "offset": "0x950", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM85", + "offset": "0x954", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM86", + "offset": "0x958", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM87", + "offset": "0x95C", + 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"fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM421", + "offset": "0xE94", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM422", + "offset": "0xE98", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM423", + "offset": "0xE9C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM424", + "offset": "0xEA0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM425", + "offset": "0xEA4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM426", + "offset": "0xEA8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM427", + "offset": "0xEAC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM428", + "offset": "0xEB0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM429", + "offset": "0xEB4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM430", + "offset": "0xEB8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM431", + "offset": "0xEBC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM432", + "offset": "0xEC0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM433", + "offset": "0xEC4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM434", + "offset": "0xEC8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM435", + "offset": "0xECC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM436", + "offset": "0xED0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM437", + "offset": "0xED4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM438", + "offset": "0xED8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM439", + "offset": "0xEDC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM440", + "offset": "0xEE0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM441", + "offset": "0xEE4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM442", + "offset": "0xEE8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM443", + "offset": "0xEEC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM444", + "offset": "0xEF0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM445", + "offset": "0xEF4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM446", + "offset": "0xEF8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM447", + "offset": "0xEFC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM448", + "offset": "0xF00", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM449", + "offset": "0xF04", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM450", + "offset": "0xF08", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM451", + "offset": "0xF0C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM452", + "offset": "0xF10", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM453", + "offset": "0xF14", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM454", + "offset": "0xF18", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM455", + "offset": "0xF1C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM456", + "offset": "0xF20", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM457", + "offset": "0xF24", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM458", + "offset": "0xF28", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM459", + "offset": "0xF2C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM460", + "offset": "0xF30", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM461", + "offset": "0xF34", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM462", + "offset": "0xF38", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM463", + "offset": "0xF3C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM464", + "offset": "0xF40", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM465", + "offset": "0xF44", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM466", + "offset": "0xF48", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM467", + "offset": "0xF4C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM468", + "offset": "0xF50", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM469", + "offset": "0xF54", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM470", + "offset": "0xF58", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM471", + "offset": "0xF5C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM472", + "offset": "0xF60", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM473", + "offset": "0xF64", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM474", + "offset": "0xF68", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM475", + "offset": "0xF6C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM476", + "offset": "0xF70", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM477", + "offset": "0xF74", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM478", + "offset": "0xF78", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM479", + "offset": "0xF7C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM480", + "offset": "0xF80", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM481", + "offset": "0xF84", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM482", + "offset": "0xF88", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM483", + "offset": "0xF8C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM484", + "offset": "0xF90", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM485", + "offset": "0xF94", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM486", + "offset": "0xF98", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM487", + "offset": "0xF9C", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM488", + "offset": "0xFA0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM489", + "offset": "0xFA4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM490", + "offset": "0xFA8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM491", + "offset": "0xFAC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM492", + "offset": "0xFB0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM493", + "offset": "0xFB4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM494", + "offset": "0xFB8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM495", + "offset": "0xFBC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM496", + "offset": "0xFC0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM497", + "offset": "0xFC4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM498", + "offset": "0xFC8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM499", + "offset": "0xFCC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM500", + "offset": "0xFD0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM501", + "offset": "0xFD4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM502", + "offset": "0xFD8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM503", + "offset": "0xFDC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM504", + "offset": "0xFE0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM505", + "offset": "0xFE4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM506", + "offset": "0xFE8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM507", + "offset": "0xFEC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM508", + "offset": "0xFF0", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM509", + "offset": "0xFF4", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM510", + "offset": "0xFF8", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] + }, + { + "name": "RAM511", + "offset": "0xFFC", + "fields": [ + [ + "DATA", + 0, + 32 + ] + ] } ] }, diff --git a/core/mcu/esp32/soc/esp32.h b/core/mcu/esp32/soc/esp32.h index 01aba4180..a6df40ba5 100644 --- a/core/mcu/esp32/soc/esp32.h +++ b/core/mcu/esp32/soc/esp32.h @@ -18,6 +18,7 @@ * sha.c the SHA accelerator * ledc.c the LED PWM controller * i2c.c I2C0 and I2C1 + * rmt.c the remote control peripheral's eight channels * misc.c the random number generator, the AHB view of the * peripherals */ #ifndef ESK_MCU_ESP32_SOC_H @@ -55,6 +56,8 @@ extern const struct esk_dev_ops esk_esp32_ledc_ops; void *esk_esp32_ledc_create(struct esk_mach *s, struct esk_rf_periph *p); extern const struct esk_dev_ops esk_esp32_i2c_ops; void *esk_esp32_i2c_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_rmt_ops; +void *esk_esp32_rmt_create(struct esk_mach *s, struct esk_rf_periph *p); extern const struct esk_dev_ops esk_esp32_sha_ops; void *esk_esp32_sha_create(struct esk_mach *s, struct esk_rf_periph *p); /* the RNG and the AHB view of the peripherals (misc.c): 0, or -1 */ diff --git a/core/mcu/esp32/soc/rmt.c b/core/mcu/esp32/soc/rmt.c new file mode 100644 index 000000000..99472863f --- /dev/null +++ b/core/mcu/esp32/soc/rmt.c @@ -0,0 +1,679 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* rmt.c -- the ESP32's remote control peripheral (RMT, TRM v5 chapter 15): + * eight channels, each a transmitter or a receiver (rmt_sig_out0-7, + * signals 87-94 of the GPIO matrix; rmt_sig_in0-7, 83-90), sharing a + * 512 x 32-bit RAM at +0x800, 64 words to a block; matrix source 47. The + * ESP32-C3's model (mcu/esp32c3/rmt.c) on the ESP32's registers. + * + * - A word holds two entries, the low half first: bits 14:0 a period in + * the channel's clock, bit 15 the level; a period of 0 ends the data. + * The channel's clock is APB_CLK (CONF1's REF_ALWAYS_ON 1) or + * REF_TICK's 1 MHz (0), divided by CONF0's DIV_CNT (0 is 256). The + * settings act as written (the ESP32 has no CONF_UPDATE). + * - Channel n uses MEM_SIZE blocks from its own (block n). The CPU + * reaches the RAM at its addresses or, with APB_CONF's APB_FIFO_MASK 0, + * through CHnDATA: a write appends to the channel's memory, a read takes + * its next word; APB_MEM_RST rewinds it (CHnADDR). + * - TX_START sends from the start of the channel's memory: each entry's + * level for its period. An end marker stops it (CHn_TX_END) and leaves + * the output at IDLE_OUT_LV when IDLE_OUT_EN is set, else at the + * marker's level. Past the end of its memory it goes on from the start + * with APB_CONF's MEM_TX_WRAP_EN, else stops with CHn_ERR. Every TX_LIM + * words sent raise CHn_TX_THR_EVENT. In continuous mode (TX_CONTI_MODE) + * an end marker, or the end of the memory, starts the data again. + * - The carrier (CARRIER_EN): while the channel sends the level + * CARRIER_OUT_LV, the output is CARRIER_DUTY's HIGH source-clock cycles + * high and LOW low, from the start of each such stretch. + * - RX_EN starts a receiver: from the input's first edge it writes each + * level and its length in the channel's clock; a level longer than + * IDLE_THRES ends it with an end marker (period 0, the idle level) and + * CHn_RX_END. With RX_FILTER_EN a pulse shorter than RX_FILTER_THRES + * APB_CLK cycles is dropped. At the end of its memory a receiver stops + * with CHn_ERR and MEM_FULL. A receiver whose memory the CPU owns + * (MEM_OWNER 0) writes nothing and sets MEM_OWNER_ERR. + * - CHnSTATUS: MEM_WADDR_EX and MEM_RADDR_EX the RAM's word addresses + * (ESP-IDF counts what a receiver wrote from the first), MEM_FULL, + * MEM_OWNER_ERR. + * - INT_ST is INT_RAW and INT_ENA, raising the source; INT_CLR clears. + * Where it differs inside: the edges are timed from the start of each + * transmission, not from a free-running divider (REF_CNT_RST has nothing + * to reset), and a carrier restarts with each stretch it modulates; the + * receiver's filter does not delay what it passes. Not yet: the memory's + * power-down (MEM_PD), STATUS's STATE and the APB-side error bits, the + * clock gate's effect on a running channel. */ +#include +#include + +#include "mcu/esp32/soc/esp32.h" + +#define SOURCE 47 +#define NCH 8 +#define NWORDS 512 +#define BLOCK 64 +#define SIG_OUT0 87 +#define SIG_IN0 83 +#define REF_TICK_HZ 1000000u +#define FS_PER_S 1000000000000000ull + +/* CONF0 */ +#define CARRIER_EN (1u << 28) +#define CARRIER_LV (1u << 29) +/* CONF1 */ +#define TX_START (1u << 0) +#define RX_EN (1u << 1) +#define MEM_WR_RST (1u << 2) +#define MEM_RD_RST (1u << 3) +#define APB_MEM_RST (1u << 4) +#define MEM_OWNER (1u << 5) +#define TX_CONTI (1u << 6) +#define FILTER_EN (1u << 7) +#define REF_ALWAYS_ON (1u << 17) +#define IDLE_LV (1u << 18) +#define IDLE_EN (1u << 19) +/* APB_CONF */ +#define FIFO_MASK (1u << 0) +#define TX_WRAP (1u << 1) +/* INT_RAW */ +#define I_TX_END(n) (1u << (3 * (n))) +#define I_RX_END(n) (1u << (3 * (n) + 1)) +#define I_ERR(n) (1u << (3 * (n) + 2)) +#define I_TX_THR(n) (1u << (24 + (n))) + +struct ch { + struct esk_rf_reg *conf0, *conf1, *status, *addr, *duty, *lim; + /* transmitting */ + int busy; + u32 e; /* the entry being sent, from the channel's first */ + u64 left; /* fs until the entry's end */ + int level; /* the data's level (while idle: the idle output's) */ + int out; /* the output */ + int carrying; /* the carrier modulates the output now */ + int cphase; /* the carrier's high half */ + u64 cleft; /* fs until the carrier's next edge */ + u32 sent; + /* receiving */ + int on, active, raw, full; + int c_level, p_level; /* the level written next, the input's since p_t */ + u64 c_t, p_t; /* their starts, in core cycles */ + u32 wr; /* entries written, from the channel's first */ + u32 apb; /* CHnDATA's word, from the channel's first */ +}; + +struct e32_rmt { + struct esk_mach *s; + struct esk_rf_periph *p; + struct esk_rf_reg *apb_conf, *raw, *st, *ena, *ram[NWORDS]; + struct ch ch[NCH]; + int clocked, level; +}; + +static u32 reg(const struct esk_rf_reg *r) { return (u32)r->value; } + +static void update(struct e32_rmt *k) +{ + u32 st = reg(k->raw) & reg(k->ena); + int level = st != 0; + esk_rf_hw(k->st, st); + if (level != k->level) { + k->level = level; + esk_esp32_source(k->s, SOURCE, level); + } +} + +static void raise(struct e32_rmt *k, u32 bits) +{ + esk_rf_hw(k->raw, reg(k->raw) | bits); + update(k); +} + +/* the channel's source clock period in fs: APB_CLK or REF_TICK */ +static double src_fs(const struct e32_rmt *k, const struct ch *c) +{ + u32 hz = (reg(c->conf1) & REF_ALWAYS_ON) ? esk_esp32_apb_hz(k->s) : REF_TICK_HZ; + return hz ? (double)FS_PER_S / (double)hz : 0; +} + +/* the channel clock's period in fs: DIV_CNT source cycles */ +static double tick_fs(const struct e32_rmt *k, const struct ch *c) +{ + u32 div = reg(c->conf0) & 0xffu; + return (div ? (double)div : 256.0) * src_fs(k, c); +} + +static u64 fs_per_cycle(const struct e32_rmt *k) +{ + u32 hz = esk_mach_core_hz(k->s); + return hz ? FS_PER_S / hz : 0; +} + +static u64 fs_of(double fs) { return fs <= 0 ? 0 : (u64)(fs + 0.5); } + +static u32 mem_size(const struct ch *c) +{ + u32 n = (reg(c->conf0) >> 24) & 15u; + return n ? n : 1u; +} + +static u32 entry(const struct e32_rmt *k, int n, u32 e) +{ + u32 w = (u32)BLOCK * (u32)n + e / 2u, v; + if (w >= NWORDS) + return 0; + v = reg(k->ram[w]); + return e & 1u ? v >> 16 : v & 0xffffu; +} + +static void status(struct e32_rmt *k, int n) +{ + struct ch *c = &k->ch[n]; + u32 raddr = (u32)BLOCK * (u32)n + c->e / 2u, waddr = (u32)BLOCK * (u32)n + (c->wr + 1u) / 2u; + u32 v = (waddr & 0x3ffu) | (raddr & 0x3ffu) << 12; + if (c->full) + v |= 1u << 28; + if (c->on && c->active && !(reg(c->conf1) & MEM_OWNER)) + v |= 1u << 27; + esk_rf_hw(c->status, v); + esk_rf_hw(c->addr, 0x3FF56800u + 4u * ((u32)BLOCK * (u32)n + c->apb)); +} + +/* ---- transmitting ------------------------------------------------------------ */ + +static void tx_drive(struct e32_rmt *k, int n) +{ + struct ch *c = &k->ch[n]; + int out = c->carrying ? c->cphase : c->level; + if (out != c->out) { + c->out = out; + esk_esp32_signal(k->s, SIG_OUT0 + n, out, 1); + } +} + +static u32 duty_half(const struct ch *c, int high) +{ + u32 v = high ? reg(c->duty) >> 16 : reg(c->duty) & 0xffffu; + return v ? v : 1u; +} + +/* the carrier for the output's present level: on (from its high half) or off */ +static void tx_carrier(struct e32_rmt *k, int n) +{ + struct ch *c = &k->ch[n]; + u32 c0 = reg(c->conf0); + int want = (c0 & CARRIER_EN) && c->busy && c->level == ((c0 & CARRIER_LV) != 0) && src_fs(k, c) > 0; + if (want && !c->carrying) { + c->carrying = 1; + c->cphase = 1; + c->cleft = fs_of((double)duty_half(c, 1) * src_fs(k, c)); + } else if (!want) { + c->carrying = 0; + } +} + +static void tx_idle(struct e32_rmt *k, int n, int marker_level) +{ + struct ch *c = &k->ch[n]; + u32 c1 = reg(c->conf1); + c->busy = 0; + c->level = (c1 & IDLE_EN) ? (c1 & IDLE_LV) != 0 : marker_level; + tx_carrier(k, n); + tx_drive(k, n); + status(k, n); +} + +/* the entry at c->e, after the one before ended: its level and period, or + * what an end marker or the memory's end does */ +static void tx_load(struct e32_rmt *k, int n) +{ + struct ch *c = &k->ch[n]; + u32 total = 2u * (u32)BLOCK * mem_size(c); + int restarts = 0; + for (;;) { + u32 v, period; + if (c->e >= total) { + if ((reg(k->apb_conf) & TX_WRAP) || (reg(c->conf1) & TX_CONTI)) { + c->e = 0; + } else { + raise(k, I_ERR(n)); + tx_idle(k, n, c->level); + return; + } + } + v = entry(k, n, c->e); + period = v & 0x7fffu; + if (period) { + c->level = (v >> 15) & 1u; + c->left = fs_of((double)period * tick_fs(k, c)); + if (!c->left) + c->left = 1; + tx_carrier(k, n); + tx_drive(k, n); + status(k, n); + return; + } + /* an end marker */ + if (!(reg(c->conf1) & TX_CONTI)) { + raise(k, I_TX_END(n)); + tx_idle(k, n, (int)((v >> 15) & 1u)); + return; + } + if (c->e == 0 || ++restarts > 1) { /* nothing but markers: nothing to send */ + raise(k, I_ERR(n)); + tx_idle(k, n, c->level); + return; + } + c->e = 0; + } +} + +static void tx_start(struct e32_rmt *k, int n) +{ + struct ch *c = &k->ch[n]; + if (src_fs(k, c) <= 0) + return; + c->busy = 1; + c->e = 0; + c->sent = 0; + c->carrying = 0; + tx_load(k, n); +} + +/* the entry ended: on to the next */ +static void tx_next(struct e32_rmt *k, int n) +{ + struct ch *c = &k->ch[n]; + c->e++; + if (!(c->e & 1u)) { /* a word sent */ + u32 lim = reg(c->lim) & 0x1ffu; + if (lim && ++c->sent >= lim) { + c->sent = 0; + raise(k, I_TX_THR(n)); + } + } + tx_load(k, n); +} + +/* ---- receiving ---------------------------------------------------------------- */ + +/* one entry into the memory: level and period */ +static void rx_write(struct e32_rmt *k, int n, int level, u32 period) +{ + struct ch *c = &k->ch[n]; + u32 total = 2u * (u32)BLOCK * mem_size(c), w; + if (c->full) + return; + if (!(reg(c->conf1) & MEM_OWNER)) { /* the CPU's: MEM_OWNER_ERR */ + status(k, n); + return; + } + if (c->wr >= total) { + c->full = 1; + c->active = 0; + raise(k, I_ERR(n)); + status(k, n); + return; + } + w = (u32)BLOCK * (u32)n + c->wr / 2u; + if (w < NWORDS) { + struct esk_rf_reg *cell = k->ram[w]; + u32 half = (period & 0x7fffu) | (u32)(level != 0) << 15; + esk_rf_hw(cell, c->wr & 1u ? (reg(cell) & 0xffffu) | half << 16 : (reg(cell) & 0xffff0000u) | half); + } + c->wr++; + status(k, n); +} + +static u32 rx_ticks(const struct e32_rmt *k, const struct ch *c, u64 cycles) +{ + double tf = tick_fs(k, c), t; + if (tf <= 0) + return 0; + t = (double)cycles * (double)fs_per_cycle(k) / tf + 0.5; + return t > 32767.0 ? 32767u : (u32)t; +} + +/* the receiver's idle threshold in core cycles */ +static u64 rx_idle_cycles(const struct e32_rmt *k, const struct ch *c) +{ + u64 fpc = fs_per_cycle(k); + double thres = (double)((reg(c->conf0) >> 8) & 0xffffu); + if (!fpc) + return 0; + return (u64)(thres * tick_fs(k, c) / (double)fpc) + 1u; +} + +/* a pulse from `from` to `to` (cycles) the filter drops */ +static int rx_drops(const struct e32_rmt *k, const struct ch *c, u64 from, u64 to) +{ + u32 apb = esk_esp32_apb_hz(k->s); + double len = (double)(to - from) * (double)fs_per_cycle(k); + return (reg(c->conf1) & FILTER_EN) && apb && + len < (double)((reg(c->conf1) >> 8) & 0xffu) * (double)FS_PER_S / (double)apb; +} + +static void rx_end(struct e32_rmt *k, int n) +{ + struct ch *c = &k->ch[n]; + if (c->p_level != c->c_level) { /* the last change held: it counts */ + rx_write(k, n, c->c_level, rx_ticks(k, c, c->p_t - c->c_t)); + c->c_level = c->p_level; + c->c_t = c->p_t; + } + rx_write(k, n, c->c_level, 0); + c->active = 0; + raise(k, I_RX_END(n)); + status(k, n); +} + +static void clocking(struct e32_rmt *k); + +/* the inputs changed: each receiver's edge at the time the change came */ +static void rx_watch(void *ctx) +{ + struct e32_rmt *k = (struct e32_rmt *)ctx; + struct esk_mach *s = k->s; + u64 lag = (u64)s->input_lead + s->output_lag, t = s->cycles > lag ? s->cycles - lag : 0; + int n; + for (n = 0; n < NCH; n++) { + struct ch *c = &k->ch[n]; + int level; + if (!c->on) + continue; + level = esk_esp32_signal_in(s, SIG_IN0 + n); + if (level == c->raw) + continue; + c->raw = level; + if (c->full) + continue; + if (!c->active) { /* the first edge starts it */ + c->active = 1; + c->c_level = c->p_level = level; + c->c_t = c->p_t = t; + status(k, n); + continue; + } + if (c->p_level != c->c_level) { + if (rx_drops(k, c, c->p_t, t)) { /* back as it was */ + c->p_level = c->c_level; + continue; + } + rx_write(k, n, c->c_level, rx_ticks(k, c, c->p_t - c->c_t)); + if (!c->active) + continue; + c->c_level = c->p_level; + c->c_t = c->p_t; + } + c->p_level = level; + c->p_t = t; + } + clocking(k); +} + +/* ---- time --------------------------------------------------------------------- */ + +static void clocking(struct e32_rmt *k) +{ + int n, on = 0; + for (n = 0; n < NCH; n++) + if (k->ch[n].busy || k->ch[n].carrying || k->ch[n].active) + on = 1; + esk_rf_clock(k->p, &k->clocked, on); +} + +/* fs until the channel's next edge, or 0 for none */ +static u64 tx_due(const struct ch *c) +{ + u64 d = 0; + if (c->busy) + d = c->left; + if (c->carrying && (!d || c->cleft < d)) + d = c->cleft; + return d; +} + +static void rmt_tick(void *ctx, u32 cycles) +{ + struct e32_rmt *k = (struct e32_rmt *)ctx; + struct esk_mach *s = k->s; + u64 fpc = fs_per_cycle(k), budget = (u64)cycles * fpc; + int n; + if (!fpc) + return; + for (;;) { + u64 d = 0; + for (n = 0; n < NCH; n++) { + u64 x = tx_due(&k->ch[n]); + if (x && (!d || x < d)) + d = x; + } + if (!d || d > budget) { + for (n = 0; n < NCH; n++) { + struct ch *c = &k->ch[n]; + if (c->busy) + c->left -= budget < c->left ? budget : c->left; + if (c->carrying) + c->cleft -= budget < c->cleft ? budget : c->cleft; + } + break; + } + budget -= d; + /* the edges switch at their time: this many cycles before now */ + s->output_lag = (u32)(budget / fpc); + for (n = 0; n < NCH; n++) { + struct ch *c = &k->ch[n]; + int ended = c->busy && c->left == d; + if (c->busy) + c->left -= d; + if (c->carrying) { + c->cleft -= d; + if (!c->cleft) { + c->cphase = !c->cphase; + c->cleft = fs_of((double)duty_half(c, c->cphase) * src_fs(k, c)); + if (!c->cleft) + c->cleft = 1; + if (!ended) + tx_drive(k, n); + } + } + if (ended) + tx_next(k, n); + } + s->output_lag = 0; + } + for (n = 0; n < NCH; n++) { + struct ch *c = &k->ch[n]; + u64 last = c->p_t > c->c_t ? c->p_t : c->c_t; + if (c->active && s->cycles >= last + rx_idle_cycles(k, c)) + rx_end(k, n); + } + clocking(k); +} + +static int rmt_next(void *ctx, u32 *cycles) +{ + struct e32_rmt *k = (struct e32_rmt *)ctx; + u64 fpc = fs_per_cycle(k), best = 0; + int n, any = 0; + if (!fpc) + return 0; + for (n = 0; n < NCH; n++) { + struct ch *c = &k->ch[n]; + u64 d = tx_due(c); + if (d) { + u64 x = (d + fpc - 1u) / fpc; + if (!any || x < best) + best = x; + any = 1; + } + if (c->active) { + u64 last = c->p_t > c->c_t ? c->p_t : c->c_t, at = last + rx_idle_cycles(k, c); + at = at > k->s->cycles ? at - k->s->cycles : 1u; + if (!any || at < best) + best = at; + any = 1; + } + } + if (!any) + return 0; + *cycles = best == 0 ? 1u : best > 0xffffffffu ? 0xffffffffu : (u32)best; + return 1; +} + +/* ---- registers ---------------------------------------------------------------- */ + +static u32 rmt_read(void *ctx, u32 off, int n) +{ + struct e32_rmt *k = (struct e32_rmt *)ctx; + u32 w = off & ~3u; + if (w < 0x20u && !(reg(k->apb_conf) & FIFO_MASK)) { /* CHnDATA: the channel's next word */ + int i = (int)(w / 4u); + struct ch *c = &k->ch[i]; + u32 at = (u32)BLOCK * (u32)i + c->apb, v = at < NWORDS ? reg(k->ram[at]) : 0; + if (!k->s->bus.debug) { + c->apb = (c->apb + 1u) % ((u32)BLOCK * mem_size(c)); + status(k, i); + } + return v >> (8u * (off & 3u)); + } + return esk_rf_read(k->p, off, n); +} + +static void conf1_write(struct e32_rmt *k, int n, u32 v, u32 was) +{ + struct ch *c = &k->ch[n]; + if (v & MEM_RD_RST) + c->e = 0; + if (v & APB_MEM_RST) + c->apb = 0; + if (v & MEM_WR_RST) { + c->wr = 0; + c->full = 0; + } + if ((v & RX_EN) && !(was & RX_EN)) { + c->on = 1; + c->active = 0; + c->full = 0; + c->raw = esk_esp32_signal_in(k->s, SIG_IN0 + n); + } else if (!(v & RX_EN)) { + c->on = 0; + c->active = 0; + } + if (!c->busy) /* the idle output as now configured */ + tx_idle(k, n, c->level); + if (v & TX_START) { + esk_rf_hw(c->conf1, reg(c->conf1) & ~TX_START); /* it clears itself */ + tx_start(k, n); + } + status(k, n); +} + +static void rmt_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_rmt *k = (struct e32_rmt *)ctx; + u32 w = off & ~3u; + int i; + if (w < 0x20u) { /* CHnDATA */ + if (!(reg(k->apb_conf) & FIFO_MASK)) { + struct ch *c = &k->ch[w / 4u]; + u32 at = (u32)BLOCK * (w / 4u) + c->apb; + if (at < NWORDS) + esk_rf_hw(k->ram[at], v); + c->apb = (c->apb + 1u) % ((u32)BLOCK * mem_size(c)); + status(k, (int)(w / 4u)); + } + return; + } + if (w == 0xACu) { /* INT_CLR */ + esk_rf_hw(k->raw, reg(k->raw) & ~v); + update(k); + return; + } + if ((w >= 0x60u && w < 0xA8u)) + return; /* STATUS, ADDR, INT_RAW and INT_ST are read-only */ + { + u32 was[NCH]; + for (i = 0; i < NCH; i++) + was[i] = reg(k->ch[i].conf1); + esk_rf_write(k->p, off, n, v); + if (w == 0xA8u) /* INT_ENA */ + update(k); + for (i = 0; i < NCH; i++) + if (w == esk_rf_off(k->ch[i].conf1)) + conf1_write(k, i, reg(k->ch[i].conf1), was[i]); + } + clocking(k); +} + +static void rmt_reset(void *ctx) +{ + struct e32_rmt *k = (struct e32_rmt *)ctx; + int i; + for (i = 0; i < NCH; i++) { + struct ch *c = &k->ch[i]; + struct ch keep = *c; + memset(c, 0, sizeof *c); + c->conf0 = keep.conf0; + c->conf1 = keep.conf1; + c->status = keep.status; + c->addr = keep.addr; + c->duty = keep.duty; + c->lim = keep.lim; + c->out = -1; + } + k->level = 0; + esk_esp32_source(k->s, SOURCE, 0); + k->clocked = 0; + for (i = 0; i < NCH; i++) { + tx_idle(k, i, 0); + k->ch[i].raw = esk_esp32_signal_in(k->s, SIG_IN0 + i); + } + update(k); + clocking(k); +} + +const struct esk_dev_ops esk_esp32_rmt_ops = { + "esp32-rmt", rmt_read, rmt_write, rmt_reset, rmt_tick, rmt_next, +}; + +void *esk_esp32_rmt_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_rmt *k = (struct e32_rmt *)esk_mach_alloc(s, sizeof *k); + char name[24]; + int i; + if (!k) + return 0; + memset(k, 0, sizeof *k); + k->s = s; + k->p = p; + k->apb_conf = esk_rf_reg(p, "APB_CONF"); + k->raw = esk_rf_reg(p, "INT_RAW"); + k->st = esk_rf_reg(p, "INT_ST"); + k->ena = esk_rf_reg(p, "INT_ENA"); + if (!k->apb_conf || !k->raw || !k->st || !k->ena) + return 0; + for (i = 0; i < NCH; i++) { + struct ch *c = &k->ch[i]; + snprintf(name, sizeof name, "CH%dCONF0", i); + c->conf0 = esk_rf_reg(p, name); + snprintf(name, sizeof name, "CH%dCONF1", i); + c->conf1 = esk_rf_reg(p, name); + snprintf(name, sizeof name, "CH%dSTATUS", i); + c->status = esk_rf_reg(p, name); + snprintf(name, sizeof name, "CH%dADDR", i); + c->addr = esk_rf_reg(p, name); + snprintf(name, sizeof name, "CH%dCARRIER_DUTY", i); + c->duty = esk_rf_reg(p, name); + snprintf(name, sizeof name, "CH%d_TX_LIM", i); + c->lim = esk_rf_reg(p, name); + if (!c->conf0 || !c->conf1 || !c->status || !c->addr || !c->duty || !c->lim) + return 0; + } + for (i = 0; i < NWORDS; i++) { + snprintf(name, sizeof name, "RAM%d", i); + if (!(k->ram[i] = esk_rf_reg(p, name))) + return 0; + } + if (esk_esp32_signal_watch(s, rx_watch, k) != 0) + return 0; + return k; +} diff --git a/core/mcu/models.c b/core/mcu/models.c index 52c983242..0f603f9be 100644 --- a/core/mcu/models.c +++ b/core/mcu/models.c @@ -73,6 +73,7 @@ static const struct esk_rf_model_type model_types[] = { { "esp32-sha", &esk_esp32_sha_ops, esk_esp32_sha_create }, { "esp32-ledc", &esk_esp32_ledc_ops, esk_esp32_ledc_create }, { "esp32-i2c", &esk_esp32_i2c_ops, esk_esp32_i2c_create }, + { "esp32-rmt", &esk_esp32_rmt_ops, esk_esp32_rmt_create }, { "esp32-iomux", &esk_esp32_iomux_ops, esk_esp32_iomux_create }, { "esp32c3-intmtx", &esk_esp32c3_intmtx_ops, esk_esp32c3_intmtx_create }, { "esp32c3-uart", &esk_esp32c3_uart_ops, esk_esp32c3_uart_create }, diff --git a/docs/STATUS.md b/docs/STATUS.md index 37798483c..41b396e1c 100644 --- a/docs/STATUS.md +++ b/docs/STATUS.md @@ -17,9 +17,10 @@ and through `esp_restart` (rst:0xc SW_CPU_RESET). Evidence: `test_lx6` scenarios `esp32_hello_world` (9/9), `esp32_blink` (6/6), `esp32_ledc_basic` (2/2), `esp32_i2c_eeprom` (3/3, I2C0 writing and reading a 24LC256 at 400 kHz), `esp32_gptimer` (17/17), `esp32_uart_echo` -(6/6) and `esp32_real_time_stats` (10/10). Not yet: Wi-Fi and Bluetooth, the +(6/6), `esp32_real_time_stats` (10/10) and `esp32_blink_strip` (7/7, a +WS2812B through the RMT). Not yet: Wi-Fi and Bluetooth, the double-precision accelerator's instructions, the peripherals the -description's fidelity lists (I2S, SPI2/3, RMT, ADC, ...), +description's fidelity lists (I2S, SPI2/3, ADC, ...), sleep. The standalone harness below remains as its own qualification fixtures. diff --git a/docs/coverage.md b/docs/coverage.md index 99d40d33f..8245e8da3 100644 --- a/docs/coverage.md +++ b/docs/coverage.md @@ -8,7 +8,7 @@ evidence for each model is in [STATUS.md](STATUS.md). | MCU | Modelled | Registers only | Missing | Peripherals | |---|---|---|---|---| -| ESP32 | 17 | 0 | 28 | 45 | +| ESP32 | 18 | 0 | 27 | 45 | | ESP32-C3 | 35 | 0 | 0 | 35 | | ATmega328P | 15 | 0 | 0 | 15 | | PIC24FJ1024GB610 | 11 | 4 | 17 | 32 | @@ -23,7 +23,7 @@ evidence for each model is in [STATUS.md](STATUS.md). ## ESP32 (`espressif/esp32`) Boards: ESP32-DevKitC V4. -17 of 45 peripherals modelled, 0 registers only, 28 missing. +18 of 45 peripherals modelled, 0 registers only, 27 missing. | Peripheral | Model | State | |---|---|---| @@ -50,7 +50,7 @@ Boards: ESP32-DevKitC V4. | I2C0 | `esp32-i2c` | modelled | | UHCI0 | — | **missing** | | SLCHOST | — | **missing** | -| RMT | — | **missing** | +| RMT | `esp32-rmt` | modelled | | PCNT | — | **missing** | | SLC | — | **missing** | | LEDC | `esp32-ledc` | modelled | @@ -73,7 +73,7 @@ Boards: ESP32-DevKitC V4. | I2S1 | — | **missing** | | UART2 | `esp32-uart` | modelled | -Declared omissions: Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written); the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept; PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts; I2C: the non-FIFO mode (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, the input filters (only their share of the SCL high time), 10-bit addressing's R/W check; the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), RMT, MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption; sleep modes (light and deep sleep, the power domains), brown-out; the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection. +Declared omissions: Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written); the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept; PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts; RMT: the memory's power-down (MEM_PD), STATUS's STATE and the APB-side error bits, the carrier on an idle output; I2C: the non-FIFO mode (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, the input filters (only their share of the SCL high time), 10-bit addressing's R/W check; the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption; sleep modes (light and deep sleep, the power domains), brown-out; the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection. ## ESP32-C3 (`espressif/esp32c3`) diff --git a/tests/vendor/esp-idf/examples/esp32_blink_strip/project.json b/tests/vendor/esp-idf/examples/esp32_blink_strip/project.json new file mode 100644 index 000000000..f56d3b192 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_blink_strip/project.json @@ -0,0 +1,100 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "esp-idf-esp32_blink_strip", + "description": "ESP-IDF's get-started/blink with its LED-strip option on the ESP32-DevKitC V4 (sdkconfig.defaults: CONFIG_BLINK_LED_STRIP, the RMT backend, GPIO18): a WS2812B on IO18, powered from the board's 5 V through a 1N4007, a common way to drive one from 3.3 V logic: the diode's drop at the LED's supply current lowers VDD to about 4.2 V, and with it the input's high threshold (0.7 VDD) below the ESP32's 3.3 V. The part's model draws no supply current (its fidelity says so), so here the diode carries none and LED_VDD reads the board's 5 V net.", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + }, + { + "id": "D1", + "component": "emblink/diode_1n4007", + "layout": { + "x": 120, + "y": 460 + } + }, + { + "id": "LED1", + "component": "emblink/ws2812b", + "layout": { + "x": 120, + "y": 560 + } + } + ], + "nets": { + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1", + "LED1.GND" + ], + "USB5V": [ + "USB.+", + "B1.VBUS" + ], + "5V": [ + "B1.5V", + "D1.A" + ], + "LED_VDD": [ + "D1.K", + "LED1.VDD" + ], + "DATA": [ + "B1.IO18", + "LED1.DIN" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + }, + { + "id": "led", + "target": "output:LED1.color", + "kind": "value" + }, + { + "id": "frames", + "target": "output:LED1.frames", + "kind": "value" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_blink_strip/scenario.json b/tests/vendor/esp-idf/examples/esp32_blink_strip/scenario.json new file mode 100644 index 000000000..89de6eef0 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_blink_strip/scenario.json @@ -0,0 +1,66 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "esp32_blink_strip", + "until": "3900ms", + "description": "blink with the LED strip on the ESP32: the RMT (channel 0, 10 MHz from APB_CLK, through the matrix's rmt_sig_out0) sends the WS2812B white at 16/255 for one second, then black, and again; the console says each. Five frames by 3.8 s: the clear when the strip is configured, then OFF, ON, OFF, ON.", + "inputs": [], + "assertions": [ + { + "id": "strip", + "at": "1s", + "probe": "console", + "expect": { + "contains": "Example configured to blink addressable LED!" + } + }, + { + "id": "off-first", + "at": "1s", + "probe": "led", + "expect": { + "equals": "#000000" + } + }, + { + "id": "on", + "at": "1800ms", + "probe": "led", + "expect": { + "equals": "#101010" + } + }, + { + "id": "off", + "at": "2800ms", + "probe": "led", + "expect": { + "equals": "#000000" + } + }, + { + "id": "on-again", + "at": "3800ms", + "probe": "led", + "expect": { + "equals": "#101010" + } + }, + { + "id": "frames", + "at": "3800ms", + "probe": "frames", + "expect": { + "equals": 5 + } + }, + { + "id": "said", + "at": "3800ms", + "probe": "console", + "expect": { + "contains": "Turning the LED ON!" + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_blink_strip/sdkconfig.defaults b/tests/vendor/esp-idf/examples/esp32_blink_strip/sdkconfig.defaults new file mode 100644 index 000000000..4557fd979 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_blink_strip/sdkconfig.defaults @@ -0,0 +1,3 @@ +CONFIG_BLINK_LED_STRIP=y +CONFIG_BLINK_LED_STRIP_BACKEND_RMT=y +CONFIG_BLINK_GPIO=18 diff --git a/tests/vendor/esp-idf/run.py b/tests/vendor/esp-idf/run.py index 63712fede..4c8d9c818 100644 --- a/tests/vendor/esp-idf/run.py +++ b/tests/vendor/esp-idf/run.py @@ -78,6 +78,7 @@ "esp32_gptimer": "examples/peripherals/timer_group/gptimer", "esp32_uart_echo": "examples/peripherals/uart/uart_echo", "esp32_real_time_stats": "examples/system/freertos/real_time_stats", + "esp32_blink_strip": "examples/get-started/blink", } # the target an example is built for, when not the ESP32-C3 (its board in # examples//project.json), and the toolchain that target needs @@ -89,6 +90,7 @@ "esp32_gptimer": "esp32", "esp32_uart_echo": "esp32", "esp32_real_time_stats": "esp32", + "esp32_blink_strip": "esp32", } TOOLCHAINS = {"esp32c3": "riscv32-esp-elf-gcc", "esp32": "xtensa-esp32-elf-gcc"} # examples built only for another's project (with examples//'s From 9d2d90415f40adee89885cd8977f419880a82731 Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 04:57:00 +0000 Subject: [PATCH 12/16] ESP32: the SAR ADCs, with ESP-IDF's adc oneshot_read SENS's RTC controller's one-shot conversions on ADC1 (GPIO36-39, 32-35) and ADC2 (GPIO4, 0, 2, 15, 13, 12, 14, 27, 25, 26): MEAS1/2_START_SAR, the attenuation per channel, 9 to 12 bits, the converter's inverted output and DATA_INV, DONE after the conversion's SAR clocks. The transfer is the line ESP-IDF's Vref calibration fits for the chip, with the chip's eFuse Vref, so the calibrated voltage matches the pin's. ESP-IDF's adc/oneshot_read runs unmodified on the DevKitC with three sources (esp32_adc_oneshot_read 6/6: 1118 for 1.1 V, 2402 for 2.2 V, 433 for 0.5 V on ADC2). --- CHANGELOG.md | 6 +- catalog/mcus/espressif/esp32/mcu.json | 19 +- core/mcu/esp32/soc/adc.c | 204 ++++++++++++++++++ core/mcu/esp32/soc/esp32.h | 3 + core/mcu/models.c | 1 + docs/STATUS.md | 7 +- docs/coverage.md | 8 +- .../esp32_adc_oneshot_read/project.json | 112 ++++++++++ .../esp32_adc_oneshot_read/scenario.json | 58 +++++ tests/vendor/esp-idf/run.py | 2 + 10 files changed, 405 insertions(+), 15 deletions(-) create mode 100644 core/mcu/esp32/soc/adc.c create mode 100644 tests/vendor/esp-idf/examples/esp32_adc_oneshot_read/project.json create mode 100644 tests/vendor/esp-idf/examples/esp32_adc_oneshot_read/scenario.json diff --git a/CHANGELOG.md b/CHANGELOG.md index d4a82d03a..feef4881f 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -21,7 +21,8 @@ versions follow semantic versioning. There is no release yet. interrupt matrix), RTC_CNTL, eFuse, APB_CTRL clocks, GPIO/IO_MUX with strapping, UART0-2, TIMG0/1, SPI0/1 with the GT25Q32A flash, SHA, LEDC, I2C0/1 (master and slave, 16 commands, APB_CLK timing; DPORT's - PERIP_RST_EN resets them), the RMT's eight channels, the internal analog I2C, RNG and the AHB view. + PERIP_RST_EN resets them), the RMT's eight channels, the SAR ADCs + through SENS, the internal analog I2C, RNG and the AHB view. - Added the `emblink/esp32_devkitc` board (ESP32-DevKitC V4, WROOM-32E) with its power path, LED, Boot and EN buttons, headers and fixtures. - Espressif's ROM, ESP-IDF v5.4's bootloader and hello_world run unmodified @@ -29,7 +30,8 @@ versions follow semantic versioning. There is no release yet. `esp32_blink` 6/6, `esp32_ledc_basic` 2/2, `esp32_i2c_eeprom` 3/3 on a 24LC256, `esp32_gptimer` 17/17, `esp32_uart_echo` 6/6 on UART2, `esp32_real_time_stats` 10/10 across both cores, - `esp32_blink_strip` 7/7 on a WS2812B through the RMT; the UARTs keep + `esp32_blink_strip` 7/7 on a WS2812B through the RMT, + `esp32_adc_oneshot_read` 6/6 with the eFuse Vref's calibration; the UARTs keep MEM_RX_STATUS's addresses, from which ESP-IDF counts the bytes waiting); `test_lx6` checks the core with programs from Espressif's assembler. ### Original ESP32 digital per-pin hold diff --git a/catalog/mcus/espressif/esp32/mcu.json b/catalog/mcus/espressif/esp32/mcu.json index 587b267dc..b97f0ba30 100644 --- a/catalog/mcus/espressif/esp32/mcu.json +++ b/catalog/mcus/espressif/esp32/mcu.json @@ -203,6 +203,10 @@ { "match": "RMT", "model": "esp32-rmt" + }, + { + "match": "SENS", + "model": "esp32-sens" } ], "io": { @@ -271,14 +275,15 @@ }, "fidelity": { "functional": { - "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts, MEM_RX_STATUS's addresses that ESP-IDF counts the bytes waiting from), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), I2C0 and I2C1 (master and slave on the open-drain lines through the matrix, the 16 commands with RSTART, WRITE, READ, STOP and END, the bus timing in APB_CLK cycles, ACK checks, arbitration, the SCL timeout, the 32-byte FIFOs through DATA and its AHB view, 7- and 10-bit slave addresses; ESP-IDF's i2c_eeprom runs on a 24LC256), the RMT (eight channels sending or receiving through the matrix, 64-word blocks of the 512-word RAM, end markers, continuous mode, wrap, TX_LIM's threshold, the carrier, the receiver's idle threshold and filter, the RAM through CHnDATA; ESP-IDF's led_strip lights a WS2812B), PERIP_RST_EN's resets of I2C0, I2C1 and LEDC, the internal analog I2C master, the random number generator and the peripherals' AHB view. The evidence: test_lx6.c's programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16) and the APP_CPU's ROM data kept apart; ESP-IDF v5.4's hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats and blink with its LED strip built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart; the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin.", + "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts, MEM_RX_STATUS's addresses that ESP-IDF counts the bytes waiting from), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), I2C0 and I2C1 (master and slave on the open-drain lines through the matrix, the 16 commands with RSTART, WRITE, READ, STOP and END, the bus timing in APB_CLK cycles, ACK checks, arbitration, the SCL timeout, the 32-byte FIFOs through DATA and its AHB view, 7- and 10-bit slave addresses; ESP-IDF's i2c_eeprom runs on a 24LC256), the RMT (eight channels sending or receiving through the matrix, 64-word blocks of the 512-word RAM, end markers, continuous mode, wrap, TX_LIM's threshold, the carrier, the receiver's idle threshold and filter, the RAM through CHnDATA; ESP-IDF's led_strip lights a WS2812B), the SAR ADCs as SENS's RTC controller drives them (one conversion at a time on ADC1's eight and ADC2's ten pads, the attenuations, 9 to 12 bits, the converter's inverted output and DATA_INV, the conversion's time; the transfer the line ESP-IDF's Vref calibration fits for the chip, its eFuse Vref), PERIP_RST_EN's resets of I2C0, I2C1 and LEDC, the internal analog I2C master, the random number generator and the peripherals' AHB view. The evidence: test_lx6.c's programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16) and the APP_CPU's ROM data kept apart; ESP-IDF v5.4's hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats, blink with its LED strip and adc oneshot_read built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart; the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin.", "omissions": [ "Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written)", "the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept", "PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts", "RMT: the memory's power-down (MEM_PD), STATUS's STATE and the APB-side error bits, the carrier on an idle output", + "the SAR ADCs: the nonlinearity above about 2450 mV at 11 dB and a chip's spread from the fitted line, noise, the ULP's and the digital controller's (DMA, I2S) conversions, the Hall sensor, ADC2's arbitration with Wi-Fi, the RTC IO MUX's routing of a pad to the ADC (not checked)", "I2C: the non-FIFO mode (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, the input filters (only their share of the SCL high time), 10-bit addressing's R/W check", - "the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption", + "the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption", "sleep modes (light and deep sleep, the power domains), brown-out", "the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection" ], @@ -292,7 +297,8 @@ "repo:tests/vendor/esp-idf/examples/esp32_gptimer/scenario.json", "repo:tests/vendor/esp-idf/examples/esp32_uart_echo/scenario.json", "repo:tests/vendor/esp-idf/examples/esp32_real_time_stats/scenario.json", - "repo:tests/vendor/esp-idf/examples/esp32_blink_strip/scenario.json" + "repo:tests/vendor/esp-idf/examples/esp32_blink_strip/scenario.json", + "repo:tests/vendor/esp-idf/examples/esp32_adc_oneshot_read/scenario.json" ] }, "timed": { @@ -398,18 +404,19 @@ }, "i18n": { "fr": { - "source": "f8310c3fa74c", + "source": "bff3ddeda639", "description": "Espressif ESP32 (ESP32-D0WD-V3, révision de puce v3.1) : deux cœurs Xtensa LX6 jusqu'à 240 MHz, 520 Kio de SRAM, 448 Kio de ROM, 16 Kio de mémoire RTC, une flash SPI externe derrière les caches des cœurs, Wi-Fi et Bluetooth ; le MCU de l'ESP32-DevKitC. La ROM d'Espressif, le bootloader de second niveau d'ESP-IDF et les applications ESP-IDF tournent sur les deux cœurs ; les radios ne sont pas encore modélisées.", "fidelity": { "functional": { - "claims": "Les deux cœurs Xtensa LX6 (mcu/xtensa/lx6.c, lx6fp.c) tels que les configure le core-isa.h d'Espressif : les instructions de base et de densité, les registres fenêtrés (64, le contrôle de débordement de chaque instruction, CALL4/8/12, ENTRY, RETW et son sous-débordement, MOVSP, ROTW, L32E/S32E), les boucles sans surcoût, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, les booléens, S32C1I avec SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), le paquet MAC16, la FPU simple précision (modes d'arrondi et drapeaux IEEE ; les séquences de division et de racine carrée qu'exécute libgcc donnent des résultats correctement arrondis), les exceptions XEA2 avec vecteurs relocalisables, 32 interruptions aux niveaux et types de core-isa.h (niveau, front, logicielles, les temporisateurs CCOMPARE0-2 contre CCOUNT, NMI), RSIL, WAITI, RFI, BREAK, IBREAK, DBREAK et ICOUNT de l'option de débogage, la protection par régions (huit régions de 512 Mo, 15 sans accès), les chargements et écritures non alignés, et les accès de données en 32 bits seulement du bus d'instructions. Les deux cœurs partagent la machine, l'APP_CPU maintenu en reset jusqu'à ce que DPORT le libère et voyant la ROM avec ses pointeurs vers les données ROM du PRO_CPU déplacés vers les siennes, comme dans l'image ROM APP_CPU d'Espressif. Le démarrage : la ROM d'Espressif (esp32_rev300_rom.elf, révision v3) depuis le vecteur de reset, sa bannière, les broches de configuration (GPIO_STRAP : SPI_FAST_FLASH_BOOT, ou le mode téléchargement avec GPIO0 bas), les causes de reset (RTC_CNTL), le contrôle anti-glitch de l'eFuse, la lecture de la flash par SPI1, le bootloader de second niveau d'ESP-IDF et sa vérification d'image sur l'accélérateur SHA, la MMU flash des caches, et l'application sur les deux cœurs. Les modèles : DPORT (reset, horloge et blocage de l'APP_CPU, CPU_PER_CONF, vidage et état des caches, tables de la MMU flash, les 69 sources de la matrice d'interruptions, les interruptions inter-CPU), RTC_CNTL (causes de reset, le temporisateur RTC, le chien de garde RTC avec sa protection au démarrage sur flash, les resets et blocages logiciels, les registres de stockage, SOC_CLK_SEL), APB_CTRL (les horloges CPU et APB depuis XTAL, PLL ou RC_FAST), le contrôleur eFuse avec les bits d'usine de la puce (ESP32-D0WD-V3 v3.1, une MAC avec son CRC, ou celle des réglages de la carte), GPIO et IO_MUX (40 plots, la matrice, tirages, drain ouvert, interruptions sur chaque CPU, le verrou de configuration), UART0-2 (FIFO, trames au débit, interruptions, les adresses de MEM_RX_STATUS d'après lesquelles ESP-IDF compte les octets en attente), TIMG0/1 (T0, T1, le temporisateur LAC, le MWDT avec sa protection au démarrage sur flash, la calibration de RTC_SLOW_CLK), SPI0/SPI1 avec la flash Giantec GT25Q32A du module (C4 60 16, l'identifiant que rapporte la carte du propriétaire), l'accélérateur SHA (SHA-1, -256, -384, -512), LEDC (huit canaux MLI rapides et huit lents sur huit temporisateurs, le fondu, sur ledc_hs/ls_sig_out de la matrice), I2C0 et I2C1 (maître et esclave sur les lignes à drain ouvert à travers la matrice, les 16 commandes avec RSTART, WRITE, READ, STOP et END, le timing du bus en cycles d'APB_CLK, les contrôles d'ACK, l'arbitrage, le délai d'attente sur SCL, les FIFO de 32 octets par DATA et sa vue AHB, les adresses esclaves sur 7 et 10 bits ; l'exemple i2c_eeprom d'ESP-IDF fonctionne avec une 24LC256), le RMT (huit canaux qui émettent ou reçoivent à travers la matrice, des blocs de 64 mots de la RAM de 512 mots, les marqueurs de fin, le mode continu, le rebouclage, le seuil de TX_LIM, la porteuse, le seuil d'inactivité et le filtre du récepteur, la RAM par CHnDATA ; le led_strip d'ESP-IDF allume une WS2812B), les resets de PERIP_RST_EN pour I2C0, I2C1 et LEDC, le maître I2C analogique interne, le générateur de nombres aléatoires et la vue AHB des périphériques. Les preuves : les programmes de test_lx6.c assemblés par l'assembleur d'Espressif (entiers, décalages, multiplication et division, boucles, branchements, mémoire avec S32C1I, récursion fenêtrée à travers les vecteurs de fenêtre de la ROM, SYSCALL, l'interruption du temporisateur CCOMPARE, FPU, MAC16) et les données ROM de l'APP_CPU tenues à part ; hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats et blink avec son ruban de LED d'ESP-IDF v5.4 compilés sans modification pour la cible esp32 sur l'ESP32-DevKitC V4, de la bannière de la ROM jusqu'à esp_restart ; l'image ROM est identique octet pour octet à l'esp32-v3-rom.bin du QEMU d'Espressif, et la vue qu'en a l'APP_CPU à son esp32-v3-rom-app.bin.", + "claims": "Les deux cœurs Xtensa LX6 (mcu/xtensa/lx6.c, lx6fp.c) tels que les configure le core-isa.h d'Espressif : les instructions de base et de densité, les registres fenêtrés (64, le contrôle de débordement de chaque instruction, CALL4/8/12, ENTRY, RETW et son sous-débordement, MOVSP, ROTW, L32E/S32E), les boucles sans surcoût, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, les booléens, S32C1I avec SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), le paquet MAC16, la FPU simple précision (modes d'arrondi et drapeaux IEEE ; les séquences de division et de racine carrée qu'exécute libgcc donnent des résultats correctement arrondis), les exceptions XEA2 avec vecteurs relocalisables, 32 interruptions aux niveaux et types de core-isa.h (niveau, front, logicielles, les temporisateurs CCOMPARE0-2 contre CCOUNT, NMI), RSIL, WAITI, RFI, BREAK, IBREAK, DBREAK et ICOUNT de l'option de débogage, la protection par régions (huit régions de 512 Mo, 15 sans accès), les chargements et écritures non alignés, et les accès de données en 32 bits seulement du bus d'instructions. Les deux cœurs partagent la machine, l'APP_CPU maintenu en reset jusqu'à ce que DPORT le libère et voyant la ROM avec ses pointeurs vers les données ROM du PRO_CPU déplacés vers les siennes, comme dans l'image ROM APP_CPU d'Espressif. Le démarrage : la ROM d'Espressif (esp32_rev300_rom.elf, révision v3) depuis le vecteur de reset, sa bannière, les broches de configuration (GPIO_STRAP : SPI_FAST_FLASH_BOOT, ou le mode téléchargement avec GPIO0 bas), les causes de reset (RTC_CNTL), le contrôle anti-glitch de l'eFuse, la lecture de la flash par SPI1, le bootloader de second niveau d'ESP-IDF et sa vérification d'image sur l'accélérateur SHA, la MMU flash des caches, et l'application sur les deux cœurs. Les modèles : DPORT (reset, horloge et blocage de l'APP_CPU, CPU_PER_CONF, vidage et état des caches, tables de la MMU flash, les 69 sources de la matrice d'interruptions, les interruptions inter-CPU), RTC_CNTL (causes de reset, le temporisateur RTC, le chien de garde RTC avec sa protection au démarrage sur flash, les resets et blocages logiciels, les registres de stockage, SOC_CLK_SEL), APB_CTRL (les horloges CPU et APB depuis XTAL, PLL ou RC_FAST), le contrôleur eFuse avec les bits d'usine de la puce (ESP32-D0WD-V3 v3.1, une MAC avec son CRC, ou celle des réglages de la carte), GPIO et IO_MUX (40 plots, la matrice, tirages, drain ouvert, interruptions sur chaque CPU, le verrou de configuration), UART0-2 (FIFO, trames au débit, interruptions, les adresses de MEM_RX_STATUS d'après lesquelles ESP-IDF compte les octets en attente), TIMG0/1 (T0, T1, le temporisateur LAC, le MWDT avec sa protection au démarrage sur flash, la calibration de RTC_SLOW_CLK), SPI0/SPI1 avec la flash Giantec GT25Q32A du module (C4 60 16, l'identifiant que rapporte la carte du propriétaire), l'accélérateur SHA (SHA-1, -256, -384, -512), LEDC (huit canaux MLI rapides et huit lents sur huit temporisateurs, le fondu, sur ledc_hs/ls_sig_out de la matrice), I2C0 et I2C1 (maître et esclave sur les lignes à drain ouvert à travers la matrice, les 16 commandes avec RSTART, WRITE, READ, STOP et END, le timing du bus en cycles d'APB_CLK, les contrôles d'ACK, l'arbitrage, le délai d'attente sur SCL, les FIFO de 32 octets par DATA et sa vue AHB, les adresses esclaves sur 7 et 10 bits ; l'exemple i2c_eeprom d'ESP-IDF fonctionne avec une 24LC256), le RMT (huit canaux qui émettent ou reçoivent à travers la matrice, des blocs de 64 mots de la RAM de 512 mots, les marqueurs de fin, le mode continu, le rebouclage, le seuil de TX_LIM, la porteuse, le seuil d'inactivité et le filtre du récepteur, la RAM par CHnDATA ; le led_strip d'ESP-IDF allume une WS2812B), les ADC SAR tels que les pilote le contrôleur RTC de SENS (une conversion à la fois sur les huit plots de l'ADC1 et les dix de l'ADC2, les atténuations, 9 à 12 bits, la sortie inversée du convertisseur et DATA_INV, la durée de la conversion ; la caractéristique est la droite que la calibration Vref d'ESP-IDF ajuste pour la puce, avec son Vref d'eFuse), les resets de PERIP_RST_EN pour I2C0, I2C1 et LEDC, le maître I2C analogique interne, le générateur de nombres aléatoires et la vue AHB des périphériques. Les preuves : les programmes de test_lx6.c assemblés par l'assembleur d'Espressif (entiers, décalages, multiplication et division, boucles, branchements, mémoire avec S32C1I, récursion fenêtrée à travers les vecteurs de fenêtre de la ROM, SYSCALL, l'interruption du temporisateur CCOMPARE, FPU, MAC16) et les données ROM de l'APP_CPU tenues à part ; hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats, blink avec son ruban de LED et adc oneshot_read d'ESP-IDF v5.4 compilés sans modification pour la cible esp32 sur l'ESP32-DevKitC V4, de la bannière de la ROM jusqu'à esp_restart ; l'image ROM est identique octet pour octet à l'esp32-v3-rom.bin du QEMU d'Espressif, et la vue qu'en a l'APP_CPU à son esp32-v3-rom-app.bin.", "omissions": [ "le Wi-Fi, le Bluetooth et l'étage RF (WIFI_MAC, BB, NRX, FE : leurs registres gardent ce qui y est écrit)", "les instructions de l'accélérateur double précision (F64ADDC, F64ITER et les autres : leurs encodages sont publics, pas ce qu'elles font ; un programme qui en exécute une s'arrête avec un diagnostic), bien que ses registres soient conservés", "la PSRAM (DRAM1), le remappage de démarrage, les permissions d'accès APB/AHB, les régions verrouillées et le timing des caches (les pages mappées sont lues entières), les interruptions d'erreur d'accès de la MMU", "RMT : la mise hors tension de la mémoire (MEM_PD), le champ STATE de STATUS et les bits d'erreur côté APB, la porteuse sur une sortie inactive", + "les ADC SAR : la non-linéarité au-delà d'environ 2450 mV à 11 dB et l'écart d'une puce à la droite ajustée, le bruit, les conversions de l'ULP et du contrôleur numérique (DMA, I2S), le capteur à effet Hall, l'arbitrage de l'ADC2 avec le Wi-Fi, le routage d'un plot vers l'ADC par l'IO MUX RTC (non vérifié)", "I2C : le mode hors FIFO (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, les filtres d'entrée (seulement leur part du temps haut de SCL), le contrôle R/W de l'adressage sur 10 bits", - "les périphériques sans modèle pour l'instant : I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, les ADC SAR, les DAC, le capteur tactile, l'IO MUX RTC et le coprocesseur ULP, les accélérateurs AES et RSA, le chiffrement de la flash", + "les périphériques sans modèle pour l'instant : I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, les DAC, le capteur tactile, l'IO MUX RTC et le coprocesseur ULP, les accélérateurs AES et RSA, le chiffrement de la flash", "les modes de veille (veille légère et profonde, les domaines d'alimentation), la détection de baisse de tension", "le contrôle du schéma de codage 3/4 de l'eFuse, la protection en écriture par champ du BLOCK0" ] diff --git a/core/mcu/esp32/soc/adc.c b/core/mcu/esp32/soc/adc.c new file mode 100644 index 000000000..2400152b0 --- /dev/null +++ b/core/mcu/esp32/soc/adc.c @@ -0,0 +1,204 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* adc.c -- the ESP32's SAR ADCs as the RTC controller drives them (SENS, + * TRM v5 chapter 29): one conversion at a time on SAR ADC1 or ADC2, as + * ESP-IDF's adc_oneshot and Arduino's analogRead use them. + * + * - ADC1 reads GPIO36, 37, 38, 39, 32, 33, 34, 35 (channels 0-7), ADC2 + * GPIO4, 0, 2, 15, 13, 12, 14, 27, 25, 26 (channels 0-9). + * - MEAS1_START_SAR (SAR_MEAS_START1) rising starts a conversion of the + * channel SAR1_EN_PAD selects (its lowest bit set), at SAR_ATTEN1's + * attenuation for it (two bits a channel: 0, 2.5, 6, 11 dB); MEAS1_DONE_SAR + * reads 0 until (SAR1_SAMPLE_CYCLE + bits + 1) SAR clocks have passed + * (RTC_FAST_CLK's 8 MHz divided by SAR1_CLK_DIV), then 1, with the code + * in MEAS1_DATA_SAR; a new start clears it. ADC2 the same with + * SAR_MEAS_START2, SAR_ATTEN2 and SAR_READ_CTRL2. + * - The code is SAR1_SAMPLE_BIT's 9 to 12 bits wide (the 12-bit code + * shifted down). The converter's own output is inverted; SAR1_DATA_INV + * (SAR2_DATA_INV) set, as ESP-IDF sets it, gives the code itself. + * - The transfer: the line ESP-IDF's Vref calibration fits for the chip + * (esp_adc's adc_cali_line_fitting.c, from Espressif's + * characterisation of the ESP32): V = a code / 65536 + b mV, with a = + * Vref x scale / 4096, scale and b per unit and attenuation (ADC1: + * 57431, 76236, 105481, 196602 and 75, 78, 107, 142 mV; ADC2: 57236, + * 76175, 105678, 197170 and 63, 66, 89, 128 mV), Vref the chip's eFuse + * ADC_VREF (1100 mV + 7 mV a step); a voltage below b reads 0, one past + * the range 4095. ESP-IDF's calibrated voltage is so the pin's within + * its rounding. + * Where it differs inside: the RTC IO MUX's routing of a pad to the ADC + * (RTC_IO's ADC pad and FUN_SEL bits) is not checked: the pad's voltage + * is read whatever its function. Not yet: the nonlinearity above about + * 2450 mV at 11 dB (ESP-IDF's LUT region) and a chip's spread from the + * fitted line, noise, the ULP's and the digital controller's (DMA, + * I2S) conversions, the Hall sensor, ADC2's arbitration with Wi-Fi, the + * amplifier (SAR_MEAS_WAIT, the AMP FSM). */ +#include + +#include "mcu/esp32/soc/esp32.h" + +#define READ_CTRL 0x00u +#define ATTEN1 0x34u +#define ATTEN2 0x38u +#define MEAS_START1 0x54u +#define READ_CTRL2 0x90u +#define MEAS_START2 0x94u +#define START_SAR (1u << 17) +#define DONE_SAR (1u << 16) +#define RTC_FAST_HZ 8000000.0 + +struct e32_adc { + struct esk_mach *s; + struct esk_rf_periph *p; + int busy[2]; + u64 due[2]; /* the conversion's end, in core cycles */ + u32 code[2]; + int clocked; +}; + +static const int pads[2][10] = { + { 36, 37, 38, 39, 32, 33, 34, 35, -1, -1 }, + { 4, 0, 2, 15, 13, 12, 14, 27, 25, 26 }, +}; +static const double scale[2][4] = { { 57431, 76236, 105481, 196602 }, { 57236, 76175, 105678, 197170 } }; +static const double offset_mv[2][4] = { { 75, 78, 107, 142 }, { 63, 66, 89, 128 } }; + +static u32 rd(const struct e32_adc *k, u32 off) { return esk_rf_read(k->p, off, 4); } + +static void hw(struct e32_adc *k, u32 off, u32 v) +{ + struct esk_rf_reg *r = esk_rf_reg_at(k->p, off); + if (r) + esk_rf_hw(r, v); +} + +/* the chip's ADC Vref in mV, from the eFuse (BLOCK0 word 4's ADC_VREF: + * sign and magnitude, 7 mV a step) */ +static double vref_mv(struct esk_mach *m) +{ + u32 bits = (esk_esp32_efuse_word(m, 0, 4) >> 8) & 0x1fu; + int steps = (int)(bits & 0xfu); + return 1100.0 + (double)((bits & 0x10u) ? -steps : steps) * 7.0; +} + +static u32 convert(struct e32_adc *k, int unit) +{ + struct esk_mach *s = k->s; + u32 start = rd(k, unit ? MEAS_START2 : MEAS_START1), ctrl = rd(k, unit ? READ_CTRL2 : READ_CTRL); + u32 pads_on = (start >> 19) & 0xfffu, bits = 9u + ((ctrl >> 16) & 3u), atten; + int ch, gpio; + double v = 0, a, d; + u32 code; + for (ch = 0; ch < 10 && !(pads_on & (1u << ch)); ch++) + ; + gpio = ch < 10 ? pads[unit][ch] : -1; + atten = ch < 10 ? (rd(k, unit ? ATTEN2 : ATTEN1) >> (2 * ch)) & 3u : 3u; + if (gpio >= 0 && s->host.pin_volts && !s->host.pin_volts(s->host.ctx, gpio / 16, gpio % 16, &v)) + v = 0; + a = vref_mv(s) * scale[unit][atten] / 4096.0; + d = (v * 1000.0 - offset_mv[unit][atten]) * 65536.0 / a + 0.5; + code = d <= 0 ? 0u : d >= 4095.0 ? 4095u : (u32)d; + code >>= 12u - bits; + if (!(ctrl & (1u << (unit ? 29 : 28)))) /* the converter's own, inverted */ + code = ((1u << bits) - 1u) - code; + return code; +} + +static void clocking(struct e32_adc *k) +{ + esk_rf_clock(k->p, &k->clocked, k->busy[0] || k->busy[1]); +} + +static void finish(struct e32_adc *k, int unit) +{ + u32 off = unit ? MEAS_START2 : MEAS_START1; + k->busy[unit] = 0; + hw(k, off, (rd(k, off) & ~0xffffu) | DONE_SAR | (k->code[unit] & 0xffffu)); +} + +static void start(struct e32_adc *k, int unit) +{ + u32 off = unit ? MEAS_START2 : MEAS_START1, ctrl = rd(k, unit ? READ_CTRL2 : READ_CTRL); + u32 div = ctrl & 0xffu, cycles = ((ctrl >> 8) & 0xffu) + 9u + ((ctrl >> 16) & 3u) + 1u; + double t = (double)cycles * (double)(div ? div : 1u) / RTC_FAST_HZ; + hw(k, off, rd(k, off) & ~DONE_SAR); + k->code[unit] = convert(k, unit); + k->busy[unit] = 1; + k->due[unit] = k->s->cycles + (u64)(t * (double)esk_mach_core_hz(k->s) + 0.5) + 1u; +} + +static void adc_tick(void *ctx, u32 cycles) +{ + struct e32_adc *k = (struct e32_adc *)ctx; + int u; + (void)cycles; + for (u = 0; u < 2; u++) + if (k->busy[u] && k->s->cycles >= k->due[u]) + finish(k, u); + clocking(k); +} + +static int adc_next(void *ctx, u32 *cycles) +{ + struct e32_adc *k = (struct e32_adc *)ctx; + u64 best = 0; + int u, any = 0; + for (u = 0; u < 2; u++) { + u64 d; + if (!k->busy[u]) + continue; + d = k->due[u] > k->s->cycles ? k->due[u] - k->s->cycles : 1u; + if (!any || d < best) + best = d; + any = 1; + } + if (!any) + return 0; + *cycles = best > 0xffffffffu ? 0xffffffffu : (u32)best; + return 1; +} + +static u32 adc_read(void *ctx, u32 off, int n) +{ + struct e32_adc *k = (struct e32_adc *)ctx; + return esk_rf_read(k->p, off, n); +} + +static void adc_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_adc *k = (struct e32_adc *)ctx; + u32 w = off & ~3u; + int unit = w == MEAS_START2 ? 1 : 0; + u32 was = (w == MEAS_START1 || w == MEAS_START2) ? rd(k, w) : 0; + esk_rf_write(k->p, off, n, v); + if (w == MEAS_START1 || w == MEAS_START2) { + u32 now = rd(k, w); + /* DATA and DONE are the converter's: what was written there is not kept */ + hw(k, w, (now & ~(0xffffu | DONE_SAR)) | (was & (0xffffu | DONE_SAR))); + if ((now & START_SAR) && !(was & START_SAR)) + start(k, unit); + } + clocking(k); +} + +static void adc_reset(void *ctx) +{ + struct e32_adc *k = (struct e32_adc *)ctx; + k->busy[0] = k->busy[1] = 0; + k->clocked = 0; + clocking(k); +} + +const struct esk_dev_ops esk_esp32_adc_ops = { + "esp32-sens", adc_read, adc_write, adc_reset, adc_tick, adc_next, +}; + +void *esk_esp32_adc_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_adc *k = (struct e32_adc *)esk_mach_alloc(s, sizeof *k); + if (!k) + return 0; + memset(k, 0, sizeof *k); + k->s = s; + k->p = p; + return k; +} diff --git a/core/mcu/esp32/soc/esp32.h b/core/mcu/esp32/soc/esp32.h index a6df40ba5..3604387de 100644 --- a/core/mcu/esp32/soc/esp32.h +++ b/core/mcu/esp32/soc/esp32.h @@ -19,6 +19,7 @@ * ledc.c the LED PWM controller * i2c.c I2C0 and I2C1 * rmt.c the remote control peripheral's eight channels + * adc.c the SAR ADCs as SENS's RTC controller drives them * misc.c the random number generator, the AHB view of the * peripherals */ #ifndef ESK_MCU_ESP32_SOC_H @@ -58,6 +59,8 @@ extern const struct esk_dev_ops esk_esp32_i2c_ops; void *esk_esp32_i2c_create(struct esk_mach *s, struct esk_rf_periph *p); extern const struct esk_dev_ops esk_esp32_rmt_ops; void *esk_esp32_rmt_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_adc_ops; +void *esk_esp32_adc_create(struct esk_mach *s, struct esk_rf_periph *p); extern const struct esk_dev_ops esk_esp32_sha_ops; void *esk_esp32_sha_create(struct esk_mach *s, struct esk_rf_periph *p); /* the RNG and the AHB view of the peripherals (misc.c): 0, or -1 */ diff --git a/core/mcu/models.c b/core/mcu/models.c index 0f603f9be..a1fbe3149 100644 --- a/core/mcu/models.c +++ b/core/mcu/models.c @@ -74,6 +74,7 @@ static const struct esk_rf_model_type model_types[] = { { "esp32-ledc", &esk_esp32_ledc_ops, esk_esp32_ledc_create }, { "esp32-i2c", &esk_esp32_i2c_ops, esk_esp32_i2c_create }, { "esp32-rmt", &esk_esp32_rmt_ops, esk_esp32_rmt_create }, + { "esp32-sens", &esk_esp32_adc_ops, esk_esp32_adc_create }, { "esp32-iomux", &esk_esp32_iomux_ops, esk_esp32_iomux_create }, { "esp32c3-intmtx", &esk_esp32c3_intmtx_ops, esk_esp32c3_intmtx_create }, { "esp32c3-uart", &esk_esp32c3_uart_ops, esk_esp32c3_uart_create }, diff --git a/docs/STATUS.md b/docs/STATUS.md index 41b396e1c..8d3bbb164 100644 --- a/docs/STATUS.md +++ b/docs/STATUS.md @@ -17,10 +17,11 @@ and through `esp_restart` (rst:0xc SW_CPU_RESET). Evidence: `test_lx6` scenarios `esp32_hello_world` (9/9), `esp32_blink` (6/6), `esp32_ledc_basic` (2/2), `esp32_i2c_eeprom` (3/3, I2C0 writing and reading a 24LC256 at 400 kHz), `esp32_gptimer` (17/17), `esp32_uart_echo` -(6/6), `esp32_real_time_stats` (10/10) and `esp32_blink_strip` (7/7, a -WS2812B through the RMT). Not yet: Wi-Fi and Bluetooth, the +(6/6), `esp32_real_time_stats` (10/10) , `esp32_blink_strip` (7/7, a +WS2812B through the RMT) and `esp32_adc_oneshot_read` (6/6, ADC1 and ADC2 +with the eFuse Vref's calibration). Not yet: Wi-Fi and Bluetooth, the double-precision accelerator's instructions, the peripherals the -description's fidelity lists (I2S, SPI2/3, ADC, ...), +description's fidelity lists (I2S, SPI2/3, the DACs, ...), sleep. The standalone harness below remains as its own qualification fixtures. diff --git a/docs/coverage.md b/docs/coverage.md index 8245e8da3..dd3902425 100644 --- a/docs/coverage.md +++ b/docs/coverage.md @@ -8,7 +8,7 @@ evidence for each model is in [STATUS.md](STATUS.md). | MCU | Modelled | Registers only | Missing | Peripherals | |---|---|---|---|---| -| ESP32 | 18 | 0 | 27 | 45 | +| ESP32 | 19 | 0 | 26 | 45 | | ESP32-C3 | 35 | 0 | 0 | 35 | | ATmega328P | 15 | 0 | 0 | 15 | | PIC24FJ1024GB610 | 11 | 4 | 17 | 32 | @@ -23,7 +23,7 @@ evidence for each model is in [STATUS.md](STATUS.md). ## ESP32 (`espressif/esp32`) Boards: ESP32-DevKitC V4. -18 of 45 peripherals modelled, 0 registers only, 27 missing. +19 of 45 peripherals modelled, 0 registers only, 26 missing. | Peripheral | Model | State | |---|---|---| @@ -40,7 +40,7 @@ Boards: ESP32-DevKitC V4. | FRC_TIMER | — | **missing** | | RTC_CNTL | `esp32-rtc` | modelled | | RTC_IO | — | **missing** | -| SENS | — | **missing** | +| SENS | `esp32-sens` | modelled | | RTC_I2C | — | **missing** | | IO_MUX | `esp32-iomux` | modelled | | HINF | — | **missing** | @@ -73,7 +73,7 @@ Boards: ESP32-DevKitC V4. | I2S1 | — | **missing** | | UART2 | `esp32-uart` | modelled | -Declared omissions: Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written); the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept; PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts; RMT: the memory's power-down (MEM_PD), STATUS's STATE and the APB-side error bits, the carrier on an idle output; I2C: the non-FIFO mode (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, the input filters (only their share of the SCL high time), 10-bit addressing's R/W check; the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, the SAR ADCs, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption; sleep modes (light and deep sleep, the power domains), brown-out; the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection. +Declared omissions: Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written); the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept; PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts; RMT: the memory's power-down (MEM_PD), STATUS's STATE and the APB-side error bits, the carrier on an idle output; the SAR ADCs: the nonlinearity above about 2450 mV at 11 dB and a chip's spread from the fitted line, noise, the ULP's and the digital controller's (DMA, I2S) conversions, the Hall sensor, ADC2's arbitration with Wi-Fi, the RTC IO MUX's routing of a pad to the ADC (not checked); I2C: the non-FIFO mode (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, the input filters (only their share of the SCL high time), 10-bit addressing's R/W check; the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption; sleep modes (light and deep sleep, the power domains), brown-out; the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection. ## ESP32-C3 (`espressif/esp32c3`) diff --git a/tests/vendor/esp-idf/examples/esp32_adc_oneshot_read/project.json b/tests/vendor/esp-idf/examples/esp32_adc_oneshot_read/project.json new file mode 100644 index 000000000..7262f65b1 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_adc_oneshot_read/project.json @@ -0,0 +1,112 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "esp-idf-esp32_adc_oneshot_read", + "description": "ESP-IDF's adc/oneshot_read on the ESP32-DevKitC V4: 1.1 V on IO32 (ADC1 channel 4), 2.2 V on IO33 (ADC1 channel 5) and 0.5 V on IO4 (ADC2 channel 0) from three sources.", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + }, + { + "id": "V2", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 1.1 + }, + "layout": { + "x": 120, + "y": 440 + } + }, + { + "id": "V3", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 2.2 + }, + "layout": { + "x": 120, + "y": 560 + } + }, + { + "id": "V4", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 0.5 + }, + "layout": { + "x": 120, + "y": 700 + } + } + ], + "nets": { + "USB5V": [ + "USB.+", + "B1.VBUS" + ], + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1", + "V2.-", + "V3.-", + "V4.-" + ], + "IO32": [ + "V2.+", + "B1.IO32" + ], + "IO33": [ + "V3.+", + "B1.IO33" + ], + "IO4": [ + "V4.+", + "B1.IO4" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_adc_oneshot_read/scenario.json b/tests/vendor/esp-idf/examples/esp32_adc_oneshot_read/scenario.json new file mode 100644 index 000000000..9d0d3b8b0 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_adc_oneshot_read/scenario.json @@ -0,0 +1,58 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "esp32_adc_oneshot_read", + "until": "3500ms", + "description": "adc/oneshot_read on the ESP32: ADC1's channels 4 and 5 and ADC2's channel 0 at 12 dB, one read a second each, with the eFuse's Vref calibration (ESP-IDF's line fitting, Vref 1170 mV on this chip). The model's transfer is that fitted line, so the raw codes are its inverse and the calibrated voltages the sources' within a millivolt. ADC1 at 12 dB: a = 1170 x 196602 / 4096 = 56158, b = 142 mV, so 1.1 V is (1100 - 142) x 65536 / 56158 = 1118 and 2.2 V 2402; ADC2: a = 56320, b = 128 mV, so 0.5 V is 433.", + "inputs": [], + "assertions": [ + { + "id": "adc1-ch4-raw", + "at": "3400ms", + "probe": "console", + "expect": { + "contains": "ADC1 Channel[4] Raw Data: 1118\r\n" + } + }, + { + "id": "adc1-ch4-mv", + "at": "3400ms", + "probe": "console", + "expect": { + "contains": "ADC1 Channel[4] Cali Voltage: 1100 mV\r\n" + } + }, + { + "id": "adc1-ch5-raw", + "at": "3400ms", + "probe": "console", + "expect": { + "contains": "ADC1 Channel[5] Raw Data: 2402\r\n" + } + }, + { + "id": "adc1-ch5-mv", + "at": "3400ms", + "probe": "console", + "expect": { + "contains": "ADC1 Channel[5] Cali Voltage: 2200 mV\r\n" + } + }, + { + "id": "adc2-ch0-raw", + "at": "3400ms", + "probe": "console", + "expect": { + "contains": "ADC2 Channel[0] Raw Data: 433\r\n" + } + }, + { + "id": "adc2-ch0-mv", + "at": "3400ms", + "probe": "console", + "expect": { + "contains": "ADC2 Channel[0] Cali Voltage: 500 mV\r\n" + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/run.py b/tests/vendor/esp-idf/run.py index 4c8d9c818..534bea08a 100644 --- a/tests/vendor/esp-idf/run.py +++ b/tests/vendor/esp-idf/run.py @@ -79,6 +79,7 @@ "esp32_uart_echo": "examples/peripherals/uart/uart_echo", "esp32_real_time_stats": "examples/system/freertos/real_time_stats", "esp32_blink_strip": "examples/get-started/blink", + "esp32_adc_oneshot_read": "examples/peripherals/adc/oneshot_read", } # the target an example is built for, when not the ESP32-C3 (its board in # examples//project.json), and the toolchain that target needs @@ -91,6 +92,7 @@ "esp32_uart_echo": "esp32", "esp32_real_time_stats": "esp32", "esp32_blink_strip": "esp32", + "esp32_adc_oneshot_read": "esp32", } TOOLCHAINS = {"esp32c3": "riscv32-esp-elf-gcc", "esp32": "xtensa-esp32-elf-gcc"} # examples built only for another's project (with examples//'s From 3d310bf43a24578f8f4f0f771ef11d5a9d544e03 Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 05:36:48 +0000 Subject: [PATCH 13/16] ESP32: Arduino-ESP32's sketches on the DevKitC; DBREAK's mask Five sketches compiled for "ESP32 Dev Module" with Arduino-ESP32 3.2.0 run unmodified (tests/vendor/arduino-esp32, ESP32_*): AnalogReadSerial and ReadAnalogVoltage on VP, DigitalReadSerial, GetChipID (ESP32-D0WD-V3 Rev 301, two cores) and RepeatTimer stopped by the board's Boot button. Arduino turns on FreeRTOS's end-of-stack watchpoint, and its loopTask stopped at once with "Stack canary watchpoint triggered": the core took DBREAKC's MASK as the address bits ignored, where its set bits are the low bits compared (ESP-IDF's 32-byte watchpoint writes 0x20). test_lx6 gains a store watchpoint over 32 bytes, missed just past it and taken inside it. --- CHANGELOG.md | 6 +- catalog/mcus/espressif/esp32/mcu.json | 9 +- core/mcu/xtensa/lx6.c | 4 +- docs/STATUS.md | 4 +- tests/unit/gen_lx6_programs.py | 27 +++++ tests/unit/lx6_programs.h | 109 ++++++++++++++++++ tests/unit/test_lx6.c | 13 +++ .../ESP32_AnalogReadSerial/project.json | 78 +++++++++++++ .../ESP32_AnalogReadSerial/scenario.json | 18 +++ .../ESP32_DigitalReadSerial/project.json | 90 +++++++++++++++ .../ESP32_DigitalReadSerial/scenario.json | 47 ++++++++ .../examples/ESP32_GetChipID/project.json | 61 ++++++++++ .../examples/ESP32_GetChipID/scenario.json | 34 ++++++ .../ESP32_ReadAnalogVoltage/project.json | 78 +++++++++++++ .../ESP32_ReadAnalogVoltage/scenario.json | 18 +++ .../examples/ESP32_RepeatTimer/project.json | 61 ++++++++++ .../examples/ESP32_RepeatTimer/scenario.json | 47 ++++++++ tests/vendor/arduino-esp32/run.py | 27 ++++- 18 files changed, 718 insertions(+), 13 deletions(-) create mode 100644 tests/vendor/arduino-esp32/examples/ESP32_AnalogReadSerial/project.json create mode 100644 tests/vendor/arduino-esp32/examples/ESP32_AnalogReadSerial/scenario.json create mode 100644 tests/vendor/arduino-esp32/examples/ESP32_DigitalReadSerial/project.json create mode 100644 tests/vendor/arduino-esp32/examples/ESP32_DigitalReadSerial/scenario.json create mode 100644 tests/vendor/arduino-esp32/examples/ESP32_GetChipID/project.json create mode 100644 tests/vendor/arduino-esp32/examples/ESP32_GetChipID/scenario.json create mode 100644 tests/vendor/arduino-esp32/examples/ESP32_ReadAnalogVoltage/project.json create mode 100644 tests/vendor/arduino-esp32/examples/ESP32_ReadAnalogVoltage/scenario.json create mode 100644 tests/vendor/arduino-esp32/examples/ESP32_RepeatTimer/project.json create mode 100644 tests/vendor/arduino-esp32/examples/ESP32_RepeatTimer/scenario.json diff --git a/CHANGELOG.md b/CHANGELOG.md index feef4881f..ea0176189 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -31,7 +31,11 @@ versions follow semantic versioning. There is no release yet. 24LC256, `esp32_gptimer` 17/17, `esp32_uart_echo` 6/6 on UART2, `esp32_real_time_stats` 10/10 across both cores, `esp32_blink_strip` 7/7 on a WS2812B through the RMT, - `esp32_adc_oneshot_read` 6/6 with the eFuse Vref's calibration; the UARTs keep + `esp32_adc_oneshot_read` 6/6 with the eFuse Vref's calibration; + Arduino-ESP32's AnalogReadSerial, ReadAnalogVoltage, DigitalReadSerial, + GetChipID and RepeatTimer for "ESP32 Dev Module" in + `tests/vendor/arduino-esp32` (`ESP32_*`); DBREAKC's MASK now marks the + address bits compared, as ESP-IDF's stack-end watchpoint has it; the UARTs keep MEM_RX_STATUS's addresses, from which ESP-IDF counts the bytes waiting); `test_lx6` checks the core with programs from Espressif's assembler. ### Original ESP32 digital per-pin hold diff --git a/catalog/mcus/espressif/esp32/mcu.json b/catalog/mcus/espressif/esp32/mcu.json index b97f0ba30..a2f031e7f 100644 --- a/catalog/mcus/espressif/esp32/mcu.json +++ b/catalog/mcus/espressif/esp32/mcu.json @@ -275,7 +275,7 @@ }, "fidelity": { "functional": { - "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts, MEM_RX_STATUS's addresses that ESP-IDF counts the bytes waiting from), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), I2C0 and I2C1 (master and slave on the open-drain lines through the matrix, the 16 commands with RSTART, WRITE, READ, STOP and END, the bus timing in APB_CLK cycles, ACK checks, arbitration, the SCL timeout, the 32-byte FIFOs through DATA and its AHB view, 7- and 10-bit slave addresses; ESP-IDF's i2c_eeprom runs on a 24LC256), the RMT (eight channels sending or receiving through the matrix, 64-word blocks of the 512-word RAM, end markers, continuous mode, wrap, TX_LIM's threshold, the carrier, the receiver's idle threshold and filter, the RAM through CHnDATA; ESP-IDF's led_strip lights a WS2812B), the SAR ADCs as SENS's RTC controller drives them (one conversion at a time on ADC1's eight and ADC2's ten pads, the attenuations, 9 to 12 bits, the converter's inverted output and DATA_INV, the conversion's time; the transfer the line ESP-IDF's Vref calibration fits for the chip, its eFuse Vref), PERIP_RST_EN's resets of I2C0, I2C1 and LEDC, the internal analog I2C master, the random number generator and the peripherals' AHB view. The evidence: test_lx6.c's programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16) and the APP_CPU's ROM data kept apart; ESP-IDF v5.4's hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats, blink with its LED strip and adc oneshot_read built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart; the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin.", + "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts, MEM_RX_STATUS's addresses that ESP-IDF counts the bytes waiting from), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), I2C0 and I2C1 (master and slave on the open-drain lines through the matrix, the 16 commands with RSTART, WRITE, READ, STOP and END, the bus timing in APB_CLK cycles, ACK checks, arbitration, the SCL timeout, the 32-byte FIFOs through DATA and its AHB view, 7- and 10-bit slave addresses; ESP-IDF's i2c_eeprom runs on a 24LC256), the RMT (eight channels sending or receiving through the matrix, 64-word blocks of the 512-word RAM, end markers, continuous mode, wrap, TX_LIM's threshold, the carrier, the receiver's idle threshold and filter, the RAM through CHnDATA; ESP-IDF's led_strip lights a WS2812B), the SAR ADCs as SENS's RTC controller drives them (one conversion at a time on ADC1's eight and ADC2's ten pads, the attenuations, 9 to 12 bits, the converter's inverted output and DATA_INV, the conversion's time; the transfer the line ESP-IDF's Vref calibration fits for the chip, its eFuse Vref), PERIP_RST_EN's resets of I2C0, I2C1 and LEDC, the internal analog I2C master, the random number generator and the peripherals' AHB view. The evidence: test_lx6.c's programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16) and the APP_CPU's ROM data kept apart; ESP-IDF v5.4's hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats, blink with its LED strip and adc oneshot_read built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart; Arduino-ESP32 3.2.0's sketches for \"ESP32 Dev Module\" (AnalogReadSerial, ReadAnalogVoltage, DigitalReadSerial, GetChipID, RepeatTimer, with FreeRTOS's stack-end watchpoints on); the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin.", "omissions": [ "Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written)", "the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept", @@ -298,7 +298,8 @@ "repo:tests/vendor/esp-idf/examples/esp32_uart_echo/scenario.json", "repo:tests/vendor/esp-idf/examples/esp32_real_time_stats/scenario.json", "repo:tests/vendor/esp-idf/examples/esp32_blink_strip/scenario.json", - "repo:tests/vendor/esp-idf/examples/esp32_adc_oneshot_read/scenario.json" + "repo:tests/vendor/esp-idf/examples/esp32_adc_oneshot_read/scenario.json", + "repo:tests/vendor/arduino-esp32/run.py" ] }, "timed": { @@ -404,11 +405,11 @@ }, "i18n": { "fr": { - "source": "bff3ddeda639", + "source": "a076e310391c", "description": "Espressif ESP32 (ESP32-D0WD-V3, révision de puce v3.1) : deux cœurs Xtensa LX6 jusqu'à 240 MHz, 520 Kio de SRAM, 448 Kio de ROM, 16 Kio de mémoire RTC, une flash SPI externe derrière les caches des cœurs, Wi-Fi et Bluetooth ; le MCU de l'ESP32-DevKitC. La ROM d'Espressif, le bootloader de second niveau d'ESP-IDF et les applications ESP-IDF tournent sur les deux cœurs ; les radios ne sont pas encore modélisées.", "fidelity": { "functional": { - "claims": "Les deux cœurs Xtensa LX6 (mcu/xtensa/lx6.c, lx6fp.c) tels que les configure le core-isa.h d'Espressif : les instructions de base et de densité, les registres fenêtrés (64, le contrôle de débordement de chaque instruction, CALL4/8/12, ENTRY, RETW et son sous-débordement, MOVSP, ROTW, L32E/S32E), les boucles sans surcoût, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, les booléens, S32C1I avec SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), le paquet MAC16, la FPU simple précision (modes d'arrondi et drapeaux IEEE ; les séquences de division et de racine carrée qu'exécute libgcc donnent des résultats correctement arrondis), les exceptions XEA2 avec vecteurs relocalisables, 32 interruptions aux niveaux et types de core-isa.h (niveau, front, logicielles, les temporisateurs CCOMPARE0-2 contre CCOUNT, NMI), RSIL, WAITI, RFI, BREAK, IBREAK, DBREAK et ICOUNT de l'option de débogage, la protection par régions (huit régions de 512 Mo, 15 sans accès), les chargements et écritures non alignés, et les accès de données en 32 bits seulement du bus d'instructions. Les deux cœurs partagent la machine, l'APP_CPU maintenu en reset jusqu'à ce que DPORT le libère et voyant la ROM avec ses pointeurs vers les données ROM du PRO_CPU déplacés vers les siennes, comme dans l'image ROM APP_CPU d'Espressif. Le démarrage : la ROM d'Espressif (esp32_rev300_rom.elf, révision v3) depuis le vecteur de reset, sa bannière, les broches de configuration (GPIO_STRAP : SPI_FAST_FLASH_BOOT, ou le mode téléchargement avec GPIO0 bas), les causes de reset (RTC_CNTL), le contrôle anti-glitch de l'eFuse, la lecture de la flash par SPI1, le bootloader de second niveau d'ESP-IDF et sa vérification d'image sur l'accélérateur SHA, la MMU flash des caches, et l'application sur les deux cœurs. Les modèles : DPORT (reset, horloge et blocage de l'APP_CPU, CPU_PER_CONF, vidage et état des caches, tables de la MMU flash, les 69 sources de la matrice d'interruptions, les interruptions inter-CPU), RTC_CNTL (causes de reset, le temporisateur RTC, le chien de garde RTC avec sa protection au démarrage sur flash, les resets et blocages logiciels, les registres de stockage, SOC_CLK_SEL), APB_CTRL (les horloges CPU et APB depuis XTAL, PLL ou RC_FAST), le contrôleur eFuse avec les bits d'usine de la puce (ESP32-D0WD-V3 v3.1, une MAC avec son CRC, ou celle des réglages de la carte), GPIO et IO_MUX (40 plots, la matrice, tirages, drain ouvert, interruptions sur chaque CPU, le verrou de configuration), UART0-2 (FIFO, trames au débit, interruptions, les adresses de MEM_RX_STATUS d'après lesquelles ESP-IDF compte les octets en attente), TIMG0/1 (T0, T1, le temporisateur LAC, le MWDT avec sa protection au démarrage sur flash, la calibration de RTC_SLOW_CLK), SPI0/SPI1 avec la flash Giantec GT25Q32A du module (C4 60 16, l'identifiant que rapporte la carte du propriétaire), l'accélérateur SHA (SHA-1, -256, -384, -512), LEDC (huit canaux MLI rapides et huit lents sur huit temporisateurs, le fondu, sur ledc_hs/ls_sig_out de la matrice), I2C0 et I2C1 (maître et esclave sur les lignes à drain ouvert à travers la matrice, les 16 commandes avec RSTART, WRITE, READ, STOP et END, le timing du bus en cycles d'APB_CLK, les contrôles d'ACK, l'arbitrage, le délai d'attente sur SCL, les FIFO de 32 octets par DATA et sa vue AHB, les adresses esclaves sur 7 et 10 bits ; l'exemple i2c_eeprom d'ESP-IDF fonctionne avec une 24LC256), le RMT (huit canaux qui émettent ou reçoivent à travers la matrice, des blocs de 64 mots de la RAM de 512 mots, les marqueurs de fin, le mode continu, le rebouclage, le seuil de TX_LIM, la porteuse, le seuil d'inactivité et le filtre du récepteur, la RAM par CHnDATA ; le led_strip d'ESP-IDF allume une WS2812B), les ADC SAR tels que les pilote le contrôleur RTC de SENS (une conversion à la fois sur les huit plots de l'ADC1 et les dix de l'ADC2, les atténuations, 9 à 12 bits, la sortie inversée du convertisseur et DATA_INV, la durée de la conversion ; la caractéristique est la droite que la calibration Vref d'ESP-IDF ajuste pour la puce, avec son Vref d'eFuse), les resets de PERIP_RST_EN pour I2C0, I2C1 et LEDC, le maître I2C analogique interne, le générateur de nombres aléatoires et la vue AHB des périphériques. Les preuves : les programmes de test_lx6.c assemblés par l'assembleur d'Espressif (entiers, décalages, multiplication et division, boucles, branchements, mémoire avec S32C1I, récursion fenêtrée à travers les vecteurs de fenêtre de la ROM, SYSCALL, l'interruption du temporisateur CCOMPARE, FPU, MAC16) et les données ROM de l'APP_CPU tenues à part ; hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats, blink avec son ruban de LED et adc oneshot_read d'ESP-IDF v5.4 compilés sans modification pour la cible esp32 sur l'ESP32-DevKitC V4, de la bannière de la ROM jusqu'à esp_restart ; l'image ROM est identique octet pour octet à l'esp32-v3-rom.bin du QEMU d'Espressif, et la vue qu'en a l'APP_CPU à son esp32-v3-rom-app.bin.", + "claims": "Les deux cœurs Xtensa LX6 (mcu/xtensa/lx6.c, lx6fp.c) tels que les configure le core-isa.h d'Espressif : les instructions de base et de densité, les registres fenêtrés (64, le contrôle de débordement de chaque instruction, CALL4/8/12, ENTRY, RETW et son sous-débordement, MOVSP, ROTW, L32E/S32E), les boucles sans surcoût, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, les booléens, S32C1I avec SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), le paquet MAC16, la FPU simple précision (modes d'arrondi et drapeaux IEEE ; les séquences de division et de racine carrée qu'exécute libgcc donnent des résultats correctement arrondis), les exceptions XEA2 avec vecteurs relocalisables, 32 interruptions aux niveaux et types de core-isa.h (niveau, front, logicielles, les temporisateurs CCOMPARE0-2 contre CCOUNT, NMI), RSIL, WAITI, RFI, BREAK, IBREAK, DBREAK et ICOUNT de l'option de débogage, la protection par régions (huit régions de 512 Mo, 15 sans accès), les chargements et écritures non alignés, et les accès de données en 32 bits seulement du bus d'instructions. Les deux cœurs partagent la machine, l'APP_CPU maintenu en reset jusqu'à ce que DPORT le libère et voyant la ROM avec ses pointeurs vers les données ROM du PRO_CPU déplacés vers les siennes, comme dans l'image ROM APP_CPU d'Espressif. Le démarrage : la ROM d'Espressif (esp32_rev300_rom.elf, révision v3) depuis le vecteur de reset, sa bannière, les broches de configuration (GPIO_STRAP : SPI_FAST_FLASH_BOOT, ou le mode téléchargement avec GPIO0 bas), les causes de reset (RTC_CNTL), le contrôle anti-glitch de l'eFuse, la lecture de la flash par SPI1, le bootloader de second niveau d'ESP-IDF et sa vérification d'image sur l'accélérateur SHA, la MMU flash des caches, et l'application sur les deux cœurs. Les modèles : DPORT (reset, horloge et blocage de l'APP_CPU, CPU_PER_CONF, vidage et état des caches, tables de la MMU flash, les 69 sources de la matrice d'interruptions, les interruptions inter-CPU), RTC_CNTL (causes de reset, le temporisateur RTC, le chien de garde RTC avec sa protection au démarrage sur flash, les resets et blocages logiciels, les registres de stockage, SOC_CLK_SEL), APB_CTRL (les horloges CPU et APB depuis XTAL, PLL ou RC_FAST), le contrôleur eFuse avec les bits d'usine de la puce (ESP32-D0WD-V3 v3.1, une MAC avec son CRC, ou celle des réglages de la carte), GPIO et IO_MUX (40 plots, la matrice, tirages, drain ouvert, interruptions sur chaque CPU, le verrou de configuration), UART0-2 (FIFO, trames au débit, interruptions, les adresses de MEM_RX_STATUS d'après lesquelles ESP-IDF compte les octets en attente), TIMG0/1 (T0, T1, le temporisateur LAC, le MWDT avec sa protection au démarrage sur flash, la calibration de RTC_SLOW_CLK), SPI0/SPI1 avec la flash Giantec GT25Q32A du module (C4 60 16, l'identifiant que rapporte la carte du propriétaire), l'accélérateur SHA (SHA-1, -256, -384, -512), LEDC (huit canaux MLI rapides et huit lents sur huit temporisateurs, le fondu, sur ledc_hs/ls_sig_out de la matrice), I2C0 et I2C1 (maître et esclave sur les lignes à drain ouvert à travers la matrice, les 16 commandes avec RSTART, WRITE, READ, STOP et END, le timing du bus en cycles d'APB_CLK, les contrôles d'ACK, l'arbitrage, le délai d'attente sur SCL, les FIFO de 32 octets par DATA et sa vue AHB, les adresses esclaves sur 7 et 10 bits ; l'exemple i2c_eeprom d'ESP-IDF fonctionne avec une 24LC256), le RMT (huit canaux qui émettent ou reçoivent à travers la matrice, des blocs de 64 mots de la RAM de 512 mots, les marqueurs de fin, le mode continu, le rebouclage, le seuil de TX_LIM, la porteuse, le seuil d'inactivité et le filtre du récepteur, la RAM par CHnDATA ; le led_strip d'ESP-IDF allume une WS2812B), les ADC SAR tels que les pilote le contrôleur RTC de SENS (une conversion à la fois sur les huit plots de l'ADC1 et les dix de l'ADC2, les atténuations, 9 à 12 bits, la sortie inversée du convertisseur et DATA_INV, la durée de la conversion ; la caractéristique est la droite que la calibration Vref d'ESP-IDF ajuste pour la puce, avec son Vref d'eFuse), les resets de PERIP_RST_EN pour I2C0, I2C1 et LEDC, le maître I2C analogique interne, le générateur de nombres aléatoires et la vue AHB des périphériques. Les preuves : les programmes de test_lx6.c assemblés par l'assembleur d'Espressif (entiers, décalages, multiplication et division, boucles, branchements, mémoire avec S32C1I, récursion fenêtrée à travers les vecteurs de fenêtre de la ROM, SYSCALL, l'interruption du temporisateur CCOMPARE, FPU, MAC16) et les données ROM de l'APP_CPU tenues à part ; hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats, blink avec son ruban de LED et adc oneshot_read d'ESP-IDF v5.4 compilés sans modification pour la cible esp32 sur l'ESP32-DevKitC V4, de la bannière de la ROM jusqu'à esp_restart ; les croquis d'Arduino-ESP32 3.2.0 pour « ESP32 Dev Module » (AnalogReadSerial, ReadAnalogVoltage, DigitalReadSerial, GetChipID, RepeatTimer, avec les points d'arrêt de fin de pile de FreeRTOS actifs) ; l'image ROM est identique octet pour octet à l'esp32-v3-rom.bin du QEMU d'Espressif, et la vue qu'en a l'APP_CPU à son esp32-v3-rom-app.bin.", "omissions": [ "le Wi-Fi, le Bluetooth et l'étage RF (WIFI_MAC, BB, NRX, FE : leurs registres gardent ce qui y est écrit)", "les instructions de l'accélérateur double précision (F64ADDC, F64ITER et les autres : leurs encodages sont publics, pas ce qu'elles font ; un programme qui en exécute une s'arrête avec un diagnostic), bien que ses registres soient conservés", diff --git a/core/mcu/xtensa/lx6.c b/core/mcu/xtensa/lx6.c index e08dc1f8a..7be442539 100644 --- a/core/mcu/xtensa/lx6.c +++ b/core/mcu/xtensa/lx6.c @@ -301,7 +301,9 @@ static int dbreak_hit(struct lx6 *c, u32 a, int n, int store) u32 ctl = c->dbreakc[i], mask; if (!(ctl & (store ? 0x80000000u : 0x40000000u))) continue; - mask = ~(ctl & 0x3fu); + /* MASK's set bits are the low address bits compared (ESP-IDF's + * 32-byte stack-end watchpoint: 0x20, bits 4:0 ignored) */ + mask = 0xffffffc0u | (ctl & 0x3fu); if (((a ^ c->dbreaka[i]) & mask) == 0 || (((a + (u32)n - 1u) ^ c->dbreaka[i]) & mask) == 0) { if ((c->ps & PS_INTLEVEL) < DEBUG_LEVEL) { diff --git a/docs/STATUS.md b/docs/STATUS.md index 8d3bbb164..59a456689 100644 --- a/docs/STATUS.md +++ b/docs/STATUS.md @@ -19,7 +19,9 @@ scenarios `esp32_hello_world` (9/9), `esp32_blink` (6/6), reading a 24LC256 at 400 kHz), `esp32_gptimer` (17/17), `esp32_uart_echo` (6/6), `esp32_real_time_stats` (10/10) , `esp32_blink_strip` (7/7, a WS2812B through the RMT) and `esp32_adc_oneshot_read` (6/6, ADC1 and ADC2 -with the eFuse Vref's calibration). Not yet: Wi-Fi and Bluetooth, the +with the eFuse Vref's calibration); Arduino-ESP32's AnalogReadSerial, +ReadAnalogVoltage, DigitalReadSerial, GetChipID and RepeatTimer for "ESP32 +Dev Module" (`tests/vendor/arduino-esp32`, `ESP32_*`). Not yet: Wi-Fi and Bluetooth, the double-precision accelerator's instructions, the peripherals the description's fidelity lists (I2S, SPI2/3, the DACs, ...), sleep. The standalone harness below remains as its own qualification diff --git a/tests/unit/gen_lx6_programs.py b/tests/unit/gen_lx6_programs.py index 7e2bbb162..f20404dad 100644 --- a/tests/unit/gen_lx6_programs.py +++ b/tests/unit/gen_lx6_programs.py @@ -216,6 +216,33 @@ movi a9, 0 wsr.intenable a9 rfe +""", + # a store watchpoint over 32 bytes as ESP-IDF sets one (DBREAKC 0x20: + # address bits 4:0 ignored): a store past it misses, one in it takes + # the debug exception (level 6) before it is done + "dbreak": """ + movi a2, vectors + wsr.vecbase a2 + movi a6, 0 + movi a3, 0x3ffb0040 + wsr.dbreaka0 a3 + movi a4, 0x80000020 + wsr.dbreakc0 a4 + isync + movi a5, 0x55 + s32i a5, a3, 32 # 0x3ffb0060: outside + s32i a5, a3, 28 # 0x3ffb005c: inside + l32i a9, a3, 28 # the store was done after the handler + j . + .align 1024 +vectors: + .org vectors + 0x280 +debug: + addi a6, a6, 1 + rsr.debugcause a7 + movi a8, 0 + wsr.dbreakc0 a8 + rfi 6 """, "float": """ movi a2, 1 diff --git a/tests/unit/lx6_programs.h b/tests/unit/lx6_programs.h index 8326b4dc3..61a897d73 100644 --- a/tests/unit/lx6_programs.h +++ b/tests/unit/lx6_programs.h @@ -295,6 +295,115 @@ static const unsigned char prog_timer[1808] = { 0x70, 0xe8, 0x03, 0x80, 0xe2, 0x03, 0x0c, 0x16, 0x0c, 0x09, 0x90, 0xe4, 0x13, 0x00, 0x30, 0x00, }; +#define PROG_DBREAK_ENTRY 0x4008000Cu +static const unsigned char prog_dbreak[1680] = { + 0x00, 0x04, 0x08, 0x40, 0x40, 0x00, 0xfb, 0x3f, 0x20, 0x00, 0x00, 0x80, 0x21, 0xfd, 0xff, 0x20, + 0xe7, 0x13, 0x0c, 0x06, 0x31, 0xfc, 0xff, 0x30, 0x90, 0x13, 0x41, 0xfb, 0xff, 0x40, 0xa0, 0x13, + 0x00, 0x20, 0x00, 0x5c, 0x55, 0x59, 0x83, 0x59, 0x73, 0x98, 0x73, 0x06, 0xff, 0xff, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1b, 0x66, 0x70, 0xe9, 0x03, 0x0c, 0x08, 0x80, 0xa0, 0x13, 0x10, 0x36, 0x00, 0x00, 0x00, 0x00, +}; + #define PROG_FLOAT_ENTRY 0x40080000u static const unsigned char prog_float[47] = { 0x0c, 0x12, 0x20, 0xe0, 0x13, 0x10, 0x20, 0x00, 0x0c, 0x33, 0x00, 0x03, 0xca, 0x0c, 0x54, 0x10, diff --git a/tests/unit/test_lx6.c b/tests/unit/test_lx6.c index 79436eb8a..cffa48c5c 100644 --- a/tests/unit/test_lx6.c +++ b/tests/unit/test_lx6.c @@ -287,6 +287,18 @@ static void test_timer(void) close32(&t); } +static void test_dbreak(void) +{ + t32 t; + if (!OPEN(t, dbreak, DBREAK)) + return; + CHECK(run_to_end(&t, 200)); + CHECK_EQ(a(&t, 6), 1u); /* one hit: the store inside */ + CHECK_EQ(a(&t, 7) & 0x4u, 0x4u); /* DEBUGCAUSE: DBREAK */ + CHECK_EQ(a(&t, 9), 0x55u); /* the store done after it */ + close32(&t); +} + static void test_float(void) { t32 t; @@ -345,6 +357,7 @@ RUN(test_memory); RUN(test_windows); RUN(test_syscall); RUN(test_timer); +RUN(test_dbreak); RUN(test_float); RUN(test_mac16); RUN(test_app_cpu_rom_data); diff --git a/tests/vendor/arduino-esp32/examples/ESP32_AnalogReadSerial/project.json b/tests/vendor/arduino-esp32/examples/ESP32_AnalogReadSerial/project.json new file mode 100644 index 000000000..3a70b1874 --- /dev/null +++ b/tests/vendor/arduino-esp32/examples/ESP32_AnalogReadSerial/project.json @@ -0,0 +1,78 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "arduino-esp32-ESP32_AnalogReadSerial", + "description": "AnalogReadSerial on the ESP32-DevKitC V4: A0 is GPIO36 (the header's VP), fed 1.1 V from a source.", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + }, + { + "id": "V1", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 1.1 + }, + "layout": { + "x": 120, + "y": 460 + } + } + ], + "nets": { + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1", + "V1.-" + ], + "USB5V": [ + "USB.+", + "B1.VBUS" + ], + "A0": [ + "V1.+", + "B1.VP" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/arduino-esp32/examples/ESP32_AnalogReadSerial/scenario.json b/tests/vendor/arduino-esp32/examples/ESP32_AnalogReadSerial/scenario.json new file mode 100644 index 000000000..76299928b --- /dev/null +++ b/tests/vendor/arduino-esp32/examples/ESP32_AnalogReadSerial/scenario.json @@ -0,0 +1,18 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "ESP32_AnalogReadSerial", + "until": "1200ms", + "description": "AnalogReadSerial on the ESP32: analogRead(A0) on GPIO36 at Arduino-ESP32's defaults (12 bits, 11 dB), 1.1 V reading 1118 as on ESP-IDF's oneshot_read (the line ESP-IDF's Vref calibration fits for this chip, Vref 1170 mV), printed every millisecond.", + "inputs": [], + "assertions": [ + { + "id": "reads", + "at": "1s", + "probe": "console", + "expect": { + "contains": "\r\n1118\r\n1118\r\n1118\r\n" + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/arduino-esp32/examples/ESP32_DigitalReadSerial/project.json b/tests/vendor/arduino-esp32/examples/ESP32_DigitalReadSerial/project.json new file mode 100644 index 000000000..0fba094a7 --- /dev/null +++ b/tests/vendor/arduino-esp32/examples/ESP32_DigitalReadSerial/project.json @@ -0,0 +1,90 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "arduino-esp32-ESP32_DigitalReadSerial", + "description": "DigitalReadSerial as its comment wires it: a push button from 3V3 to IO2 (pin 2), 10 kohm from IO2 to ground. On the ESP32-DevKitC V4 (pin 2 is GPIO2).", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + }, + { + "id": "SW1", + "component": "emblink/push_button", + "layout": { + "x": 120, + "y": 460 + } + }, + { + "id": "R1", + "component": "emblink/resistor", + "params": { + "resistance": 10000 + }, + "layout": { + "x": 260, + "y": 460 + } + } + ], + "nets": { + "USB5V": [ + "USB.+", + "B1.VBUS" + ], + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1", + "R1.2" + ], + "3V3": [ + "B1.3V3", + "SW1.1" + ], + "BTN": [ + "SW1.2", + "B1.IO2", + "R1.1" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/arduino-esp32/examples/ESP32_DigitalReadSerial/scenario.json b/tests/vendor/arduino-esp32/examples/ESP32_DigitalReadSerial/scenario.json new file mode 100644 index 000000000..614c6b9dc --- /dev/null +++ b/tests/vendor/arduino-esp32/examples/ESP32_DigitalReadSerial/scenario.json @@ -0,0 +1,47 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "ESP32_DigitalReadSerial", + "until": "2000ms", + "description": "DigitalReadSerial: the button's state printed at 9600 baud, a line a millisecond or as fast as the UART takes it: 0 until the button is pressed at 1 s, 1 while it is held.", + "inputs": [ + { + "at": "1s", + "target": "SW1", + "input": "pressed", + "value": true + }, + { + "at": "1500ms", + "target": "SW1", + "input": "pressed", + "value": false + } + ], + "assertions": [ + { + "id": "released", + "at": "900ms", + "probe": "console", + "expect": { + "contains": "\r\n0\r\n0\r\n" + } + }, + { + "id": "not-yet", + "at": "900ms", + "probe": "console", + "expect": { + "not_contains": "\r\n1\r\n" + } + }, + { + "id": "pressed", + "at": "1450ms", + "probe": "console", + "expect": { + "contains": "\r\n1\r\n1\r\n1\r\n" + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/arduino-esp32/examples/ESP32_GetChipID/project.json b/tests/vendor/arduino-esp32/examples/ESP32_GetChipID/project.json new file mode 100644 index 000000000..a9df5493f --- /dev/null +++ b/tests/vendor/arduino-esp32/examples/ESP32_GetChipID/project.json @@ -0,0 +1,61 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "arduino-esp32-ESP32_GetChipID", + "description": "GetChipID on the ESP32-DevKitC V4, plugged into USB; Serial is UART0 through the CP2102N.", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + } + ], + "nets": { + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1" + ], + "USB5V": [ + "USB.+", + "B1.VBUS" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/arduino-esp32/examples/ESP32_GetChipID/scenario.json b/tests/vendor/arduino-esp32/examples/ESP32_GetChipID/scenario.json new file mode 100644 index 000000000..4b56af140 --- /dev/null +++ b/tests/vendor/arduino-esp32/examples/ESP32_GetChipID/scenario.json @@ -0,0 +1,34 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "ESP32_GetChipID", + "until": "3600ms", + "description": "GetChipID on the ESP32: the chip as ESP.getChipModel, getChipRevision and getChipCores report it (ESP32-D0WD-V3, 301 for v3.1, two cores) and the ESP8266-style ID, the eFuse MAC's last three bytes (24:0A:C4:45:6D:62: 0x456D62), printed again after 3 s. Serial.printf's \\n goes out alone.", + "inputs": [], + "assertions": [ + { + "id": "model", + "at": "1s", + "probe": "console", + "expect": { + "contains": "ESP32 Chip model = ESP32-D0WD-V3 Rev 301\nThis chip has 2 cores\nChip ID: 4549986\r\n" + } + }, + { + "id": "once", + "at": "1s", + "probe": "console", + "expect": { + "not_contains": "4549986\r\nESP32" + } + }, + { + "id": "again", + "at": "3500ms", + "probe": "console", + "expect": { + "contains": "Chip ID: 4549986\r\nESP32 Chip model = ESP32-D0WD-V3 Rev 301\n" + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/arduino-esp32/examples/ESP32_ReadAnalogVoltage/project.json b/tests/vendor/arduino-esp32/examples/ESP32_ReadAnalogVoltage/project.json new file mode 100644 index 000000000..0378b2579 --- /dev/null +++ b/tests/vendor/arduino-esp32/examples/ESP32_ReadAnalogVoltage/project.json @@ -0,0 +1,78 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "arduino-esp32-ESP32_ReadAnalogVoltage", + "description": "ReadAnalogVoltage on the ESP32-DevKitC V4: A0 is GPIO36 (the header's VP), fed 1.1 V from a source.", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + }, + { + "id": "V1", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 1.1 + }, + "layout": { + "x": 120, + "y": 460 + } + } + ], + "nets": { + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1", + "V1.-" + ], + "USB5V": [ + "USB.+", + "B1.VBUS" + ], + "A0": [ + "V1.+", + "B1.VP" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/arduino-esp32/examples/ESP32_ReadAnalogVoltage/scenario.json b/tests/vendor/arduino-esp32/examples/ESP32_ReadAnalogVoltage/scenario.json new file mode 100644 index 000000000..8bde6d32c --- /dev/null +++ b/tests/vendor/arduino-esp32/examples/ESP32_ReadAnalogVoltage/scenario.json @@ -0,0 +1,18 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "ESP32_ReadAnalogVoltage", + "until": "1200ms", + "description": "ReadAnalogVoltage on the ESP32: the sketch converts as for the Uno (value x 5.0 / 1023), so the ESP32's 12-bit 1118 for 1.1 V prints 5.46, as it does on a real ESP32.", + "inputs": [], + "assertions": [ + { + "id": "reads", + "at": "1s", + "probe": "console", + "expect": { + "contains": "\r\n5.46\r\n5.46\r\n5.46\r\n" + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/arduino-esp32/examples/ESP32_RepeatTimer/project.json b/tests/vendor/arduino-esp32/examples/ESP32_RepeatTimer/project.json new file mode 100644 index 000000000..300352de6 --- /dev/null +++ b/tests/vendor/arduino-esp32/examples/ESP32_RepeatTimer/project.json @@ -0,0 +1,61 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "arduino-esp32-ESP32_RepeatTimer", + "description": "RepeatTimer on the ESP32-DevKitC V4: BTN_STOP_ALARM is GPIO0, the board's own Boot button (SW1).", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + } + ], + "nets": { + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1" + ], + "USB5V": [ + "USB.+", + "B1.VBUS" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/arduino-esp32/examples/ESP32_RepeatTimer/scenario.json b/tests/vendor/arduino-esp32/examples/ESP32_RepeatTimer/scenario.json new file mode 100644 index 000000000..ab30ee778 --- /dev/null +++ b/tests/vendor/arduino-esp32/examples/ESP32_RepeatTimer/scenario.json @@ -0,0 +1,47 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "ESP32_RepeatTimer", + "until": "6s", + "description": "RepeatTimer: a timer at 1 MHz with a 1 s auto-reload alarm, its ISR giving a semaphore the loop prints from, with millis() as the ISR saw it; the board's Boot button (IO0) pressed at 3.5 s ends the timer, so there is no fourth. The alarms come at 1006, 2006 and 3006 ms of millis(): setup starts the timer 6 ms after the clock millis() reads began, later than on the C3.", + "inputs": [ + { + "at": "3500ms", + "target": "B1.SW1", + "input": "pressed", + "value": true + }, + { + "at": "3700ms", + "target": "B1.SW1", + "input": "pressed", + "value": false + } + ], + "assertions": [ + { + "id": "first", + "at": "1200ms", + "probe": "console", + "expect": { + "contains": "onTimer no. 1 at 1006 ms\r\n" + } + }, + { + "id": "third", + "at": "3400ms", + "probe": "console", + "expect": { + "contains": "onTimer no. 2 at 2006 ms\r\nonTimer no. 3 at 3006 ms\r\n" + } + }, + { + "id": "stopped", + "at": "6s", + "probe": "console", + "expect": { + "not_contains": "onTimer no. 4" + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/arduino-esp32/run.py b/tests/vendor/arduino-esp32/run.py index a99c3050f..1f284a934 100644 --- a/tests/vendor/arduino-esp32/run.py +++ b/tests/vendor/arduino-esp32/run.py @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright 2026 Junior Deogracias """Arduino sketches built with Espressif's Arduino-ESP32 core, unmodified, on -EmbSIM's ESP32-C3-DevKitM-1 (the RTOS boards plan, part 2, step 7; 01 §8.2). +EmbSIM's ESP32-C3-DevKitM-1 (the RTOS boards plan, part 2, step 7; 01 §8.2) +and, for the examples named ESP32_*, its ESP32-DevKitC V4. The core is not vendored. --cli names arduino-cli and --config its configuration, in whose data directory the esp32 platform (3.2.0, on ESP-IDF @@ -14,7 +15,8 @@ Each example under examples// is one of those sketches (EXAMPLES below names where), compiled as the IDE compiles it for "ESP32C3 Dev Module" (`arduino-cli compile --fqbn esp32:esp32:esp32c3`, the board's defaults: -UART0 as Serial, 4 MB flash in QIO at 80 MHz). The build's merged image +UART0 as Serial, 4 MB flash in QIO at 80 MHz), the ESP32_* ones for "ESP32 +Dev Module" (esp32:esp32:esp32, its defaults). The build's merged image (bootloader, partition table, boot_app0 and the sketch at their offsets, the rest erased) runs examples//project.json, or this directory's, under the example's scenario.json, whose assertions must all pass. @@ -36,10 +38,19 @@ from vendor_run import run_scenario, sh # noqa: E402 FQBN = "esp32:esp32:esp32c3" +# the board an example is compiled for, when not "ESP32C3 Dev Module" (its +# project.json names the EmbSIM board): "ESP32 Dev Module" for the +# ESP32-DevKitC V4's ESP32_ examples +FQBNS = {"ESP32_": "esp32:esp32:esp32"} PLATFORM = "3.2.0" # examples// and its sketch: the IDE's built-in examples ("builtin", # arduino-examples' examples/) or the core's ("core", its libraries/) EXAMPLES = { + "ESP32_AnalogReadSerial": ("builtin", "01.Basics/AnalogReadSerial"), + "ESP32_ReadAnalogVoltage": ("builtin", "01.Basics/ReadAnalogVoltage"), + "ESP32_DigitalReadSerial": ("builtin", "01.Basics/DigitalReadSerial"), + "ESP32_GetChipID": ("core", "ESP32/examples/ChipID/GetChipID"), + "ESP32_RepeatTimer": ("core", "ESP32/examples/Timer/RepeatTimer"), "Blink": ("builtin", "01.Basics/Blink"), "DigitalReadSerial": ("builtin", "01.Basics/DigitalReadSerial"), "Fade": ("builtin", "01.Basics/Fade"), @@ -63,12 +74,16 @@ def platform_dir(cli: str, config: str) -> Path: return d if (d / "platform.txt").exists() else None -def build(cli: str, config: str, sketch: Path, out: Path) -> Path: +def fqbn_of(name: str) -> str: + return next((f for prefix, f in FQBNS.items() if name.startswith(prefix)), FQBN) + + +def build(cli: str, config: str, sketch: Path, out: Path, fqbn: str = FQBN) -> Path: """The sketch compiled as the IDE compiles it: its merged flash image""" - work = out / sketch.name + work = out / fqbn.rsplit(":", 1)[-1] / sketch.name shutil.rmtree(work, ignore_errors=True) shutil.copytree(sketch, work / sketch.name) - sh([cli, "--config-file", config, "compile", "--fqbn", FQBN, "--output-dir", work / "out", work / sketch.name]) + sh([cli, "--config-file", config, "compile", "--fqbn", fqbn, "--output-dir", work / "out", work / sketch.name]) return work / "out" / f"{sketch.name}.ino.merged.bin" @@ -99,7 +114,7 @@ def main() -> int: for name in names: where, path = EXAMPLES[name] sketch = (Path(args.examples) / "examples" if where == "builtin" else core / "libraries") / path - flash = build(args.cli, args.config, sketch, work / "build") + flash = build(args.cli, args.config, sketch, work / "build", fqbn_of(name)) mine = HERE / "examples" / name project = mine / "project.json" if (mine / "project.json").exists() else HERE / "project.json" bad += not run_scenario(Path(args.embsim), project, name, flash, mine / "scenario.json", work / "run", From 3eba631405ddc249f3b42966dd169d2dc2338af3 Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 05:38:20 +0000 Subject: [PATCH 14/16] ESP32: GPIO's pad mask without a truncating cast (MSVC C4310) (u32)PADS cut a 64-bit constant, which MSVC's /W4 /WX rejects; the low word is taken with a mask instead. --- core/mcu/esp32/soc/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/mcu/esp32/soc/gpio.c b/core/mcu/esp32/soc/gpio.c index df156be19..b2941fefd 100644 --- a/core/mcu/esp32/soc/gpio.c +++ b/core/mcu/esp32/soc/gpio.c @@ -406,7 +406,7 @@ static void set_clr(struct esk_rf_reg *r, int set, u32 v, u32 mask) static void gp_write(void *ctx, u32 off, int n, u32 v) { struct e32_gpio *k = (struct e32_gpio *)ctx; - const u32 lo = (u32)PADS, hi = (u32)(PADS >> 32) & 0xffu; + const u32 lo = (u32)(PADS & 0xffffffffull), hi = (u32)(PADS >> 32) & 0xffu; switch (off) { case 0x38: case 0x3C: case 0x40: case 0x60: case 0x64: case 0x68: case 0x6C: return; /* read-only */ From 54f37c8d99d2792d10f5cc9854f9278c12da679a Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 06:07:02 +0000 Subject: [PATCH 15/16] LX6: MOVF/MOVT compare the boolean as unsigned (MSVC C4389) The branch register's bit is unsigned, the comparison's result an int: MSVC's /W4 /WX rejects the mixed ==. --- core/mcu/xtensa/lx6.c | 2 +- core/mcu/xtensa/lx6fp.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/core/mcu/xtensa/lx6.c b/core/mcu/xtensa/lx6.c index 7be442539..d2fb215f9 100644 --- a/core/mcu/xtensa/lx6.c +++ b/core/mcu/xtensa/lx6.c @@ -1211,7 +1211,7 @@ static void exec(struct lx6 *c, u32 w, u32 len) case 12: case 13: /* MOVF MOVT */ if (win(c, r > s ? r : s)) return; - if (((c->br >> t) & 1u) == (op2 == 13)) + if (((c->br >> t) & 1u) == (u32)(op2 == 13)) AR(c, r) = AR(c, s); return; case 14: { /* RUR */ diff --git a/core/mcu/xtensa/lx6fp.c b/core/mcu/xtensa/lx6fp.c index 411a11b62..8c3b1786e 100644 --- a/core/mcu/xtensa/lx6fp.c +++ b/core/mcu/xtensa/lx6fp.c @@ -408,7 +408,7 @@ int esk_lx6_fp(struct lx6 *c, u32 w) return 0; } if (op2 == 12 || op2 == 13) { /* MOVF.S MOVT.S */ - if (((esk_lx6_br(c) >> t) & 1u) == (op2 == 13)) + if (((esk_lx6_br(c) >> t) & 1u) == (u32)(op2 == 13)) f[r] = f[s]; return 0; } From 36685afed9c8bccca1fcce9f6323091c961a97d4 Mon Sep 17 00:00:00 2001 From: Junior Deogracias Date: Sun, 8 Nov 2026 06:36:50 +0000 Subject: [PATCH 16/16] ESP32: the DACs, with ESP-IDF's dac_oneshot RTC_IO's PAD_DAC1 and PAD_DAC2: with the pad the RTC IO MUX's and the DAC powered, GPIO25 and GPIO26 carry VDD3P3_RTC x code / 255 (the GPIO model hands the pad to the DAC as an analog output). ESP-IDF's dac/dac_oneshot runs unmodified on the DevKitC, its ADC2 reading both DACs back on their pads (esp32_dac_oneshot 4/4). For that the runtime's pin_volts gives a pin's own DAC voltage when its net has no analog part (it gave the digital level, so an ADC read 0). --- CHANGELOG.md | 6 +- catalog/mcus/espressif/esp32/mcu.json | 17 ++-- core/mcu/esp32/soc/esp32.h | 6 ++ core/mcu/esp32/soc/gpio.c | 6 ++ core/mcu/esp32/soc/rtcio.c | 82 +++++++++++++++++++ core/mcu/mcu.c | 2 + core/mcu/models.c | 1 + docs/STATUS.md | 5 +- docs/coverage.md | 8 +- .../examples/esp32_dac_oneshot/project.json | 61 ++++++++++++++ .../examples/esp32_dac_oneshot/scenario.json | 42 ++++++++++ tests/vendor/esp-idf/run.py | 2 + 12 files changed, 225 insertions(+), 13 deletions(-) create mode 100644 core/mcu/esp32/soc/rtcio.c create mode 100644 tests/vendor/esp-idf/examples/esp32_dac_oneshot/project.json create mode 100644 tests/vendor/esp-idf/examples/esp32_dac_oneshot/scenario.json diff --git a/CHANGELOG.md b/CHANGELOG.md index ea0176189..c51c9a1ab 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -22,7 +22,7 @@ versions follow semantic versioning. There is no release yet. strapping, UART0-2, TIMG0/1, SPI0/1 with the GT25Q32A flash, SHA, LEDC, I2C0/1 (master and slave, 16 commands, APB_CLK timing; DPORT's PERIP_RST_EN resets them), the RMT's eight channels, the SAR ADCs - through SENS, the internal analog I2C, RNG and the AHB view. + through SENS, the two DACs through RTC_IO, the internal analog I2C, RNG and the AHB view. - Added the `emblink/esp32_devkitc` board (ESP32-DevKitC V4, WROOM-32E) with its power path, LED, Boot and EN buttons, headers and fixtures. - Espressif's ROM, ESP-IDF v5.4's bootloader and hello_world run unmodified @@ -31,7 +31,9 @@ versions follow semantic versioning. There is no release yet. 24LC256, `esp32_gptimer` 17/17, `esp32_uart_echo` 6/6 on UART2, `esp32_real_time_stats` 10/10 across both cores, `esp32_blink_strip` 7/7 on a WS2812B through the RMT, - `esp32_adc_oneshot_read` 6/6 with the eFuse Vref's calibration; + `esp32_adc_oneshot_read` 6/6 with the eFuse Vref's calibration, + `esp32_dac_oneshot` 4/4 (the DACs read back by ADC2); an ADC reads a + pin's own DAC on a net with no analog part (the runtime's pin_volts); Arduino-ESP32's AnalogReadSerial, ReadAnalogVoltage, DigitalReadSerial, GetChipID and RepeatTimer for "ESP32 Dev Module" in `tests/vendor/arduino-esp32` (`ESP32_*`); DBREAKC's MASK now marks the diff --git a/catalog/mcus/espressif/esp32/mcu.json b/catalog/mcus/espressif/esp32/mcu.json index a2f031e7f..d8e4d37bf 100644 --- a/catalog/mcus/espressif/esp32/mcu.json +++ b/catalog/mcus/espressif/esp32/mcu.json @@ -207,6 +207,10 @@ { "match": "SENS", "model": "esp32-sens" + }, + { + "match": "RTC_IO", + "model": "esp32-rtcio" } ], "io": { @@ -275,15 +279,16 @@ }, "fidelity": { "functional": { - "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts, MEM_RX_STATUS's addresses that ESP-IDF counts the bytes waiting from), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), I2C0 and I2C1 (master and slave on the open-drain lines through the matrix, the 16 commands with RSTART, WRITE, READ, STOP and END, the bus timing in APB_CLK cycles, ACK checks, arbitration, the SCL timeout, the 32-byte FIFOs through DATA and its AHB view, 7- and 10-bit slave addresses; ESP-IDF's i2c_eeprom runs on a 24LC256), the RMT (eight channels sending or receiving through the matrix, 64-word blocks of the 512-word RAM, end markers, continuous mode, wrap, TX_LIM's threshold, the carrier, the receiver's idle threshold and filter, the RAM through CHnDATA; ESP-IDF's led_strip lights a WS2812B), the SAR ADCs as SENS's RTC controller drives them (one conversion at a time on ADC1's eight and ADC2's ten pads, the attenuations, 9 to 12 bits, the converter's inverted output and DATA_INV, the conversion's time; the transfer the line ESP-IDF's Vref calibration fits for the chip, its eFuse Vref), PERIP_RST_EN's resets of I2C0, I2C1 and LEDC, the internal analog I2C master, the random number generator and the peripherals' AHB view. The evidence: test_lx6.c's programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16) and the APP_CPU's ROM data kept apart; ESP-IDF v5.4's hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats, blink with its LED strip and adc oneshot_read built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart; Arduino-ESP32 3.2.0's sketches for \"ESP32 Dev Module\" (AnalogReadSerial, ReadAnalogVoltage, DigitalReadSerial, GetChipID, RepeatTimer, with FreeRTOS's stack-end watchpoints on); the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin.", + "claims": "The two Xtensa LX6 cores (mcu/xtensa/lx6.c, lx6fp.c) as Espressif's core-isa.h configures them: the core and density instructions, the windowed registers (64, the overflow check of every instruction, CALL4/8/12, ENTRY, RETW and its underflow, MOVSP, ROTW, L32E/S32E), zero-overhead loops, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, booleans, S32C1I with SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), the MAC16 package, the single-precision FPU (IEEE rounding modes and flags; the division and square root sequences libgcc runs give correctly rounded results), XEA2 exceptions with relocatable vectors, 32 interrupts at core-isa.h's levels and types (level, edge, software, the CCOMPARE0-2 timers against CCOUNT, NMI), RSIL, WAITI, RFI, the debug option's BREAK, IBREAK, DBREAK and ICOUNT, region protection (eight 512 MB regions, 15 no access), unaligned loads and stores, and the instruction bus's 32-bit-only data accesses. Both cores share the machine, the APP_CPU held in reset until DPORT releases it and seeing the ROM with its pointers into the PRO_CPU's ROM data moved to its own, as Espressif's own APP_CPU ROM image has them. The boot: Espressif's ROM (esp32_rev300_rom.elf, chip revision v3) from the reset vector, its banner, the strapping pins (GPIO_STRAP: SPI_FAST_FLASH_BOOT, or the download mode with GPIO0 low), the reset causes (RTC_CNTL), the eFuse glitch check, the flash read through SPI1, ESP-IDF's second-stage bootloader and its image check on the SHA accelerator, the caches' flash MMU, and the application on both cores. The models: DPORT (the APP_CPU's reset, clock and stall, CPU_PER_CONF, the caches' flush and state, the flash MMU tables, the interrupt matrix's 69 sources, the cross-CPU interrupts), RTC_CNTL (reset causes, the RTC timer, the RTC watchdog with its flash-boot protection, the software resets and stalls, the store registers, SOC_CLK_SEL), APB_CTRL (the CPU and APB clocks from XTAL, PLL or RC_FAST), the eFuse controller with the chip's factory bits (ESP32-D0WD-V3 v3.1, a MAC with its CRC, or the board settings'), GPIO and IO_MUX (40 pads, the matrix, pulls, open drain, interrupts on each CPU, the strapping latch), UART0-2 (FIFOs, frames at the baud rate, interrupts, MEM_RX_STATUS's addresses that ESP-IDF counts the bytes waiting from), TIMG0/1 (T0, T1, the LAC timer, the MWDT with its flash-boot protection, the RTC_SLOW_CLK calibration), SPI0/SPI1 with the module's Giantec GT25Q32A flash (C4 60 16, the ID the owner's board reports), the SHA accelerator (SHA-1, -256, -384, -512), LEDC (eight high-speed and eight low-speed PWM channels on eight timers, fading, on the matrix's ledc_hs/ls_sig_out), I2C0 and I2C1 (master and slave on the open-drain lines through the matrix, the 16 commands with RSTART, WRITE, READ, STOP and END, the bus timing in APB_CLK cycles, ACK checks, arbitration, the SCL timeout, the 32-byte FIFOs through DATA and its AHB view, 7- and 10-bit slave addresses; ESP-IDF's i2c_eeprom runs on a 24LC256), the RMT (eight channels sending or receiving through the matrix, 64-word blocks of the 512-word RAM, end markers, continuous mode, wrap, TX_LIM's threshold, the carrier, the receiver's idle threshold and filter, the RAM through CHnDATA; ESP-IDF's led_strip lights a WS2812B), the SAR ADCs as SENS's RTC controller drives them (one conversion at a time on ADC1's eight and ADC2's ten pads, the attenuations, 9 to 12 bits, the converter's inverted output and DATA_INV, the conversion's time; the transfer the line ESP-IDF's Vref calibration fits for the chip, its eFuse Vref), the two DACs on GPIO25 and GPIO26 (RTC_IO's PAD_DAC1/2: powered and the RTC IO MUX's, VDD3P3_RTC x code / 255 on the pad, which ADC2 reads back), PERIP_RST_EN's resets of I2C0, I2C1 and LEDC, the internal analog I2C master, the random number generator and the peripherals' AHB view. The evidence: test_lx6.c's programs assembled by Espressif's assembler (integer, shifts, multiply and divide, loops, branches, memory with S32C1I, windowed recursion through the ROM's own window vectors, SYSCALL, the CCOMPARE timer interrupt, FPU, MAC16) and the APP_CPU's ROM data kept apart; ESP-IDF v5.4's hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats, blink with its LED strip, adc oneshot_read and dac_oneshot built unmodified for the esp32 target on the ESP32-DevKitC V4, from the ROM's banner to esp_restart; Arduino-ESP32 3.2.0's sketches for \"ESP32 Dev Module\" (AnalogReadSerial, ReadAnalogVoltage, DigitalReadSerial, GetChipID, RepeatTimer, with FreeRTOS's stack-end watchpoints on); the ROM image equals Espressif QEMU's esp32-v3-rom.bin byte for byte, and the APP_CPU's view of it QEMU's esp32-v3-rom-app.bin.", "omissions": [ "Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written)", "the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept", "PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts", "RMT: the memory's power-down (MEM_PD), STATUS's STATE and the APB-side error bits, the carrier on an idle output", "the SAR ADCs: the nonlinearity above about 2450 mV at 11 dB and a chip's spread from the fitted line, noise, the ULP's and the digital controller's (DMA, I2S) conversions, the Hall sensor, ADC2's arbitration with Wi-Fi, the RTC IO MUX's routing of a pad to the ADC (not checked)", + "the DACs: the cosine-wave generator and the DMA path (I2S0), the output's impedance (a stiff source: the datasheet gives none) and its offset and nonlinearity", "I2C: the non-FIFO mode (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, the input filters (only their share of the SCL high time), 10-bit addressing's R/W check", - "the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption", + "the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, the touch sensor, the RTC IO MUX's other pads and the ULP coprocessor, the AES and RSA accelerators, flash encryption", "sleep modes (light and deep sleep, the power domains), brown-out", "the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection" ], @@ -299,6 +304,7 @@ "repo:tests/vendor/esp-idf/examples/esp32_real_time_stats/scenario.json", "repo:tests/vendor/esp-idf/examples/esp32_blink_strip/scenario.json", "repo:tests/vendor/esp-idf/examples/esp32_adc_oneshot_read/scenario.json", + "repo:tests/vendor/esp-idf/examples/esp32_dac_oneshot/scenario.json", "repo:tests/vendor/arduino-esp32/run.py" ] }, @@ -405,19 +411,20 @@ }, "i18n": { "fr": { - "source": "a076e310391c", + "source": "97aa22899d11", "description": "Espressif ESP32 (ESP32-D0WD-V3, révision de puce v3.1) : deux cœurs Xtensa LX6 jusqu'à 240 MHz, 520 Kio de SRAM, 448 Kio de ROM, 16 Kio de mémoire RTC, une flash SPI externe derrière les caches des cœurs, Wi-Fi et Bluetooth ; le MCU de l'ESP32-DevKitC. La ROM d'Espressif, le bootloader de second niveau d'ESP-IDF et les applications ESP-IDF tournent sur les deux cœurs ; les radios ne sont pas encore modélisées.", "fidelity": { "functional": { - "claims": "Les deux cœurs Xtensa LX6 (mcu/xtensa/lx6.c, lx6fp.c) tels que les configure le core-isa.h d'Espressif : les instructions de base et de densité, les registres fenêtrés (64, le contrôle de débordement de chaque instruction, CALL4/8/12, ENTRY, RETW et son sous-débordement, MOVSP, ROTW, L32E/S32E), les boucles sans surcoût, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, les booléens, S32C1I avec SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), le paquet MAC16, la FPU simple précision (modes d'arrondi et drapeaux IEEE ; les séquences de division et de racine carrée qu'exécute libgcc donnent des résultats correctement arrondis), les exceptions XEA2 avec vecteurs relocalisables, 32 interruptions aux niveaux et types de core-isa.h (niveau, front, logicielles, les temporisateurs CCOMPARE0-2 contre CCOUNT, NMI), RSIL, WAITI, RFI, BREAK, IBREAK, DBREAK et ICOUNT de l'option de débogage, la protection par régions (huit régions de 512 Mo, 15 sans accès), les chargements et écritures non alignés, et les accès de données en 32 bits seulement du bus d'instructions. Les deux cœurs partagent la machine, l'APP_CPU maintenu en reset jusqu'à ce que DPORT le libère et voyant la ROM avec ses pointeurs vers les données ROM du PRO_CPU déplacés vers les siennes, comme dans l'image ROM APP_CPU d'Espressif. Le démarrage : la ROM d'Espressif (esp32_rev300_rom.elf, révision v3) depuis le vecteur de reset, sa bannière, les broches de configuration (GPIO_STRAP : SPI_FAST_FLASH_BOOT, ou le mode téléchargement avec GPIO0 bas), les causes de reset (RTC_CNTL), le contrôle anti-glitch de l'eFuse, la lecture de la flash par SPI1, le bootloader de second niveau d'ESP-IDF et sa vérification d'image sur l'accélérateur SHA, la MMU flash des caches, et l'application sur les deux cœurs. Les modèles : DPORT (reset, horloge et blocage de l'APP_CPU, CPU_PER_CONF, vidage et état des caches, tables de la MMU flash, les 69 sources de la matrice d'interruptions, les interruptions inter-CPU), RTC_CNTL (causes de reset, le temporisateur RTC, le chien de garde RTC avec sa protection au démarrage sur flash, les resets et blocages logiciels, les registres de stockage, SOC_CLK_SEL), APB_CTRL (les horloges CPU et APB depuis XTAL, PLL ou RC_FAST), le contrôleur eFuse avec les bits d'usine de la puce (ESP32-D0WD-V3 v3.1, une MAC avec son CRC, ou celle des réglages de la carte), GPIO et IO_MUX (40 plots, la matrice, tirages, drain ouvert, interruptions sur chaque CPU, le verrou de configuration), UART0-2 (FIFO, trames au débit, interruptions, les adresses de MEM_RX_STATUS d'après lesquelles ESP-IDF compte les octets en attente), TIMG0/1 (T0, T1, le temporisateur LAC, le MWDT avec sa protection au démarrage sur flash, la calibration de RTC_SLOW_CLK), SPI0/SPI1 avec la flash Giantec GT25Q32A du module (C4 60 16, l'identifiant que rapporte la carte du propriétaire), l'accélérateur SHA (SHA-1, -256, -384, -512), LEDC (huit canaux MLI rapides et huit lents sur huit temporisateurs, le fondu, sur ledc_hs/ls_sig_out de la matrice), I2C0 et I2C1 (maître et esclave sur les lignes à drain ouvert à travers la matrice, les 16 commandes avec RSTART, WRITE, READ, STOP et END, le timing du bus en cycles d'APB_CLK, les contrôles d'ACK, l'arbitrage, le délai d'attente sur SCL, les FIFO de 32 octets par DATA et sa vue AHB, les adresses esclaves sur 7 et 10 bits ; l'exemple i2c_eeprom d'ESP-IDF fonctionne avec une 24LC256), le RMT (huit canaux qui émettent ou reçoivent à travers la matrice, des blocs de 64 mots de la RAM de 512 mots, les marqueurs de fin, le mode continu, le rebouclage, le seuil de TX_LIM, la porteuse, le seuil d'inactivité et le filtre du récepteur, la RAM par CHnDATA ; le led_strip d'ESP-IDF allume une WS2812B), les ADC SAR tels que les pilote le contrôleur RTC de SENS (une conversion à la fois sur les huit plots de l'ADC1 et les dix de l'ADC2, les atténuations, 9 à 12 bits, la sortie inversée du convertisseur et DATA_INV, la durée de la conversion ; la caractéristique est la droite que la calibration Vref d'ESP-IDF ajuste pour la puce, avec son Vref d'eFuse), les resets de PERIP_RST_EN pour I2C0, I2C1 et LEDC, le maître I2C analogique interne, le générateur de nombres aléatoires et la vue AHB des périphériques. Les preuves : les programmes de test_lx6.c assemblés par l'assembleur d'Espressif (entiers, décalages, multiplication et division, boucles, branchements, mémoire avec S32C1I, récursion fenêtrée à travers les vecteurs de fenêtre de la ROM, SYSCALL, l'interruption du temporisateur CCOMPARE, FPU, MAC16) et les données ROM de l'APP_CPU tenues à part ; hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats, blink avec son ruban de LED et adc oneshot_read d'ESP-IDF v5.4 compilés sans modification pour la cible esp32 sur l'ESP32-DevKitC V4, de la bannière de la ROM jusqu'à esp_restart ; les croquis d'Arduino-ESP32 3.2.0 pour « ESP32 Dev Module » (AnalogReadSerial, ReadAnalogVoltage, DigitalReadSerial, GetChipID, RepeatTimer, avec les points d'arrêt de fin de pile de FreeRTOS actifs) ; l'image ROM est identique octet pour octet à l'esp32-v3-rom.bin du QEMU d'Espressif, et la vue qu'en a l'APP_CPU à son esp32-v3-rom-app.bin.", + "claims": "Les deux cœurs Xtensa LX6 (mcu/xtensa/lx6.c, lx6fp.c) tels que les configure le core-isa.h d'Espressif : les instructions de base et de densité, les registres fenêtrés (64, le contrôle de débordement de chaque instruction, CALL4/8/12, ENTRY, RETW et son sous-débordement, MOVSP, ROTW, L32E/S32E), les boucles sans surcoût, MUL16/MULL/MULUH/MULSH, QUOS/QUOU/REMS/REMU, NSA, MIN/MAX, SEXT, CLAMPS, les booléens, S32C1I avec SCOMPARE1, THREADPTR, MISC0-3, PRID (0xCDCD, 0xABAB), le paquet MAC16, la FPU simple précision (modes d'arrondi et drapeaux IEEE ; les séquences de division et de racine carrée qu'exécute libgcc donnent des résultats correctement arrondis), les exceptions XEA2 avec vecteurs relocalisables, 32 interruptions aux niveaux et types de core-isa.h (niveau, front, logicielles, les temporisateurs CCOMPARE0-2 contre CCOUNT, NMI), RSIL, WAITI, RFI, BREAK, IBREAK, DBREAK et ICOUNT de l'option de débogage, la protection par régions (huit régions de 512 Mo, 15 sans accès), les chargements et écritures non alignés, et les accès de données en 32 bits seulement du bus d'instructions. Les deux cœurs partagent la machine, l'APP_CPU maintenu en reset jusqu'à ce que DPORT le libère et voyant la ROM avec ses pointeurs vers les données ROM du PRO_CPU déplacés vers les siennes, comme dans l'image ROM APP_CPU d'Espressif. Le démarrage : la ROM d'Espressif (esp32_rev300_rom.elf, révision v3) depuis le vecteur de reset, sa bannière, les broches de configuration (GPIO_STRAP : SPI_FAST_FLASH_BOOT, ou le mode téléchargement avec GPIO0 bas), les causes de reset (RTC_CNTL), le contrôle anti-glitch de l'eFuse, la lecture de la flash par SPI1, le bootloader de second niveau d'ESP-IDF et sa vérification d'image sur l'accélérateur SHA, la MMU flash des caches, et l'application sur les deux cœurs. Les modèles : DPORT (reset, horloge et blocage de l'APP_CPU, CPU_PER_CONF, vidage et état des caches, tables de la MMU flash, les 69 sources de la matrice d'interruptions, les interruptions inter-CPU), RTC_CNTL (causes de reset, le temporisateur RTC, le chien de garde RTC avec sa protection au démarrage sur flash, les resets et blocages logiciels, les registres de stockage, SOC_CLK_SEL), APB_CTRL (les horloges CPU et APB depuis XTAL, PLL ou RC_FAST), le contrôleur eFuse avec les bits d'usine de la puce (ESP32-D0WD-V3 v3.1, une MAC avec son CRC, ou celle des réglages de la carte), GPIO et IO_MUX (40 plots, la matrice, tirages, drain ouvert, interruptions sur chaque CPU, le verrou de configuration), UART0-2 (FIFO, trames au débit, interruptions, les adresses de MEM_RX_STATUS d'après lesquelles ESP-IDF compte les octets en attente), TIMG0/1 (T0, T1, le temporisateur LAC, le MWDT avec sa protection au démarrage sur flash, la calibration de RTC_SLOW_CLK), SPI0/SPI1 avec la flash Giantec GT25Q32A du module (C4 60 16, l'identifiant que rapporte la carte du propriétaire), l'accélérateur SHA (SHA-1, -256, -384, -512), LEDC (huit canaux MLI rapides et huit lents sur huit temporisateurs, le fondu, sur ledc_hs/ls_sig_out de la matrice), I2C0 et I2C1 (maître et esclave sur les lignes à drain ouvert à travers la matrice, les 16 commandes avec RSTART, WRITE, READ, STOP et END, le timing du bus en cycles d'APB_CLK, les contrôles d'ACK, l'arbitrage, le délai d'attente sur SCL, les FIFO de 32 octets par DATA et sa vue AHB, les adresses esclaves sur 7 et 10 bits ; l'exemple i2c_eeprom d'ESP-IDF fonctionne avec une 24LC256), le RMT (huit canaux qui émettent ou reçoivent à travers la matrice, des blocs de 64 mots de la RAM de 512 mots, les marqueurs de fin, le mode continu, le rebouclage, le seuil de TX_LIM, la porteuse, le seuil d'inactivité et le filtre du récepteur, la RAM par CHnDATA ; le led_strip d'ESP-IDF allume une WS2812B), les ADC SAR tels que les pilote le contrôleur RTC de SENS (une conversion à la fois sur les huit plots de l'ADC1 et les dix de l'ADC2, les atténuations, 9 à 12 bits, la sortie inversée du convertisseur et DATA_INV, la durée de la conversion ; la caractéristique est la droite que la calibration Vref d'ESP-IDF ajuste pour la puce, avec son Vref d'eFuse), les deux DAC sur GPIO25 et GPIO26 (PAD_DAC1/2 de RTC_IO : alimentés et confiés à l'IO MUX RTC, VDD3P3_RTC x code / 255 sur le plot, que l'ADC2 relit), les resets de PERIP_RST_EN pour I2C0, I2C1 et LEDC, le maître I2C analogique interne, le générateur de nombres aléatoires et la vue AHB des périphériques. Les preuves : les programmes de test_lx6.c assemblés par l'assembleur d'Espressif (entiers, décalages, multiplication et division, boucles, branchements, mémoire avec S32C1I, récursion fenêtrée à travers les vecteurs de fenêtre de la ROM, SYSCALL, l'interruption du temporisateur CCOMPARE, FPU, MAC16) et les données ROM de l'APP_CPU tenues à part ; hello_world, blink, ledc_basic, i2c_eeprom, gptimer, uart_echo, real_time_stats, blink avec son ruban de LED, adc oneshot_read et dac_oneshot d'ESP-IDF v5.4 compilés sans modification pour la cible esp32 sur l'ESP32-DevKitC V4, de la bannière de la ROM jusqu'à esp_restart ; les croquis d'Arduino-ESP32 3.2.0 pour « ESP32 Dev Module » (AnalogReadSerial, ReadAnalogVoltage, DigitalReadSerial, GetChipID, RepeatTimer, avec les points d'arrêt de fin de pile de FreeRTOS actifs) ; l'image ROM est identique octet pour octet à l'esp32-v3-rom.bin du QEMU d'Espressif, et la vue qu'en a l'APP_CPU à son esp32-v3-rom-app.bin.", "omissions": [ "le Wi-Fi, le Bluetooth et l'étage RF (WIFI_MAC, BB, NRX, FE : leurs registres gardent ce qui y est écrit)", "les instructions de l'accélérateur double précision (F64ADDC, F64ITER et les autres : leurs encodages sont publics, pas ce qu'elles font ; un programme qui en exécute une s'arrête avec un diagnostic), bien que ses registres soient conservés", "la PSRAM (DRAM1), le remappage de démarrage, les permissions d'accès APB/AHB, les régions verrouillées et le timing des caches (les pages mappées sont lues entières), les interruptions d'erreur d'accès de la MMU", "RMT : la mise hors tension de la mémoire (MEM_PD), le champ STATE de STATUS et les bits d'erreur côté APB, la porteuse sur une sortie inactive", "les ADC SAR : la non-linéarité au-delà d'environ 2450 mV à 11 dB et l'écart d'une puce à la droite ajustée, le bruit, les conversions de l'ULP et du contrôleur numérique (DMA, I2S), le capteur à effet Hall, l'arbitrage de l'ADC2 avec le Wi-Fi, le routage d'un plot vers l'ADC par l'IO MUX RTC (non vérifié)", + "les DAC : le générateur d'onde cosinus et la voie DMA (I2S0), l'impédance de sortie (une source idéale : la fiche technique n'en donne pas), leur décalage et leur non-linéarité", "I2C : le mode hors FIFO (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, les filtres d'entrée (seulement leur part du temps haut de SCL), le contrôle R/W de l'adressage sur 10 bits", - "les périphériques sans modèle pour l'instant : I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, les DAC, le capteur tactile, l'IO MUX RTC et le coprocesseur ULP, les accélérateurs AES et RSA, le chiffrement de la flash", + "les périphériques sans modèle pour l'instant : I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, le capteur tactile, les autres plots de l'IO MUX RTC et le coprocesseur ULP, les accélérateurs AES et RSA, le chiffrement de la flash", "les modes de veille (veille légère et profonde, les domaines d'alimentation), la détection de baisse de tension", "le contrôle du schéma de codage 3/4 de l'eFuse, la protection en écriture par champ du BLOCK0" ] diff --git a/core/mcu/esp32/soc/esp32.h b/core/mcu/esp32/soc/esp32.h index 3604387de..fdb5d6f75 100644 --- a/core/mcu/esp32/soc/esp32.h +++ b/core/mcu/esp32/soc/esp32.h @@ -20,6 +20,7 @@ * i2c.c I2C0 and I2C1 * rmt.c the remote control peripheral's eight channels * adc.c the SAR ADCs as SENS's RTC controller drives them + * rtcio.c the RTC IO MUX's DACs * misc.c the random number generator, the AHB view of the * peripherals */ #ifndef ESK_MCU_ESP32_SOC_H @@ -61,6 +62,11 @@ extern const struct esk_dev_ops esk_esp32_rmt_ops; void *esk_esp32_rmt_create(struct esk_mach *s, struct esk_rf_periph *p); extern const struct esk_dev_ops esk_esp32_adc_ops; void *esk_esp32_adc_create(struct esk_mach *s, struct esk_rf_periph *p); +extern const struct esk_dev_ops esk_esp32_rtcio_ops; +void *esk_esp32_rtcio_create(struct esk_mach *s, struct esk_rf_periph *p); +/* DAC1 on GPIO25, DAC2 on GPIO26 (rtcio.c): 1 and the voltage it drives + * behind its output resistance, or 0 when the pad is not the DAC's */ +int esk_esp32_dac_out(struct esk_mach *m, int gpio, double *volts, double *rout); extern const struct esk_dev_ops esk_esp32_sha_ops; void *esk_esp32_sha_create(struct esk_mach *s, struct esk_rf_periph *p); /* the RNG and the AHB view of the peripherals (misc.c): 0, or -1 */ diff --git a/core/mcu/esp32/soc/gpio.c b/core/mcu/esp32/soc/gpio.c index b2941fefd..89be81ebc 100644 --- a/core/mcu/esp32/soc/gpio.c +++ b/core/mcu/esp32/soc/gpio.c @@ -265,6 +265,12 @@ static void settle(struct e32_gpio *k) o.pull = wpu && !wpd ? 1 : wpd && !wpu ? 2 : 0; o.af = af || (mux_sel(k, n) == 0 && n == 3) /* U0RXD */ || (rx >> n & 1u); o.analog = !(mux & MUX_FUN_IE) && !oe; + if (esk_esp32_dac_out(s, n, &o.volts, &o.aout_r)) { /* a DAC's pad */ + o.aout = 1; + o.analog = 1; + o.drive = -1; + drive = 0; + } if (s->host.pin_cfg && (!k->known || memcmp(&k->cfg[n], &o, sizeof o) != 0)) s->host.pin_cfg(s->host.ctx, n / 16, n % 16, &o); k->cfg[n] = o; diff --git a/core/mcu/esp32/soc/rtcio.c b/core/mcu/esp32/soc/rtcio.c new file mode 100644 index 000000000..62087a8c5 --- /dev/null +++ b/core/mcu/esp32/soc/rtcio.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright 2026 Junior Deogracias */ +/* rtcio.c -- the ESP32's RTC IO MUX (RTC_IO, TRM v5 chapter 4.11) as far as + * its two DACs (chapter 29.5): DAC1 on GPIO25 (PAD_DAC1), DAC2 on GPIO26 + * (PAD_DAC2). + * + * - While the pad is the RTC IO MUX's (MUX_SEL) and its DAC powered + * (XPD_DAC, with DAC_XPD_FORCE as ESP-IDF sets it), the pad is the DAC's + * output: VDD3P3_RTC x DAC / 255 for the eight-bit code in PDACn_DAC, + * the relation ESP-IDF's dac_oneshot documents; the GPIO model gives the + * pad that voltage (gpio.c). + * - Writes to the registers settle the pads again. + * Where it differs inside: the output is a stiff source (the datasheet gives + * no output impedance). Not yet: the cosine-wave generator (SENS's + * SAR_DAC_CTRL1/2: SW_TONE_EN, DAC_CW_EN1/2, the scale, phase and offset) + * and the DMA path (DAC_DIG_FORCE, I2S0), whose outputs read as the code + * written; the other RTC pads' functions, pulls and hold. */ +#include + +#include "mcu/esp32/soc/esp32.h" + +#define PAD_DAC1 0x84u +#define PAD_DAC2 0x88u +#define XPD_DAC (1u << 18) +#define MUX_SEL (1u << 17) + +struct e32_rtcio { + struct esk_mach *s; + struct esk_rf_periph *p; +}; + +static struct e32_rtcio *rtcio_of(struct esk_mach *m) +{ + return m->rf ? (struct e32_rtcio *)esk_rf_ctx_of(m->rf, &esk_esp32_rtcio_ops) : 0; +} + +int esk_esp32_dac_out(struct esk_mach *m, int gpio, double *volts, double *rout) +{ + struct e32_rtcio *k = gpio == 25 || gpio == 26 ? rtcio_of(m) : 0; + u32 v; + double vdd; + if (!k) + return 0; + v = esk_rf_read(k->p, gpio == 25 ? PAD_DAC1 : PAD_DAC2, 4); + if (!(v & XPD_DAC) || !(v & MUX_SEL)) + return 0; + vdd = m->vdd > 0.0 ? m->vdd : 3.3; + *volts = vdd * (double)((v >> 19) & 0xffu) / 255.0; + *rout = 1.0; + return 1; +} + +static u32 rio_read(void *ctx, u32 off, int n) +{ + struct e32_rtcio *k = (struct e32_rtcio *)ctx; + return esk_rf_read(k->p, off, n); +} + +static void rio_write(void *ctx, u32 off, int n, u32 v) +{ + struct e32_rtcio *k = (struct e32_rtcio *)ctx; + esk_rf_write(k->p, off, n, v); + if ((off & ~3u) == PAD_DAC1 || (off & ~3u) == PAD_DAC2) + esk_esp32_pins_changed(k->s); +} + +static void rio_reset(void *ctx) { (void)ctx; } + +const struct esk_dev_ops esk_esp32_rtcio_ops = { + "esp32-rtcio", rio_read, rio_write, rio_reset, 0, 0, +}; + +void *esk_esp32_rtcio_create(struct esk_mach *s, struct esk_rf_periph *p) +{ + struct e32_rtcio *k = (struct e32_rtcio *)esk_mach_alloc(s, sizeof *k); + if (!k) + return 0; + memset(k, 0, sizeof *k); + k->s = s; + k->p = p; + return k; +} diff --git a/core/mcu/mcu.c b/core/mcu/mcu.c index 08a3404d5..05464c286 100644 --- a/core/mcu/mcu.c +++ b/core/mcu/mcu.c @@ -773,6 +773,8 @@ static int h_pin_volts(void *ctx, int port, int bit, double *v) n = p->net; if (n->island) *v = esk_net_voltage_now(p->net); /* an ADC samples it now */ + else if (st->pq[port][bit].cfg.aout) + *v = st->pq[port][bit].cfg.volts; /* the pin's own DAC, alone on its net */ else *v = esk_net_value(n) == ESK_L1 ? st->m.vdd : 0.0; return 1; diff --git a/core/mcu/models.c b/core/mcu/models.c index a1fbe3149..b7cfbea77 100644 --- a/core/mcu/models.c +++ b/core/mcu/models.c @@ -75,6 +75,7 @@ static const struct esk_rf_model_type model_types[] = { { "esp32-i2c", &esk_esp32_i2c_ops, esk_esp32_i2c_create }, { "esp32-rmt", &esk_esp32_rmt_ops, esk_esp32_rmt_create }, { "esp32-sens", &esk_esp32_adc_ops, esk_esp32_adc_create }, + { "esp32-rtcio", &esk_esp32_rtcio_ops, esk_esp32_rtcio_create }, { "esp32-iomux", &esk_esp32_iomux_ops, esk_esp32_iomux_create }, { "esp32c3-intmtx", &esk_esp32c3_intmtx_ops, esk_esp32c3_intmtx_create }, { "esp32c3-uart", &esk_esp32c3_uart_ops, esk_esp32c3_uart_create }, diff --git a/docs/STATUS.md b/docs/STATUS.md index 59a456689..4ea1a62bc 100644 --- a/docs/STATUS.md +++ b/docs/STATUS.md @@ -19,11 +19,12 @@ scenarios `esp32_hello_world` (9/9), `esp32_blink` (6/6), reading a 24LC256 at 400 kHz), `esp32_gptimer` (17/17), `esp32_uart_echo` (6/6), `esp32_real_time_stats` (10/10) , `esp32_blink_strip` (7/7, a WS2812B through the RMT) and `esp32_adc_oneshot_read` (6/6, ADC1 and ADC2 -with the eFuse Vref's calibration); Arduino-ESP32's AnalogReadSerial, +with the eFuse Vref's calibration), `esp32_dac_oneshot` (4/4, the DACs +read back by ADC2); Arduino-ESP32's AnalogReadSerial, ReadAnalogVoltage, DigitalReadSerial, GetChipID and RepeatTimer for "ESP32 Dev Module" (`tests/vendor/arduino-esp32`, `ESP32_*`). Not yet: Wi-Fi and Bluetooth, the double-precision accelerator's instructions, the peripherals the -description's fidelity lists (I2S, SPI2/3, the DACs, ...), +description's fidelity lists (I2S, SPI2/3, touch, ...), sleep. The standalone harness below remains as its own qualification fixtures. diff --git a/docs/coverage.md b/docs/coverage.md index dd3902425..ad9dc481a 100644 --- a/docs/coverage.md +++ b/docs/coverage.md @@ -8,7 +8,7 @@ evidence for each model is in [STATUS.md](STATUS.md). | MCU | Modelled | Registers only | Missing | Peripherals | |---|---|---|---|---| -| ESP32 | 19 | 0 | 26 | 45 | +| ESP32 | 20 | 0 | 25 | 45 | | ESP32-C3 | 35 | 0 | 0 | 35 | | ATmega328P | 15 | 0 | 0 | 15 | | PIC24FJ1024GB610 | 11 | 4 | 17 | 32 | @@ -23,7 +23,7 @@ evidence for each model is in [STATUS.md](STATUS.md). ## ESP32 (`espressif/esp32`) Boards: ESP32-DevKitC V4. -19 of 45 peripherals modelled, 0 registers only, 26 missing. +20 of 45 peripherals modelled, 0 registers only, 25 missing. | Peripheral | Model | State | |---|---|---| @@ -39,7 +39,7 @@ Boards: ESP32-DevKitC V4. | FLASH_ENCRYPTION | — | **missing** | | FRC_TIMER | — | **missing** | | RTC_CNTL | `esp32-rtc` | modelled | -| RTC_IO | — | **missing** | +| RTC_IO | `esp32-rtcio` | modelled | | SENS | `esp32-sens` | modelled | | RTC_I2C | — | **missing** | | IO_MUX | `esp32-iomux` | modelled | @@ -73,7 +73,7 @@ Boards: ESP32-DevKitC V4. | I2S1 | — | **missing** | | UART2 | `esp32-uart` | modelled | -Declared omissions: Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written); the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept; PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts; RMT: the memory's power-down (MEM_PD), STATUS's STATE and the APB-side error bits, the carrier on an idle output; the SAR ADCs: the nonlinearity above about 2450 mV at 11 dB and a chip's spread from the fitted line, noise, the ULP's and the digital controller's (DMA, I2S) conversions, the Hall sensor, ADC2's arbitration with Wi-Fi, the RTC IO MUX's routing of a pad to the ADC (not checked); I2C: the non-FIFO mode (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, the input filters (only their share of the SCL high time), 10-bit addressing's R/W check; the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, the DACs, the touch sensor, the RTC IO MUX and the ULP coprocessor, the AES and RSA accelerators, flash encryption; sleep modes (light and deep sleep, the power domains), brown-out; the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection. +Declared omissions: Wi-Fi, Bluetooth and the RF front end (WIFI_MAC, BB, NRX, FE: their registers keep what is written); the double-precision accelerator's instructions (F64ADDC, F64ITER and the others: their encodings are public, not what they do; a program that runs one stops with a diagnostic), though its registers are kept; PSRAM (DRAM1), the boot remap, the APB/AHB access permissions, the caches' lock regions and timing (the mapped pages are read whole), the MMU's access-error interrupts; RMT: the memory's power-down (MEM_PD), STATUS's STATE and the APB-side error bits, the carrier on an idle output; the SAR ADCs: the nonlinearity above about 2450 mV at 11 dB and a chip's spread from the fitted line, noise, the ULP's and the digital controller's (DMA, I2S) conversions, the Hall sensor, ADC2's arbitration with Wi-Fi, the RTC IO MUX's routing of a pad to the ADC (not checked); the DACs: the cosine-wave generator and the DMA path (I2S0), the output's impedance (a stiff source: the datasheet gives none) and its offset and nonlinearity; I2C: the non-FIFO mode (NONFIFO_EN, RX_REC_FULL, TX_SEND_EMPTY), SAMPLE_SCL_LEVEL, the input filters (only their share of the SCL high time), 10-bit addressing's R/W check; the peripherals without a model yet: I2S0/1, SPI2/3 (HSPI, VSPI), MCPWM, PCNT, TWAI, SDMMC, EMAC, the touch sensor, the RTC IO MUX's other pads and the ULP coprocessor, the AES and RSA accelerators, flash encryption; sleep modes (light and deep sleep, the power domains), brown-out; the eFuse 3/4 coding scheme's check, BLOCK0's per-field write protection. ## ESP32-C3 (`espressif/esp32c3`) diff --git a/tests/vendor/esp-idf/examples/esp32_dac_oneshot/project.json b/tests/vendor/esp-idf/examples/esp32_dac_oneshot/project.json new file mode 100644 index 000000000..ba2de2ed0 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_dac_oneshot/project.json @@ -0,0 +1,61 @@ +{ + "schema_version": 1, + "kind": "project", + "name": "esp-idf-esp32_dac_oneshot", + "description": "ESP-IDF's dac/dac_oneshot on the ESP32-DevKitC V4: DAC1 on IO25 and DAC2 on IO26, read back by ADC2's channels 8 and 9 on the same pads, plugged into USB.", + "policy": "electrical", + "boards": [ + { + "id": "B1", + "board": "emblink/esp32_devkitc", + "layout": { + "x": 360, + "y": 120 + }, + "firmware": { + "image": "flash.bin", + "format": "bin" + } + } + ], + "components": [ + { + "id": "USB", + "component": "emblink/vsource", + "params": { + "kind": "dc", + "dc": 5 + }, + "layout": { + "x": 120, + "y": 160 + } + }, + { + "id": "GND1", + "component": "emblink/gnd", + "layout": { + "x": 120, + "y": 320 + } + } + ], + "nets": { + "GND": [ + "USB.-", + "GND1.GND", + "B1.GND1" + ], + "USB5V": [ + "USB.+", + "B1.VBUS" + ] + }, + "probes": [ + { + "id": "console", + "target": "serial:B1", + "kind": "serial" + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/examples/esp32_dac_oneshot/scenario.json b/tests/vendor/esp-idf/examples/esp32_dac_oneshot/scenario.json new file mode 100644 index 000000000..32a438554 --- /dev/null +++ b/tests/vendor/esp-idf/examples/esp32_dac_oneshot/scenario.json @@ -0,0 +1,42 @@ +{ + "schema_version": 1, + "kind": "scenario", + "name": "esp32_dac_oneshot", + "until": "3s", + "description": "dac/dac_oneshot on the ESP32: each DAC steps its code by 10 every 500 ms (DAC2 half a second behind), VDD3P3_RTC x code / 255 on its pad, and ADC2 (channels 8 and 9, GPIO25 and GPIO26, 12 dB) reads the pads every 100 ms. With this chip's Vref (1170 mV) ADC2's fitted line is a = 56320, b = 128 mV: code 10 (129.4 mV) reads 2, 20 reads 152, 30 reads 303, 40 reads 453, 50 (647.1 mV) reads 604. The example prints with a bare \\n.", + "inputs": [], + "assertions": [ + { + "id": "started", + "at": "1s", + "probe": "console", + "expect": { + "contains": "DAC channel 0 value: 2\tDAC channel 1 value: 0\n" + } + }, + { + "id": "steps", + "at": "2900ms", + "probe": "console", + "expect": { + "contains": "DAC channel 0 value: 152\tDAC channel 1 value: 2\n" + } + }, + { + "id": "steps2", + "at": "2900ms", + "probe": "console", + "expect": { + "contains": "DAC channel 0 value: 453\tDAC channel 1 value: 303\n" + } + }, + { + "id": "code50", + "at": "2900ms", + "probe": "console", + "expect": { + "contains": "DAC channel 0 value: 604\tDAC channel 1 value: 453\n" + } + } + ] +} \ No newline at end of file diff --git a/tests/vendor/esp-idf/run.py b/tests/vendor/esp-idf/run.py index 534bea08a..b07671e86 100644 --- a/tests/vendor/esp-idf/run.py +++ b/tests/vendor/esp-idf/run.py @@ -80,6 +80,7 @@ "esp32_real_time_stats": "examples/system/freertos/real_time_stats", "esp32_blink_strip": "examples/get-started/blink", "esp32_adc_oneshot_read": "examples/peripherals/adc/oneshot_read", + "esp32_dac_oneshot": "examples/peripherals/dac/dac_oneshot", } # the target an example is built for, when not the ESP32-C3 (its board in # examples//project.json), and the toolchain that target needs @@ -93,6 +94,7 @@ "esp32_real_time_stats": "esp32", "esp32_blink_strip": "esp32", "esp32_adc_oneshot_read": "esp32", + "esp32_dac_oneshot": "esp32", } TOOLCHAINS = {"esp32c3": "riscv32-esp-elf-gcc", "esp32": "xtensa-esp32-elf-gcc"} # examples built only for another's project (with examples//'s