newIP.md

Using IP Modules

1. Clock IP Core Usage

Open Vivado, click IP Catalog -> FPGA Features and Design -> Clocking, and double-click Clocking Wizard, as shown in the figure below.

Then, in the Clocking Wizard dialog box, change the IP core name to cpuclk and set it to use PLL clock, as shown in the figure below.

Click to switch to the Output Clocks tab, set the output frequency of clk_out1 to the required frequency, remove Reset and check locked, then click OK, as shown in the figure below.

The system will pop up a prompt dialog box, click the Generate button. At this time, a cpuclk.xci module will be generated in the corresponding directory.

2. Defining Program ROM

The instruction fetch unit contains a program ROM (Instruction ROM, IROM) that stores assembly programs. We need to use Vivado's built-in memory IP core Distributed Memory Generator to define IROM. The manual for this IP core can be found in Xilinx's online documentation pg063-dist-mem-gen.pdf

Under Vivado's Project Manager, click IP Catalog. Enter distributed in the search box and double-click Distributed Memory Generator, as shown in the figure below.

This will open the Distributed Memory Generator configuration dialog box. In this dialog box, change the component name to IROM and set the data depth and data width, as shown in the figure below.

IROM Configuration Description
This experiment needs to create a 64KB size IROM, so IROM contains a total of 16384 data units (data width is 32 bits), corresponding to 14 address lines.

After configuration is complete, click the "OK" button and "Generate" button in sequence. At this time, Vivado will generate an IROM module named IROM.xci in the current project.

Note that the IROM is not initialized at this time and does not contain any valid data internally. In order for the CPU to run assembly programs, we need to import the machine code generated by the assembler into the IROM.

The Distributed Memory Generator IP core supports importing initial data through .coe files. The syntax of .coe files is as follows:

memory_initialization_radix = 16;  // Indicates that the following data uses hexadecimal (supports 2, 8, 10, 16 bases)
memory_initialization_vector =     // Put data below, doesn't need to be full; data units are separated by commas
3c01ffff,
343cf000,
3401ff0f,
af810c04,
8c020000,
8c030004,
00000000,
......        
00000000;   // End with a semicolon

IP Core Addressing Method Description
Taking the .coe file shown above as an example, address 0 corresponds to the first data 0x3c01ffff, address 1 corresponds to the second data 0x343cf000, and so on.

According to the syntax shown above, copy the machine code generated by the assembler to the .coe file, save and close it, then copy it to the root directory of the project.

Then, in Vivado, double-click the IROM IP core just created, click to enter the RST & Initialization tab in the settings window, and import the .coe file, as shown in the figure below.

3. Defining Data RAM

Like IROM, DRAM is also implemented using Distributed Memory Generator.

The operation of establishing DRAM is generally similar to IROM, but there are 2 differences:

First, you need to set Memory Type to Single Port RAM, as shown in the figure below.

Second, you need to configure both input and output ports to Non Registered under the Port config tab, as shown in the figure below.

Note
Note that after configuring according to Figure 3-15, DRAM's read timing is asynchronous read, and write timing is synchronous write.