Processor.sv

module Processor(
	input logic Clock,
	input logic Reset,
	output logic [31:0] InstructionAddress,
	input logic [31:0] Instruction,
	output logic [31:0] BusAddress,
	inout logic [31:0] BusData,
	output logic BusRead,
	output logic BusWrite
	);
	
	logic PCLoad;
	
	logic [31:0] BranchDestination;
	
	logic[31:0] RegData1,RegData2,RegDataIn,
					ALUResult,ALUIn2,
					ImmediateData;
	
	logic[4:0] ReadReg1,ReadReg2,WriteReg;
	
	logic [31:0] ALUData1,ALUData2;
	
	//Single Bit Signals
	//Outcome Signals
	logic ALUZero,ALUNegative;
	
	//Control Signals
	logic	BranchEQ,
			BranchNEQ,
			BranchGRT,
			BranchLST,
			ReadFromBus,
			WriteToBus,
			ALUSrc,
			RegWrite;
			
	logic[3:0] ALUOp;
	
	//Pipelining
	typedef struct packed
	{
		logic [31:0] Instruction,InstructionAddress,ImmediateData,RegData1,RegData2,BranchDestination,ALUResult,BusData;
		logic [4:0] ReadReg1,ReadReg2,WriteReg;
		logic [3:0] ALUOp;
		logic BranchEQ,BranchNEQ,BranchGRT,BranchLST,
				ReadFromBus,WriteToBus,ALUSrc,RegWrite,
				ALUZero,ALUNegative;
	}pipeline;
	
	pipeline IFPipe,IDPipe,EXPipe,MEMPipe;
	
	//IFPipe
	always_ff@(posedge Clock,posedge Reset)
	begin
		if(Reset)
		begin
			IFPipe.InstructionAddress<=0;
			IFPipe.Instruction<=0;
		end else begin
			if(PCLoad)
			begin
				IFPipe.InstructionAddress<=0;
				IFPipe.Instruction<=0;
			end else begin
				IFPipe.InstructionAddress<=InstructionAddress;
				IFPipe.Instruction<=Instruction;
			end
		end
	end
	
	
	//IDPipe.Pipe
	always_ff@(posedge Clock,posedge Reset)
	begin
		if(Reset)
		begin
			IDPipe.InstructionAddress<=0;
			IDPipe.RegData1<=0;
			IDPipe.RegData2<=0;
			IDPipe.WriteReg<=0;
			IDPipe.ReadReg1<=0;
			IDPipe.ReadReg2<=0;
			IDPipe.ImmediateData<=0;
			IDPipe.BranchEQ<=0;
			IDPipe.BranchNEQ<=0;
			IDPipe.BranchGRT<=0;
			IDPipe.BranchLST<=0;
			IDPipe.ReadFromBus<=0;
			IDPipe.WriteToBus<=0;
			IDPipe.ALUSrc<=0;
			IDPipe.RegWrite<=0;
			IDPipe.ALUOp<=0;
		end else begin
			if(PCLoad)
			begin
				IDPipe.InstructionAddress<=0;
				IDPipe.RegData1<=0;
				IDPipe.RegData2<=0;
				IDPipe.WriteReg<=0;
				IDPipe.ReadReg1<=0;
				IDPipe.ReadReg2<=0;
				IDPipe.ImmediateData<=0;
				IDPipe.BranchEQ<=0;
				IDPipe.BranchNEQ<=0;
				IDPipe.BranchGRT<=0;
				IDPipe.BranchLST<=0;
				IDPipe.ReadFromBus<=0;
				IDPipe.WriteToBus<=0;
				IDPipe.ALUSrc<=0;
				IDPipe.RegWrite<=0;
				IDPipe.ALUOp<=0;
			end else begin
				IDPipe.InstructionAddress<=IFPipe.InstructionAddress;
				IDPipe.RegData1<=RegData1;
				IDPipe.RegData2<=RegData2;
				IDPipe.ImmediateData<=ImmediateData;
				IDPipe.ReadReg1<=ReadReg1;
				IDPipe.ReadReg2<=ReadReg2;
				IDPipe.WriteReg<=WriteReg;
				IDPipe.BranchEQ<=BranchEQ;
				IDPipe.BranchNEQ<=BranchNEQ;
				IDPipe.BranchGRT<=BranchGRT;
				IDPipe.BranchLST<=BranchLST;
				IDPipe.ReadFromBus<=ReadFromBus;
				IDPipe.WriteToBus<=WriteToBus;
				IDPipe.ALUSrc<=ALUSrc;
				IDPipe.RegWrite<=RegWrite;
				IDPipe.ALUOp<=ALUOp;
			end
		end
	end
	
	//EXPipe
	always_ff@(posedge Clock,posedge Reset)
	begin
		if(Reset)
		begin
			EXPipe.WriteReg<=0;
			EXPipe.BranchDestination<=0;
			EXPipe.ALUZero<=0;
			EXPipe.ALUNegative<=0;
			EXPipe.ALUResult<=0;
			EXPipe.RegData2<=0;
			EXPipe.BranchEQ<=0;
			EXPipe.BranchNEQ<=0;
			EXPipe.BranchGRT<=0;
			EXPipe.BranchLST<=0;
			EXPipe.ReadFromBus<=0;
			EXPipe.WriteToBus<=0;
			EXPipe.RegWrite<=0;
		end else begin
			if(PCLoad)
			begin
				EXPipe.WriteReg<=0;
				EXPipe.BranchDestination<=0;
				EXPipe.ALUZero<=0;
				EXPipe.ALUNegative<=0;
				EXPipe.ALUResult<=0;
				EXPipe.RegData2<=0;
				EXPipe.BranchEQ<=0;
				EXPipe.BranchNEQ<=0;
				EXPipe.BranchGRT<=0;
				EXPipe.BranchLST<=0;
				EXPipe.ReadFromBus<=0;
				EXPipe.WriteToBus<=0;
				EXPipe.RegWrite<=0;
			end else begin
				EXPipe.WriteReg<=IDPipe.WriteReg;
				EXPipe.BranchDestination<=BranchDestination;
				EXPipe.ALUZero<=ALUZero;
				EXPipe.ALUNegative<=ALUNegative;
				EXPipe.ALUResult<=ALUResult;
				EXPipe.RegData2<= ALUData2; //to solve the hazard
				EXPipe.BranchEQ<=IDPipe.BranchEQ;
				EXPipe.BranchNEQ<=IDPipe.BranchNEQ;
				EXPipe.BranchGRT<=IDPipe.BranchGRT;
				EXPipe.BranchLST<=IDPipe.BranchLST;
				EXPipe.WriteToBus<=IDPipe.WriteToBus;
				EXPipe.ReadFromBus<=IDPipe.ReadFromBus;
				EXPipe.RegWrite<=IDPipe.RegWrite;
			end
		end
	end
	
	//MEMPipe
	always_ff@(posedge Clock,posedge Reset)
	begin
		if(Reset)
		begin
			MEMPipe.ReadFromBus<=0;
			MEMPipe.RegWrite<=0;
			MEMPipe.WriteReg<=0;
			MEMPipe.BusData<=0;
			MEMPipe.ALUResult<=0;
		end else begin
			MEMPipe.ReadFromBus<=EXPipe.ReadFromBus;
			MEMPipe.RegWrite<=EXPipe.RegWrite;
			MEMPipe.WriteReg<=EXPipe.WriteReg;
			MEMPipe.BusData<=BusData;
			MEMPipe.ALUResult<=EXPipe.ALUResult;
		end
	end
	
	assign BranchDestination = IDPipe.ImmediateData * 2 + IDPipe.InstructionAddress;
	
	assign BusAddress = EXPipe.ALUResult;
	
	assign BusRead = EXPipe.ReadFromBus;
	
	assign BusWrite = EXPipe.WriteToBus;
	
	assign BusData =  EXPipe.ReadFromBus ? {32{1'bz}} :
							(EXPipe.WriteToBus ? EXPipe.RegData2 : {32{1'bz}});
							
	
	ProgramCounter PC(
		.Clock(Clock),
		.Reset(Reset),
		.Branch(PCLoad),
		.Move(EXPipe.BranchDestination),
		.Count(InstructionAddress));
		
	RegisterFile RF(
		.Clock(Clock),
		.RegWrite(MEMPipe.RegWrite),
		.ReadReg1(ReadReg1),
		.ReadReg2(ReadReg2),
		.WriteReg(MEMPipe.WriteReg),
		.ReadData1(RegData1),
		.ReadData2(RegData2),
		.WriteData(RegDataIn));
	
	ALU CPU(
		.Input1(ALUData1),
		.Input2(ALUIn2),
		.Output(ALUResult),
		.OpCode(IDPipe.ALUOp),
		.Zero(ALUZero),
		.Negative(ALUNegative));
		
	InstructionDecoder ID(
		.Instruction(IFPipe.Instruction),
		.ReadReg1(ReadReg1),
		.ReadReg2(ReadReg2),
		.WriteReg(WriteReg),
		.Immediate(ImmediateData),
		.OpCode());
	
	ControlLogic CL(
		.Instruction(IFPipe.Instruction),
		.BranchEQ(BranchEQ),
		.BranchNEQ(BranchNEQ),
		.BranchGRT(BranchGRT),
		.BranchLST(BranchLST),
		.MemtoReg(ReadFromBus),
		.ALUOp(ALUOp),
		.MemWrite(WriteToBus),
		.ALUSrc(ALUSrc),
		.RegWrite(RegWrite)
		);
	
	assign PCLoad	=(	EXPipe.ALUZero 		& 	EXPipe.BranchEQ 	)|
						 (~EXPipe.ALUZero 		& 	EXPipe.BranchNEQ )|
						 ( EXPipe.ALUNegative	&	EXPipe.BranchLST	)|
						 (~EXPipe.ALUNegative	&	EXPipe.BranchGRT );
	
	//ALU Signals
	assign ALUData1 = (EXPipe.WriteReg==IDPipe.ReadReg1 && EXPipe.WriteReg!=0 && EXPipe.RegWrite) ? ((EXPipe.ReadFromBus) ? BusData : EXPipe.ALUResult):
							(MEMPipe.WriteReg==IDPipe.ReadReg1 && MEMPipe.WriteReg!=0 && MEMPipe.RegWrite) ? RegDataIn :
							IDPipe.RegData1;
							
	assign ALUData2 = (EXPipe.WriteReg==IDPipe.ReadReg2 && EXPipe.WriteReg!=0 && EXPipe.RegWrite) ? ((EXPipe.ReadFromBus) ? BusData : EXPipe.ALUResult) :
							(MEMPipe.WriteReg==IDPipe.ReadReg2 && MEMPipe.WriteReg!=0 && MEMPipe.RegWrite) ? RegDataIn :
							IDPipe.RegData2;
	
	assign ALUIn2 = (IDPipe.ALUSrc) ? IDPipe.ImmediateData : ALUData2;
	
	//Register File Signals
	assign RegDataIn = (MEMPipe.ReadFromBus) ? MEMPipe.BusData : MEMPipe.ALUResult;
	
endmodule