32Bit_Computer/InstructionDecoder.sv.bak at master · Chrisake/32Bit_Computer · GitHub

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module InstructionDecoder(
	input logic[31:0] Instruction,
	output logic[4:0] ReadReg1,
	output logic[4:0] ReadReg2,
	output logic[4:0] WriteReg,
	output logic[11:0] Immediate,
	output logic[6:0] OpCode);

	assign OpCode = Instruction[6:0];

	always_comb
	begin
		ReadReg1=0;
		ReadReg2=0;
		WriteReg=0;

		//R-Type Instructions
		if(Instruction[6:0]==7'b0110011)
		begin
			ReadReg1=Instruction[19:15];
			ReadReg2=Instruction[24:20];
			WriteReg=Instruction[11:7];
		end

		//R&I-Type Instructions
		if(Instruction[6:0]==7'b0010011)
		begin
			if(Instruction[14:12==3'b001]) //It's R-Type Instruction
			begin
				ReadReg1=Instruction[19:15];
				ReadReg2=Instruction[24:20];
				WriteReg=Instruction[11:7];
			end else begin	//It's I-Type Instruction
				ReadReg1=Instruction[19:15];
				ReadReg2=0;
				WriteReg=Instruction[11:7];
			end
		end

		//I-Type Instructions
		if(Instruction[6:0]==7'b1110011 ||
			Instruction[6:0]==7'b0110111 ||
			Instruction[6:0]==7'b0010111 ||
			Instruction[6:0]==7'b0000011 ||
			Instruction[6:0]==7'b1100111)
		begin
			ReadReg1=Instruction[19:15];
			ReadReg2=0;
			WriteReg=Instruction[11:7];
		end

		//S-Type Instructions
		if(Instruction[6:0]==7'b0100011 ||
			Instruction[6:0]==7'b1100011)
		begin
			ReadReg1=Instruction[19:15];
			ReadReg2=Instruction[24:20];
			WriteReg=0;
		end

		//U-Type Instructions
		if(Instruction[6:0]==7'b1101111)
		begin
			ReadReg1=0;
			ReadReg2=0;
			WriteReg=Instruction[11:7];
		end
	end

endmodule