32Bit_Computer/InstructionDecoder.sv at master · Chrisake/32Bit_Computer · GitHub

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module InstructionDecoder(
	input logic[31:0] Instruction,
	output logic[4:0] ReadReg1,
	output logic[4:0] ReadReg2,
	output logic[4:0] WriteReg,
	output logic[31:0] Immediate,
	output logic[6:0] OpCode);

	assign OpCode = Instruction[6:0];

	always_comb //ReadReg 1&2 and WriteReg
	begin
		ReadReg1=0;
		ReadReg2=0;
		WriteReg=0;

		//R-Type Instructions
		if(Instruction[6:0]==7'b0110011)
		begin
			ReadReg1=Instruction[19:15];
			ReadReg2=Instruction[24:20];
			WriteReg=Instruction[11:7];
		end

		//R&I-Type Instructions
		if(Instruction[6:0]==7'b0010011)
		begin
			if(Instruction[14:12]==3'b001) //It's R-Type Instruction
			begin
				ReadReg1=Instruction[19:15];
				ReadReg2=Instruction[24:20];
				WriteReg=Instruction[11:7];
			end else begin	//It's I-Type Instruction
				ReadReg1=Instruction[19:15];
				ReadReg2=0;
				WriteReg=Instruction[11:7];
			end
		end

		//I-Type Instructions
		if(Instruction[6:0]==7'b1110011 ||
			Instruction[6:0]==7'b0010111 ||
			Instruction[6:0]==7'b0000011 ||
			Instruction[6:0]==7'b1100111)
		begin
			ReadReg1=Instruction[19:15];
			ReadReg2=0;
			WriteReg=Instruction[11:7];
		end

		if(Instruction[6:0]==7'b0110111)
		begin
			ReadReg1=0;
			ReadReg2=0;
			WriteReg=Instruction[11:7];
		end

		//S-Type Instructions
		if(Instruction[6:0]==7'b0100011 ||
			Instruction[6:0]==7'b1100011)
		begin
			ReadReg1=Instruction[19:15];
			ReadReg2=Instruction[24:20];
			WriteReg=0;
		end

		//U-Type Instructions
		if(Instruction[6:0]==7'b1101111)
		begin
			ReadReg1=0;
			ReadReg2=0;
			WriteReg=Instruction[11:7];
		end
	end


	always_comb //Immidiate formation
	begin
		Immediate={32{1'b0}};
		//I-Immediate
		if(Instruction[6:0]==7'b1110011 ||
			Instruction[6:0]==7'b0010011 ||
			Instruction[6:0]==7'b0000011 ||
			Instruction[6:0]==7'b1100111)
		begin
			Immediate[31:11]={21{Instruction[31]}};
			Immediate[10:5]=Instruction[30:25];
			Immediate[4:1]=Instruction[24:21];
			Immediate[0]=Instruction[20];
		end

		//S-Immediate
		if(Instruction[6:0]==7'b0100011)
		begin
			Immediate[31:11]={21{Instruction[31]}};
			Immediate[10:5]=Instruction[30:25];
			Immediate[4:1]=Instruction[11:8];
			Immediate[0]=Instruction[7];
		end

		//B-Immediate
		if(Instruction[6:0]==7'b1100011)
		begin
			Immediate[31:12]={20{Instruction[31]}};
			Immediate[11]=Instruction[7];
			Immediate[10:5]=Instruction[30:25];
			Immediate[4:1]=Instruction[11:8];
			Immediate[0]=0;
		end

		//U-Immediate
		if(Instruction[6:0]==7'b0110111 ||
			Instruction[6:0]==7'b0010111)
		begin
			Immediate[31]=Instruction[31];
			Immediate[30:12]=Instruction[30:12];
			Immediate[11:0]=12'b000000000000;
		end

		//J-Immediate
		if(Instruction[6:0]==7'b1101111)
		begin
			Immediate[31:20]={12{Instruction[31]}};
			Immediate[19:12]=Instruction[19:12];
			Immediate[11]=Instruction[20];
			Immediate[10:5]=Instruction[30:25];
			Immediate[4:1]=Instruction[24:21];
			Immediate[0]=1'b0;
		end
	end
endmodule