GPU.sv

module GPU_old (
	// Synchronization
	input logic Clock,
	input logic Reset,
	// VGA In-Out
	output logic hsync,
	output logic vsync,
	output logic[7:0] red,
	output logic[7:0] green,
	output logic[7:0] blue,
	output logic PxClock,
	output logic Blank,
	output logic Sync,
	// Video RAM Access
	output logic[19:0] RAMAddress,
	inout logic[15:0] RAMData,
	output logic RAMHB,
	output logic RAMLB,
	output logic RAMOE,
	output logic RAMWE,
	output logic RAMCE,
	// Bus Interface
	input logic [32:0] BusAddress,
	inout logic [32:0] BusData,
	input logic DataRead,
	input logic DataWrite,
	
	input logic [63:0] Instruction,
	input logic AddInstruction,
	output logic[2:0] InstructionsRemaining
	);
	
	logic PixelClock;
	
	logic [63:0] Instructions [7:0];
	logic [2:0] NE,NP;
	logic [63:0] CInstruction;
	logic [4:0] CRed,CGreen,CBlue;
	logic [2:0] COP;
	logic Clear;
	logic [9:0] CXS,CXE;
	logic [8:0] CYS,CYE;
	
	
	assign InstructionsRemaining=NE-NP;
	
	
	assign CRed=CInstruction[63:59];
	assign CGreen=CInstruction[58:54];
	assign CBlue=CInstruction[53:49];
	assign Clear=CInstruction[48];
	
	assign COP=CInstruction[47:45];
	assign CXS=CInstruction[44:35];
	assign CYS=CInstruction[34:26];
	assign CXE=CInstruction[25:16];
	
	assign CYE=CInstruction[15:7];
	
	always_ff@(posedge Clock)
	begin
		if(AddInstruction)
		begin
			if(NE+1!=NP)
			begin
				NE<=NE+1;
				Instructions[NE]=Instruction;
			end
		end
	end
	
	always_ff@(posedge Clock)
	begin
		if(~Finished)
		begin
			if(Initialized)
			begin
				if(GPUTime)
				begin
					if(~Clear)
					begin
						if(GPUX<639)
						begin
							GPUX<=GPUX+1;
						end
						else
						begin
							GPUX<=0;
							if(GPUY<479)
							begin
								GPUY<=GPUY+1;
							end
							else
							begin
								Finished<=1;
							end
						end
					end
					else
					begin
						case(COP)
							3'b000:
							begin
								if(GPUY<CYE)
									GPUY<=GPUY+1;
								else
									Finished<=1;
							end
							3'b001:
							begin
								if(GPUX<CXE)
									GPUX<=GPUX+1;
								else
									Finished<=1;
							end
							3'b010:
							begin
								if(GPUX<CXE)
								begin
									GPUX<=GPUX+1;
								end
								else
								begin
									if(GPUY<CYE)
									begin
										GPUY<=GPUY+1;
										GPUX<=CXS;
									end
									else
									begin
										Finished<=1;
									end
								end
							end
							default:Finished<=1;
						endcase
					end
				end
			end
			else
			begin
				Initialized<=1;
				if(Clear)
				begin
					GPUX<=CXS;
					GPUY<=CYS;
				end
				else
				begin
					GPUX<=0;
					GPUY<=0;
				end
			end
		end
		else
		begin
			if(NE!=NP)
			begin
				CInstruction=Instructions[NP];
				NP<=NP+1;
				Finished<=0;
				Initialized<=0;
			end
		end
	end
	
	
	//VGA Controller
	logic [9:0] col,line;
	logic [19:0] PixelAddress;
	assign PixelAddress[19]=0;
	assign PixelAddress[18:9]=col[9:0];
	assign PixelAddress[8:0]=line[8:0];
	
	//RAM signals
	assign RAMCE=0;
	assign RAMLB=0;
	assign RAMHB=0;
	
	//GPU Controller
	logic[19:0] GPUAddress;
	logic[15:0] GPUData;
	logic GPUWE;
	logic [9:0] GPUX,GPUY;
	
	assign GPUAddress[19]=0;
	assign GPUAddress[18:9]=GPUX[9:0];
	assign GPUAddress[8:0]=GPUY[8:0];
	assign GPUData[15:11]=CRed;
	assign GPUData[10:6]=CGreen;
	assign GPUData[5:0]=CBlue;

	assign GPUWE=~(~Finished&&Initialized&&GPUTime);
	
	logic Finished;
	logic Initialized;
	
	logic GPUTime;
	assign GPUTime=~((col<640 && line<480)||col>798);
	
	always_comb
	begin
		if(~GPUTime)
		begin
			RAMAddress[19]<=0;
			RAMAddress[18:0]<=PixelAddress;
			RAMData<=16'bzzzzzzzzzzzzzzzz;
			RAMOE<=0;
			RAMWE<=1;
		end
		else
		begin
			RAMAddress<=GPUAddress;
			RAMData<=GPUData;
			RAMOE<=1;
			RAMWE<=GPUWE;
		end
	end
	
	assign hsync=~(col>=656 && col<752);
	assign vsync=~(line>=491 && line<493);
	assign Sync=1;
	assign Blank=(col<640 && line<480);
	assign PxClock=PixelClock;
	
	always_ff @(negedge Clock,negedge Reset)
	begin
		if(~Reset)
		begin
			red<=0;
			green<=0;
			blue<=0;
		end
		else
		begin
			if(~PixelClock)
			begin
				if (col<640 && line<480)
				begin
					red[7:3]<=RAMData[15:11];
					red[2:0]<=3'b111;
					green[7:3]<=RAMData[10:6];
					green[2:0]<=3'b000;
					blue[7:3]<=RAMData[5:0];
					blue[2:0]<=3'b000;
				end
			end
		end
	end
	
	always_ff @(posedge Clock,negedge Reset)	//PixelClock
	begin
		if(~Reset)
		begin
			PixelClock<=0;
		end
		else
		begin
			PixelClock<=~PixelClock;
		end
	end
	
	always_ff @(posedge Clock,negedge Reset)	//Columns
	begin
		if(~Reset)
		begin
			col<=0;
		end
		else
		begin
			if (PixelClock)
			begin
				if(col<799)
					col<=col+1;
				else
					col<=0;
			end
		end
	end

	always_ff @(posedge Clock,negedge Reset)	//lines
	begin
		if(~Reset)
		begin
			line<=0;
		end
		else
		begin
			if (PixelClock)
			begin
				if(col==799) begin
					if(line==523)
						line<=0;
					else
						line<=line+1;
				end
			end
		end
	end
endmodule