Computer_wo_Pipelining.sv

module Computer(
	input logic Clock,
	input logic[17:0] SW,
	input logic[3:0] KEY,
	output logic[17:0] RLED,
	output logic[8:0] GLED,
	output logic[7:0] HEX[7:0]
	);
	
	logic[31:0] InstructionAddress,Instruction,InstructionWriteAddress,InstructionWriteData,
					RegData1,RegData2,RegDataIn,
					ALUResult,ALUIn2,
					MemData,
					ImmediateData;
	
	logic[4:0] ReadReg1,ReadReg2,WriteReg;
	
	//Single Bit Signals
	//Outcome Signals
	logic ALUZero;
	
	//Control Signals
	logic	Branch,
			MemRead,
			MemtoReg,
			MemWrite,
			ALUSrc,
			RegWrite;
	
	logic[3:0] ALUOp;
	
	//UI Signals
	logic clk,
			Reset,
			ImmediateShow,
			ManualClock,
			HighManualClock,
			LowManualClock,
			InstructionWrite,
			RegisterShow;
	
	logic [3:0] ClockReduction;
	
	logic [31:0] InputAddress,InputData,HEXNumber,OutputRegister;
		
	logic [1:0] Address,Data;
	
	assign RLED[14:0] = {WriteReg,ReadReg1,ReadReg2}; 
	
	assign RLED[17:15] = ALUOp[2:0];
	
	assign GLED[6:0]={RegWrite,ALUSrc,MemWrite,MemtoReg,MemRead,Branch,ALUZero};
	
	always_ff@(posedge Clock)
	begin
		ClockReduction<=ClockReduction+1;
	end
	
	always_ff@(posedge Clock)
	begin
		if(HighManualClock)
		begin
			ManualClock<=1;
		end else begin
			if(LowManualClock)
			begin
				ManualClock<=0;
			end
		end
	end
	
	always_ff@(posedge Clock)
	begin
		if(SW[17])//Programming Mode
		begin
			if(KEY[3]==0)//Upper 16-bit
			begin
				if(SW[16])//Data Mode
				begin
					Data[1]<=1;
				end else begin//Address Mode
					Address[1]<=1;
				end
			end else begin
				if(KEY[2]==0)
				begin//Lower 16-bit
					if(SW[16])//Data Mode
					begin
						Data[0]<=1;
					end else begin//Address Mode
						Address[0]<=1;
					end
				end
			end
			if(KEY[1]==0)
			begin
				Data<=0;
				Address<=0;
			end
		end
	end
	
	always_ff@(posedge Clock)
	begin
		if(SW[17])//Programming Mode
		begin
			if(KEY[3]==0)//Upper 16-bit
			begin
				if(SW[16])//Data Mode
				begin
					InputData[31:16]<=SW[15:0];
				end else begin//Address Mode
					InputAddress[31:16]<=SW[15:0];
				end
			end else begin
				if(KEY[2]==0)
				begin//Lower 16-bit
					if(SW[16])//Data Mode
					begin
						InputData[15:0]<=SW[15:0];
					end else begin//Address Mode
						InputAddress[15:0]<=SW[15:0];
					end
				end
			end
		end
	end
	
	always_comb
	begin
		if(SW[17])		//Programming Mode
		begin
			HEXNumber = SW[16] ? InputData : InputAddress;
			InstructionWriteAddress=InputAddress;
			InstructionWriteData=InputData;
			InstructionWrite=~KEY[1];
			Reset=~KEY[0];
			HighManualClock=0;
			LowManualClock=0;
			ImmediateShow=0;
			RegisterShow=0;
			clk = 0;
		end else begin	//Running Mode
			if(SW[16])
			begin
				clk=Clock;//ClockReduction[3];
				HighManualClock=0;
				LowManualClock=0;
				Reset=~KEY[0];
			end else begin
				HighManualClock=~KEY[0];
				LowManualClock=~KEY[1];
				clk=ManualClock;
				Reset=0;
			end
			ImmediateShow = ~KEY[2];
			RegisterShow = ~KEY[3];
			HEXNumber = RegisterShow & ImmediateShow ? ALUResult:
							RegisterShow ? OutputRegister :
							ImmediateShow ? ImmediateData : 
							InstructionAddress;
			InstructionWriteAddress={32{1'b0}};
			InstructionWriteData={32{1'b0}};
			InstructionWrite=0;
		end
	end
	
	HEXDisplay Disp7(
		.I(HEXNumber[31:28]),
		.O(HEX[7]));
		
	HEXDisplay Disp6(
		.I(HEXNumber[27:24]),
		.O(HEX[6]));
		
	HEXDisplay Disp5(
		.I(HEXNumber[23:20]),
		.O(HEX[5]));
		
	HEXDisplay Disp4(
		.I(HEXNumber[19:16]),
		.O(HEX[4]));
		
	HEXDisplay Disp3(
		.I(HEXNumber[15:12]),
		.O(HEX[3]));
	
	HEXDisplay Disp2(
		.I(HEXNumber[11:8]),
		.O(HEX[2]));
		
	HEXDisplay Disp1(
		.I(HEXNumber[7:4]),
		.O(HEX[1]));
		
	HEXDisplay Disp0(
		.I(HEXNumber[3:0]),
		.O(HEX[0]));
	
	ProgramCounter PC(
		.Clock(clk),
		.Reset(Reset),
		.Branch(Branch & ALUZero),
		.Move(ImmediateData * 2),
		.Count(InstructionAddress));
		
	InstructionMemoryStatic IM(
		.Clock(clk),
		.ReadAddress(InstructionAddress),
		.ReadInstruction(Instruction)//,
		//.WriteAddress(InstructionWriteAddress),
		//.WriteInstruction(InstructionWriteData),
		//.InstructionWrite(InstructionWrite)
		);
	
	RegisterFile RF(
		.Clock(clk),
		.RegWrite(RegWrite),
		.ReadReg1(ReadReg1),
		.ReadReg2(ReadReg2),
		.ReadReg3(SW[4:0]),
		.WriteReg(WriteReg),
		.ReadData1(RegData1),
		.ReadData2(RegData2),
		.ReadData3(OutputRegister),
		.WriteData(RegDataIn));
	
	ALU CPU(
		.Input1(RegData1),
		.Input2(ALUIn2),
		.Output(ALUResult),
		.OpCode(ALUOp),
		.Zero(ALUZero));
		
	DataMemory DM(
		.Clock(clk),
		.Address(ALUResult),
		.DataIn(RegData2),
		.DataOut(MemData),
		.MemWrite(MemWrite));
	
	InstructionDecoder ID(
		.Instruction(Instruction),
		.ReadReg1(ReadReg1),
		.ReadReg2(ReadReg2),
		.WriteReg(WriteReg),
		.Immediate(ImmediateData),
		.OpCode());
	
	ControlLogic CL(
		.Instruction(Instruction),
		.Branch(Branch),
		.MemtoReg(MemtoReg),
		.ALUOp(ALUOp),
		.MemWrite(MemWrite),
		.ALUSrc(ALUSrc),
		.RegWrite(RegWrite));
	
	//ALU Signals
	assign ALUIn2 = (ALUSrc) ? ImmediateData : RegData2;
	
	//Register File Signals
	assign RegDataIn = (MemtoReg) ? MemData : ALUResult;
	
	
endmodule