Computer_w_Pipelining.sv

module Computer(
	input logic Clock,
	input logic[17:0] SW,
	input logic[3:0] KEY,
	output logic[17:0] RLED,
	output logic[8:0] GLED,
	output logic[7:0] HEX[7:0]
	);
	
	logic[31:0] InstructionAddress,Instruction,
					RegData1,RegData2,RegDataIn,
					ALUResult,ALUIn2,
					MemData,
					ImmediateData;
	
	logic[4:0] ReadReg1,ReadReg2,WriteReg;
	
	//Single Bit Signals
	//Outcome Signals
	logic ALUZero,ALUNegative;
	
	//Control Signals
	logic	BranchEQ,
			BranchNEQ,
			BranchGRT,
			BranchLST,
			MemtoReg,
			MemWrite,
			ALUSrc,
			RegWrite;
	
	logic[3:0] ALUOp;
	
	//UI Signals
	logic clk,
			Reset,
			ImmediateShow,
			MatoClock,
			HighManualClock,
			LowManualClock,
			RegisterShow;
			
	
	//Pipelining
	//IFPipe
	logic [31:0] IFInstructionAddress,IFImmediateData;
	logic [4:0] IFReadReg1,IFReadReg2,IFWriteReg;
	logic [3:0] IFALUOp;
	logic IFBranchEQ,IFBranchNEQ,IFBranchGRT,IFBranchLST,
			IFMemtoReg,IFMemWrite,IFALUSrc,IFRegWrite;
	always_ff@(posedge clk,posedge Reset)
	begin
		if(Reset)
		begin
			IFInstructionAddress<=0;
			IFImmediateData<=0;
			IFReadReg1<=0;
			IFReadReg2<=0;
			IFWriteReg<=0;
			IFBranchEQ<=0;
			IFBranchNEQ<=0;
			IFBranchGRT<=0;
			IFBranchLST<=0;
			IFMemtoReg<=0;
			IFMemWrite<=0;
			IFALUSrc<=0;
			IFRegWrite<=0;
			IFALUOp<=0;
		end else begin
			if(PCLoad)
			begin
				IFInstructionAddress<=0;
				IFImmediateData<=0;
				IFReadReg1<=0;
				IFReadReg2<=0;
				IFWriteReg<=0;
				IFBranchEQ<=0;
				IFBranchNEQ<=0;
				IFBranchGRT<=0;
				IFBranchLST<=0;
				IFMemtoReg<=0;
				IFMemWrite<=0;
				IFALUSrc<=0;
				IFRegWrite<=0;
				IFALUOp<=0;
			end else begin
				IFInstructionAddress<=InstructionAddress;
				IFImmediateData<=ImmediateData;
				IFReadReg1<=ReadReg1;
				IFReadReg2<=ReadReg2;
				IFWriteReg<=WriteReg;
				IFBranchEQ<=BranchEQ;
				IFBranchNEQ<=BranchNEQ;
				IFBranchGRT<=BranchGRT;
				IFBranchLST<=BranchLST;
				IFMemtoReg<=MemtoReg;
				IFMemWrite<=MemWrite;
				IFALUSrc<=ALUSrc;
				IFRegWrite<=RegWrite;
				IFALUOp<=ALUOp;
			end
		end
	end
	
	
	//IOPipe
	logic [31:0] IOInstructionAddress,IORegData1,IORegData2,IOImmediateData;
	logic [4:0] IOWriteReg,IOReadReg1,IOReadReg2;
	logic [3:0] IOALUOp;
	logic IOBranchEQ,IOBranchNEQ,IOBranchGRT,IOBranchLST,
			IOMemtoReg,IOMemWrite,IOALUSrc,IORegWrite;
	always_ff@(posedge clk,posedge Reset)
	begin
		if(Reset)
		begin
			IOInstructionAddress<=0;
			IORegData1<=0;
			IORegData2<=0;
			IOWriteReg<=0;
			IOReadReg1<=0;
			IOReadReg2<=0;
			IOImmediateData<=0;
			IOBranchEQ<=0;
			IOBranchNEQ<=0;
			IOBranchGRT<=0;
			IOBranchLST<=0;
			IOMemtoReg<=0;
			IOMemWrite<=0;
			IOALUSrc<=0;
			IORegWrite<=0;
			IOALUOp<=0;
		end else begin
			if(PCLoad)
			begin
				IOInstructionAddress<=0;
				IORegData1<=0;
				IORegData2<=0;
				IOWriteReg<=0;
				IOReadReg1<=0;
				IOReadReg2<=0;
				IOImmediateData<=0;
				IOBranchEQ<=0;
				IOBranchNEQ<=0;
				IOBranchGRT<=0;
				IOBranchLST<=0;
				IOMemtoReg<=0;
				IOMemWrite<=0;
				IOALUSrc<=0;
				IORegWrite<=0;
				IOALUOp<=0;
			end else begin
				IOInstructionAddress<=IFInstructionAddress;
				IORegData1<=RegData1;
				IORegData2<=RegData2;
				IOWriteReg<=IFWriteReg;
				IOReadReg1<=IFReadReg1;
				IOReadReg2<=IFReadReg2;
				IOImmediateData<=IFImmediateData;
				IOBranchEQ<=IFBranchEQ;
				IOBranchNEQ<=IFBranchNEQ;
				IOBranchGRT<=IFBranchGRT;
				IOBranchLST<=IFBranchLST;
				IOMemtoReg<=IFMemtoReg;
				IOMemWrite<=IFMemWrite;
				IOALUSrc<=IFALUSrc;
				IORegWrite<=IFRegWrite;
				IOALUOp<=IFALUOp;
			end
		end
	end
	
	//EXPipe
	logic [31:0] EXBranchDestination,EXALUResult,EXRegData2;
	logic [4:0] EXWriteReg;
	logic EXALUZero,EXALUNegative,
			EXBranchEQ,EXBranchNEQ,EXBranchGRT,EXBranchLST,
			EXMemtoReg,EXMemWrite,EXRegWrite;
	always_ff@(posedge clk,posedge Reset)
	begin
		if(Reset)
		begin
			EXWriteReg<=0;
			EXBranchDestination<=0;
			EXALUZero<=0;
			EXALUNegative<=0;
			EXALUResult<=0;
			EXRegData2<=0;
			EXBranchEQ<=0;
			EXBranchNEQ<=0;
			EXBranchGRT<=0;
			EXBranchLST<=0;
			EXMemtoReg<=0;
			EXRegWrite<=0;
		end else begin
			if(PCLoad)
			begin
				EXWriteReg<=0;
				EXBranchDestination<=0;
				EXALUZero<=0;
				EXALUNegative<=0;
				EXALUResult<=0;
				EXRegData2<=0;
				EXBranchEQ<=0;
				EXBranchNEQ<=0;
				EXBranchGRT<=0;
				EXBranchLST<=0;
				EXMemtoReg<=0;
				EXRegWrite<=0;
			end else begin
				EXWriteReg<=IOWriteReg;
				EXBranchDestination<=BranchDestination;
				EXALUZero<=ALUZero;
				EXALUNegative<=ALUNegative;
				EXALUResult<=ALUResult;
				EXRegData2<=IOData2; //to solve the hazard
				EXBranchEQ<=IOBranchEQ;
				EXBranchNEQ<=IOBranchNEQ;
				EXBranchGRT<=IOBranchGRT;
				EXBranchLST<=IOBranchLST;
				EXMemtoReg<=IOMemtoReg;
				EXRegWrite<=IORegWrite;
			end
		end
	end
	
	//MEMPipe
	logic MEMMemtoReg,MEMRegWrite;
	logic [4:0] MEMWriteReg;
	logic [31:0] MEMMemData,MEMALUResult;
	always_ff@(posedge clk,posedge Reset)
	begin
		if(Reset)
		begin
			MEMMemtoReg<=0;
			MEMRegWrite<=0;
			MEMWriteReg<=0;
			MEMMemData<=0;
			MEMALUResult<=0;
		end else begin
			MEMMemtoReg<=EXMemtoReg;
			MEMRegWrite<=EXRegWrite;
			MEMWriteReg<=EXWriteReg;
			MEMMemData<=MemData;
			MEMALUResult<=EXALUResult;
		end
	end
	
	/*
	always_ff@(posedge clk)
	begin
		//				[87:56]					[55:51]		[50:46]		[45:41]		[40:9]			[8]		[7]			[6]			[5]		[4]			[3:0]
		IFPipe = {	InstructionAddress,	ReadReg1,	ReadReg2,	WriteReg,	ImmediateData,	Branch,	MemtoReg,	MemWrite,	ALUSrc,	RegWrite,	ALUOp};
	
		//				[141:110](PC)	[109:78]		[77:46]		[45:41](WriteReg)	[40:9](ImmediateData)	[8](Branch)	[7](MemtoReg)	[6](MemWrite)	[5](ALUSrc)	[4](RegWrite)	[3:0](ALUOp)
		IOPipe = {	IFPipe[87:56],	RegData1,	RegData2,	IFPipe[45:41],		IFPipe[40:9],	 			IFPipe[8],	IFPipe[7],		IFPipe[6],		IFPipe[5],	IFPipe[4],		IFPipe[3:0]};
	
		//				[106:102](WriteReg)	[101:70]					[69]		[68:37]		[36:5](RegData2)	[4](Branch)	[3](MemtoReg)	[2](MemWrite)	[1](ALUSrc)	[0](RegWrite)
		EXPipe = {	IOPipe[45:41],			BranchDestination,	ALUZero,	ALUResult,	IOPipe[77:46],		IOPipe[8],	IOPipe[7],		IOPipe[6],		IOPipe[5],	IOPipe[4]};
	end
	*/
	
	logic PCLoad;
	
	logic [3:0] ClockReduction;
	
	logic [31:0] InputAddress,InputData,HEXNumber,OutputRegister,BranchDestination;
		
	assign BranchDestination = IOImmediateData * 2 + IOInstructionAddress;
	
	assign RLED[14:0] = {IFWriteReg,IFReadReg1,IFReadReg2}; 
	
	assign RLED[17:15] = IFALUOp[2:0];
	
	assign GLED[5:0]={EXRegWrite,IOALUSrc,EXMemWrite,EXMemtoReg,EXBranchEQ,EXALUZero};
	
	always_ff@(posedge Clock)
	begin
		ClockReduction<=ClockReduction+1;
	end
	
	always_ff@(posedge Clock)
	begin
		if(SW[17])
		begin
			MatoClock<=~MatoClock;
		end else begin
			if(HighManualClock)
			begin
				MatoClock<=1;
			end else begin
				if(LowManualClock)
				begin
					MatoClock<=0;
				end
			end
		end
	end

	
	always_comb
	begin
		clk=MatoClock;//ClockReduction[3];
		HighManualClock=~KEY[0];
		LowManualClock=~KEY[1];
		RegisterShow = ~KEY[2];
		Reset=~KEY[3];
		HEXNumber = RegisterShow ? OutputRegister : InstructionAddress;
	end
	
	HEXDisplay Disp7(
		.I(HEXNumber[31:28]),
		.O(HEX[7]));
		
	HEXDisplay Disp6(
		.I(HEXNumber[27:24]),
		.O(HEX[6]));
		
	HEXDisplay Disp5(
		.I(HEXNumber[23:20]),
		.O(HEX[5]));
		
	HEXDisplay Disp4(
		.I(HEXNumber[19:16]),
		.O(HEX[4]));
		
	HEXDisplay Disp3(
		.I(HEXNumber[15:12]),
		.O(HEX[3]));
	
	HEXDisplay Disp2(
		.I(HEXNumber[11:8]),
		.O(HEX[2]));
		
	HEXDisplay Disp1(
		.I(HEXNumber[7:4]),
		.O(HEX[1]));
		
	HEXDisplay Disp0(
		.I(HEXNumber[3:0]),
		.O(HEX[0]));
	
	ProgramCounter PC(
		.Clock(clk),
		.Reset(Reset),
		.Branch(PCLoad),
		.Move(EXBranchDestination),
		.Count(InstructionAddress));
		
	InstructionMemoryStatic IM(
		.Clock(clk),
		.ReadAddress(InstructionAddress),
		.ReadInstruction(Instruction)//,
		//.WriteAddress(InstructionWriteAddress),
		//.WriteInstruction(InstructionWriteData),
		//.InstructionWrite(InstructionWrite)
		);
	
	RegisterFile RF(
		.Clock(clk),
		.RegWrite(MEMRegWrite),
		.ReadReg1(IFReadReg1),
		.ReadReg2(IFReadReg2),
		.ReadReg3(SW[4:0]),
		.WriteReg(MEMWriteReg),
		.ReadData1(RegData1),
		.ReadData2(RegData2),
		.ReadData3(OutputRegister),
		.WriteData(RegDataIn));
	
	ALU CPU(
		.Input1(IOData1),
		.Input2(ALUIn2),
		.Output(ALUResult),
		.OpCode(IOALUOp),
		.Zero(ALUZero),
		.Negative(ALUNegative));
		
	DataMemory DM(
		.Clock(clk),
		.Address(EXALUResult),
		.DataIn(EXRegData2),
		.DataOut(MemData),
		.MemWrite(EXMemWrite));
	
	InstructionDecoder ID(
		.Instruction(Instruction),
		.ReadReg1(ReadReg1),
		.ReadReg2(ReadReg2),
		.WriteReg(WriteReg),
		.Immediate(ImmediateData),
		.OpCode());
	
	ControlLogic CL(
		.Instruction(Instruction),
		.BranchEQ(BranchEQ),
		.BranchNEQ(BranchNEQ),
		.BranchGRT(BranchGRT),
		.BranchLST(BranchLST),
		.MemtoReg(MemtoReg),
		.ALUOp(ALUOp),
		.MemWrite(MemWrite),
		.ALUSrc(ALUSrc),
		.RegWrite(RegWrite));
	
	assign PCLoad	=(	EXALUZero 		& 	EXBranchEQ 	)|
						 (~EXALUZero 		& 	EXBranchNEQ )|
						 ( EXALUNegative	&	EXBranchLST	)|
						 (~EXALUNegative	&	EXBranchGRT );
	
	logic[31:0] IOData1,IOData2;
	
	
	
	//ALU Signals
	assign IOData1 = 	(EXWriteReg==IOReadReg1 & EXWriteReg!=0 & EXRegWrite) ? EXALUResult :
							(MEMWriteReg==IOReadReg1 & MEMWriteReg!=0 & MEMRegWrite) ? RegDataIn :
							IORegData1;
							
	assign IOData2 = 	(EXWriteReg==IOReadReg2 & EXWriteReg!=0 & EXRegWrite) ? EXALUResult :
							(MEMWriteReg==IOReadReg2 & MEMWriteReg!=0 & MEMRegWrite) ? RegDataIn :
							IORegData2;
	
	assign ALUIn2 = (IOALUSrc) ? IOImmediateData : IOData2;
	
	//Register File Signals
	assign RegDataIn = (MEMMemtoReg) ? MEMMemData : MEMALUResult;
	
	
endmodule