32Bit_Computer/ALU.sv at master · Chrisake/32Bit_Computer · GitHub

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module ALU(
	input signed [31:0] Input1,
	input signed [31:0] Input2,
	output logic[31:0] Output,
	input logic[3:0] OpCode,
	output logic Zero,
	output logic Negative);

	assign Zero = Output==0;
	assign Negative = Output[31];

	always_comb
	begin
		case(OpCode)
			4'b0000: Output = Input1 + Input2;
			4'b0001: Output = Input1 - Input2;
			4'b0010: Output = Input1 & Input2;
			4'b0011: Output = Input1 | Input2;
			4'b0100: Output = Input1 ^ Input2;
			4'b0101: Output = Input1 * Input2;
			4'b0110: Output = Input1 >>> Input2[4:0];
			4'b0111: Output = Input1 >> Input2[4:0];
			4'b1000: Output = Input1 << Input2[4:0];
			default: Output = 0;
		endcase
	end

endmodule